A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a functional device setting area, a main display area, a first sub-pixel in the main display area, and a second sub-pixel in the functional device setting area. The density of the first sub-pixel in the main display area is greater than the density of the second sub-pixel in the functional device setting area. The display panel further comprises a scanning signal line extending at least partially along a first direction. A second pixel circuit of each of the plurality of second sub-pixels comprises a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit and the second sub-circuit are connected to the same scanning signal line. The scanning signal line connected to the second sub-circuit and the scanning signal line connected to the third sub-circuit are arranged adjacently. In a second direction, the center distance between the first sub-circuit and the second sub-circuit is a first distance, and the center distance between the second sub-circuit and the third sub-circuit is a second distance. The first distance is less than the second distance, which can ensure the light transmittance and the display effect of the functional device setting area.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] As users' demands for diverse uses of display devices increase, non-display devices may be embedded in the display area, or display devices may be embedded in the functional area. The display area of ​​a display device may contain both display and non-display devices. How to balance ensuring the light transmittance and display effect of the functional device area has become an important issue of concern for researchers. Summary of the Invention

[0003] This application provides a display panel and a display device to balance the light transmittance of the functional device setting area and the display effect.

[0004] According to one aspect of this application, a display panel is provided, comprising: a functional device setting area and a main display area that at least partially surrounds the functional device setting area; The display panel also includes a plurality of first sub-pixels and a plurality of second sub-pixels; the first sub-pixel includes a first light-emitting device and a first pixel circuit located in the main display area; the second sub-pixel includes a second light-emitting device and a second pixel circuit located in the functional device setting area; the density of the first sub-pixels in the main display area is greater than the density of the second sub-pixels in the functional device setting area; The display panel also includes at least a portion of scan signal lines extending along the first direction; The multiple second pixel circuits include a first sub-circuit, a second sub-circuit, and a third sub-circuit; the first sub-circuit and the second sub-circuit are connected to the same scan signal line, and the scan signal lines connected to the second sub-circuit and the scan signal lines connected to the third sub-circuit are arranged adjacent to each other. Along the second direction, the center distance between the first sub-circuit and the second sub-circuit is the first distance, and the center distance between the second sub-circuit and the third sub-circuit is the second distance. The first distance is less than the second distance. The first direction intersects the second direction, and both the first direction and the second direction are parallel to the plane where the display panel is located.

[0005] According to another aspect of this application, a display device is provided, including the aforementioned display panel.

[0006] The technical solution of this application, by placing the second light-emitting device in the functional device setting area, enables the functional device setting area to also display the image. Placing the second pixel circuit, which is electrically connected to the second light-emitting device, in the functional device setting area also helps reduce film layer setup and fabrication processes, thus lowering production costs. Simultaneously, reducing the density of the second sub-pixels in the functional device setting area helps increase the light transmittance of the functional device setting area and optimizes the layout of signal lines, simplifying the design of signal lines. Furthermore, since the first distance is smaller than the second distance, the center distance of the second pixel circuits connected to the same scanning signal line in the second direction can be reduced, which helps reduce the bending degree of the scanning signal line in the functional device setting area, thereby reducing design difficulty and improving product yield.

[0007] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a top view of a display panel structure in related technologies; Figure 2 This is a top view of the structure of the first type of display panel provided in this application embodiment; Figure 3 This is a top view of the structure of the second type of display panel provided in this application embodiment; Figure 4 This is a schematic diagram of the circuit structure of a second pixel circuit provided in an embodiment of this application; Figure 5 This is a top view schematic diagram of a second pixel circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the active structure of a second pixel circuit provided in an embodiment of this application; Figure 7 This is a top view of the third type of display panel provided in the embodiments of this application; Figure 8 This is a top view of the fourth type of display panel provided in the embodiments of this application; Figure 9 This is a top view of the fifth type of display panel provided in the embodiments of this application; Figure 10 This is a top view of the sixth type of display panel provided in this application embodiment; Figure 11 This is a top view of the seventh type of display panel provided in the embodiments of this application; Figure 12 This is a partial top view of the first type of functional device setting area provided in the embodiments of this application; Figure 13 This is a partial cross-sectional structural diagram of the first type of functional device setting area provided in the embodiments of this application; Figure 14 This is a schematic diagram of the structure of the first metal conductive layer of a second pixel circuit provided in an embodiment of this application; Figure 15 This is a schematic diagram of the structure of the second metal conductive layer of a second pixel circuit provided in an embodiment of this application; Figure 16 This is a schematic diagram of the structure of the third metal conductive layer of a second pixel circuit provided in an embodiment of this application; Figure 17 This is a top view schematic diagram of the stacked first to third metal conductive layers of a second pixel circuit provided in an embodiment of this application; Figure 18 This is a partial top view of the structure of the second type of functional device setting area provided in the embodiments of this application; Figure 19 This is a top view of the eighth type of display panel provided in this application embodiment; Figure 20 This is a partial top view of the structure of the third type of functional device setting area provided in the embodiments of this application; Figure 21 This is a partial cross-sectional structural diagram of the second type of functional device setting area provided in the embodiments of this application; Figure 22 This is a top view of the ninth type of display panel provided in this application embodiment; Figure 23 This is a partial top view of the fourth type of functional device setting area provided in the embodiments of this application; Figure 24 This is a schematic diagram of the structure of the fourth metal conductive layer of a second pixel circuit provided in an embodiment of this application; Figure 25 This is a top view of the tenth type of display panel provided in this application embodiment; Figure 26 This is a partial cross-sectional structural diagram of the third type of functional device setting area provided in the embodiments of this application; Figure 27This is a partial top view of the fifth type of functional device setting area provided in the embodiments of this application; Figure 28 This is a schematic diagram of the structure of the transparent conductive layer of a second pixel circuit provided in an embodiment of this application; Figure 29 This is a schematic diagram of the structure of a light-shielding layer in a functional device setting area provided in an embodiment of this application; Figure 30 This is a partial cross-sectional structural diagram of the fourth type of display panel provided in the embodiments of this application; Figure 31 This is a schematic diagram of the structure of the second electrode layer in a functional device setting area provided in an embodiment of this application; Figure 32 This is a partial cross-sectional structural diagram of the fifth type of functional device setting area provided in the embodiments of this application; Figure 33 This is a partial cross-sectional structural diagram of the sixth type of functional device setting area provided in the embodiments of this application; Figure 34 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0011] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0012] Figure 1 This is a top view structural diagram of a display panel in related technologies, for reference. Figure 1In related technologies, the display panel 001' includes a main display area A01' and a functional device setting area A02'; the display panel 001 also includes multiple sub-pixels P', each sub-pixel P' including a light-emitting device D' and a pixel circuit PC'. The display panel 001 also includes multiple scan signal lines SL, and the multiple second pixel circuits PC2 located in the functional device setting area A02' include a first sub-circuit PC_1', a second sub-circuit PC_2', and a third sub-circuit PC_3'. The first sub-circuit PC_1' and the second sub-circuit PC_2' are connected to the same scan signal line SL', and the scan signal line SL' connected to the second sub-circuit PC_2 and the scan signal line SL' connected to the third sub-circuit PC_3 are arranged adjacently, that is, the third sub-circuit PC_3' and the second sub-circuit PC_2' are respectively connected to different and adjacent scan signal lines SL'. Along the second direction Y, the center distance between the first sub-circuit PC_1' and the second sub-circuit PC_2' is the first distance S1', and the center distance between the second sub-circuit PC_2' and the third sub-circuit PC_3' is the second distance S2'. The first distance S1' is greater than or equal to the second distance S2'. The first direction X intersects the second direction Y, and both the first direction X and the second direction Y are parallel to the plane where the display panel 001' is located.

[0013] Continue to refer to Figure 1 The scan signal line SL' located in the main display area A01' can extend along the first direction X, and the extension direction of the scan signal line SL' located in the functional device setting area A02' can intersect with the first direction X. When the scan signal line SL' located in the functional device setting area A02' changes, the angle between the extension direction before the change and the extension direction after the change is the bending angle α', which can also be called the turning angle α'. When the extension direction of the scan signal line SL changes multiple times, there can be multiple turning angles α'. In related technologies, the first distance S1' is greater than or equal to the second distance S2'. A larger first distance S1' results in a larger angle between the extension direction of the scan signal line SL' located in the functional device setting area A02' and the first direction X. When the extension direction of the scan signal line SL' changes continuously, the angles between the extension direction before and after the change and the first direction X are both large, resulting in a larger bending angle α' of the scan signal line SL. This leads to smaller angles of the scan signal line SL before and after the change in extension direction, and a greater degree of bending of the scan signal line SL' in the functional device setting area A02'. When the degree of bending of the scan signal line SL' in the functional device setting area A02' is large, there are cases where the angles of the scan signal line SL' are sharp or dense. This makes it easy for deformation to occur during the fabrication of the scan signal line SL', causing open circuits or short circuits and affecting the reliability of the display panel 001.

[0014] Based on this, embodiments of this application provide a display panel, including: a functional device setting area and a main display area at least partially surrounding the functional device setting area; the display panel further includes a plurality of first sub-pixels and a plurality of second sub-pixels; the first sub-pixel includes a first light-emitting device and a first pixel circuit located in the main display area; the second sub-pixel includes a second light-emitting device and a second pixel circuit located in the functional device setting area; the density of the first sub-pixels in the main display area is greater than the density of the second sub-pixels in the functional device setting area; the display panel further includes at least a scan signal line extending along a first direction; the plurality of second pixel circuits include a first sub-circuit, a second sub-circuit, and a third sub-circuit; the first sub-circuit and the second sub-circuit are connected to the same scan signal line, and the scan signal line connected to the second sub-circuit and the scan signal line connected to the third sub-circuit are arranged adjacent to each other; along a second direction, the center distance between the first sub-circuit and the second sub-circuit is a first distance, and the center distance between the second sub-circuit and the third sub-circuit is a second distance, the first distance being less than the second distance; wherein, the first direction intersects the second direction, and both the first direction and the second direction are parallel to the plane where the display panel is located.

[0015] By adopting the above technical solution, the first distance can be made smaller than the second distance, reducing the center distance of the second pixel circuit connected to the same scanning signal line in the second direction, and reducing the bending degree of the scanning signal line in the functional device setting area. This helps to reduce design difficulty and improve product yield. The above is the core idea of ​​this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0016] It should be noted that the implementation methods provided in this application can be combined with each other without contradiction.

[0017] Figure 2 This is a top view of the structure of the first type of display panel provided in this application embodiment. Figure 3 This is a top view structural diagram of the second type of display panel provided in the embodiments of this application, with reference to... Figure 2 and Figure 3The display panel 001 includes a functional device setting area A02 and a main display area A01 that at least partially surrounds the functional device setting area A02. The display panel 001 also includes a plurality of first sub-pixels P01 and a plurality of second sub-pixels P02. The first sub-pixels P01 include a first light-emitting device D1 and a first pixel circuit PC1 located in the main display area A01. The second sub-pixels P02 include a second light-emitting device D2 and a second pixel circuit PC2 located in the functional device setting area A02. The density of the first sub-pixels P01 in the main display area A01 is greater than the density of the second sub-pixels P02 in the functional device setting area A02.

[0018] The first pixel circuit PC1 drives the first light-emitting device D1 to emit light for display, and the second pixel circuit PC2 drives the second light-emitting device D2 to emit light for display. The functional device setting area A02 also includes functional devices (…). Figure 2 and Figure 3 (Not shown in the image) In one embodiment, the functional device includes an image sensor capable of image capture, video recording, facial recognition, etc., and the functional device setting area A02 can be an under-display camera (CUP) area; in another embodiment, the functional device includes an optical sensor capable of fingerprint recognition, and the functional device setting area A02 can be an under-display fingerprint recognition area; in yet another embodiment, the functional device can be disposed on the backlight side of the second sub-pixel P02, and along a direction perpendicular to the plane of the display panel 001, the functional device and the second sub-pixel P02 do not overlap ( Figure 2 and Figure 3 (Not shown in the image).

[0019] Specifically, the second light-emitting device D2 is located in the functional device setting area A02, enabling the functional device setting area A02 to display images. The second pixel circuit PC2, which is electrically connected to the second light-emitting device D2, is also located in the functional device setting area A02. This helps to shorten the connection traces between the second light-emitting device D2 and the second pixel circuit PC2, improving the display effect and avoiding excessively long connection traces between the second light-emitting device D2 and the second pixel circuit PC2, which are easily affected by parasitic parameters and result in poor display effects in the functional device setting area A02. It also avoids placing the second pixel circuit PC2 in the edge area of ​​the main display area A01 near the functional device setting area A02, which would increase the number of signal lines in the functional device setting area A02. This would require multiple transparent conductive layers to form the signal lines in the functional device setting area A02 in order to reduce the impact of signal lines on light transmittance, thus increasing production processes and costs. In one embodiment, in the second sub-pixel P02, the orthographic projection of the second pixel circuit PC2 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second light-emitting device D2 on the plane where the display panel 001 is located. That is, the second pixel circuit PC2 and the second light-emitting device D2, which are electrically connected to each other along a direction perpendicular to the plane where the display panel 001 is located, overlap.

[0020] Compared to the density of the first sub-pixel P01 in the main display area A01, the density of the second sub-pixel P02 in the functional device setting area A02 is reduced. This increases the light transmittance of the functional device setting area A02, enabling it to perform functions other than display, such as under-display camera and under-display fingerprint recognition. Furthermore, reducing the number of second sub-pixels P02 in the functional device setting area A02 optimizes the layout of signal lines and simplifies their design. For example, an increased density of second sub-pixels P02 in the functional device setting area A02 occupies more wiring space, causing multiple signal lines to be densely packed in a narrow space. These lines may need to pass through vias on different conductive layers or be close together, increasing the risk of defects and parasitic interference. A reduced density of second sub-pixels P02 in the functional device setting area A02 provides ample wiring space, allowing for more rational placement of signal lines, simplifying wiring, and improving yield.

[0021] For example, the first light-emitting device D1 located in the main display area A01 and the second light-emitting device D2 located in the functional device setting area A02 both include a first-color light-emitting device LR, a second-color light-emitting device LG, and a third-color light-emitting device GB, to emit light of the first color R, the second color G, and the third color B. The density of the first sub-pixel P01 in the main display area A01 is relatively large, and the first pixel circuit PC1 can be arranged in an array (arranged sequentially along the row and column directions). The opening areas of the light-emitting devices of different colors are different. In order to avoid the overlapping of light-emitting devices of different colors along the direction perpendicular to the plane where the display panel 001 is located, the first light-emitting device D1 is not arranged in an array (adjacent first light-emitting devices D1 are arranged neither along the row nor along the column direction). The density of the second sub-pixel P02 in the functional device setting area A02 is relatively small. In order to increase light transmittance and reduce light diffraction, the arrangement of the second pixel circuit PC2 is different from that of the first pixel circuit PC1, and / or the arrangement of the second light-emitting device D2 is different from that of the first light-emitting device D1. For example, the second pixel circuit PC2 is not arrayed (there are adjacent second pixel circuits PC2 that are neither arranged along the row direction nor along the column direction).

[0022] It is understandable that the arrangement direction and arrangement method can be determined based on the center of the structure. The arrangement direction and arrangement method of the pixel circuit can be determined based on the center of the region where the pixel circuit is located (the region where the transistor, the active region of the transistor, or the active structure is located in the pixel circuit). The arrangement direction and arrangement method of the light-emitting device can be determined based on the center of the region where the light-emitting device is formed.

[0023] It should be noted that, Figure 2 and Figure 3 The illustrations only show two exemplary arrangements of pixel circuits and light-emitting devices, but are not limited thereto. The embodiments of this application do not limit the arrangement of pixel circuits and light-emitting devices in the main display area A01 and the functional device setting area A02.

[0024] It should also be noted that the structure of the pixel circuit is not limited in the embodiments of this application. The first pixel circuit PC1 includes, but is not limited to, pixel circuits such as 2T1C and 7T1C, and the second pixel circuit PC2 also includes, but is not limited to, pixel circuits such as 2T1C and 7T1C; the first pixel circuit PC1 and the second pixel circuit PC2 may be the same or different, and the embodiments of this application do not limit them.

[0025] Continue to refer to Figure 2 and Figure 3The display panel 001 also includes at least a scan signal line SL extending along the first direction X; a plurality of second pixel circuits PC2 include a first sub-circuit PC_1, a second sub-circuit PC_2, and a third sub-circuit PC_3. The first sub-circuit PC_1 and the second sub-circuit PC_2 are connected to the same scan signal line SL. The scan signal line SL connected to the second sub-circuit PC_2 and the scan signal line SL connected to the third sub-circuit PC_3 are arranged adjacently, that is, the third sub-circuit PC_3 and the second sub-circuit PC_2 are respectively connected to different and adjacent scan signal lines SL. Along the second direction Y, the center distance between the first sub-circuit PC_1 and the second sub-circuit PC_2 is a first distance S1, and the center distance between the second sub-circuit PC_2 and the third sub-circuit PC_3 is a second distance S2. The first distance S1 is less than the second distance S2. The first direction X intersects the second direction Y, and both the first direction X and the second direction Y are parallel to the plane where the display panel 001 is located.

[0026] Wherein, the first direction X can be the row direction of the display panel 001, and the second direction Y can be the column direction of the display panel 001. At least a portion of the scan signal lines SL can extend along the row direction, and different scan signal lines SL can be arranged along the column direction. The scan signal lines SL are used to transmit scan signals and provide scan signals to the pixel circuits electrically connected to the scan signal lines SL, controlling the conduction state of the transistors in the pixel circuits. The same scan signal line SL can connect multiple pixel circuits and control the conduction state of transistors at the same position or with the same function in these pixel circuits. Two adjacent scan signal lines SL are of the same type. Two adjacent scan signal lines SL can connect different pixel circuits and control the conduction state of transistors at the same position or with the same function in different pixel circuits. For example, multiple scan signal lines SL arranged in sequence can be used to transmit SP signals in sequence and provide SP signals to the gates of transistors at the same position in different pixel circuits. The i-th scan signal line SL can be used to transmit the i-th level SP signal, and the (i+1)-th adjacent scan signal line SL can be used to transmit the (i+1)-th level SP signal, where i is a positive integer less than the number of scan signal lines SL.

[0027] In one embodiment, some scan signal lines SL may be provided only in the main display area A01. First pixel circuits PC1 located in the same row (arranged along the row direction) may be connected to the same scan signal line SL, which may extend along the row direction. In another embodiment, some scan signal lines SL may be provided in the main display area A01 and the functional device setting area A02. Some second pixel circuits PC2 in the functional device setting area A02 may not be arranged along the row direction, but may still be connected to the same scan signal line SL. This scan signal line SL may also be connected to some first pixel circuits PC1 located in the same row in the main display area A01. The portion of the scan signal line SL in the main display area A01 may extend along the row direction, and at least the portion of the scan signal line SL in the functional device setting area A02 may extend in a direction intersecting the row direction, i.e., the scan signal line SL has a bend in the functional device setting area A02.

[0028] In the functional device setting area A02, the first sub-circuit PC_1 and the second sub-circuit PC_2 can be any two second pixel circuits PC2 connected to the same scan signal line SL, and the third sub-circuit PC_3 can be any second pixel circuit PC2 connected to the scan signal line SL that is adjacent to the scan signal line SL. There are multiple second pixel circuits PC2 connected to the same scan signal line SL. Among the multiple second pixel circuits PC2 connected to the same scan signal line SL, any two second pixel circuits PC2 are selected as the first sub-circuit PC_1 and the second sub-circuit PC_2, respectively. Along the second direction Y, the center distance between any two second pixel circuits PC2 can be different, that is, the first distance S1 can have multiple cases: for example, among the multiple second pixel circuits PC2 connected to the same scan signal line SL, when the two second pixel circuits PC2 with the largest center distance along the second direction Y are selected as the first sub-circuit PC_1 and the second sub-circuit PC_2, the center distance is the maximum value of the first distance S1; for example, among the multiple second pixel circuits PC2 connected to the same scan signal line SL, when the two second pixel circuits PC2 with the smallest center distance along the second direction Y are selected as the first sub-circuit PC_1 and the second sub-circuit PC_2, the center distance is the minimum value of the first distance S1.

[0029] Similarly, there are multiple second pixel circuits PC2 connected to the scan signal lines SL connected to the first sub-circuit PC_1 and the second sub-circuit PC_2. These second pixel circuits PC2 can be, for example, a first part of the second pixel circuits PC2. There are also multiple second pixel circuits PC2 connected to scan signal lines SL arranged adjacent to the scan signal lines SL connected to the first sub-circuit PC_1 and the second sub-circuit PC_2. These second pixel circuits PC2 can be, for example, a second part of the second pixel circuits PC2. Any one of the second pixel circuits PC2 in the first part of the second pixel circuits PC2 is selected as the second sub-circuit PC_2, and any one of the second pixel circuits PC2 in the second part of the second pixel circuits PC2 is selected as the third sub-circuit PC_1. When the selected second pixel circuits PC2 are different, the second distance S2 can be different: for example, in the first part of the second pixel circuits PC_1 and the second part of the second pixel circuits PC_2... In PC2, when the second pixel circuit PC2 furthest from the second pixel circuit PC2 in the second direction Y is selected as the second sub-circuit PC_2 and the second pixel circuit PC2 furthest from the first pixel circuit PC2 is selected as the third sub-circuit PC_3, the center distance between the second sub-circuit PC_2 and the third sub-circuit PC_3 in the second direction Y is the maximum value of the second distance S2. For example, in the first and second pixel circuits PC2, when the second pixel circuit PC2 closest to the second pixel circuit PC2 in the second direction Y is selected as the second sub-circuit PC_2 and the second pixel circuit PC2 closest to the first pixel circuit PC2 is selected as the third sub-circuit PC_3, the center distance between the second sub-circuit PC_2 and the third sub-circuit PC_3 in the second direction Y is the minimum value of the second distance S2.

[0030] Generally, the larger the first distance S1, the larger the angle between the arrangement direction of the first sub-circuit PC_1 and the second sub-circuit PC_2 and the first direction X, and the greater the bend in the scan signal line SL connecting the first sub-circuit PC_1 and the second sub-circuit PC_2; conversely, the smaller the first distance S1, the smaller the angle between the arrangement direction of the first sub-circuit PC_1 and the second sub-circuit PC_2 and the first direction X, and the less bend in the scan signal line SL connecting the first sub-circuit PC_1 and the second sub-circuit PC_2. Since the space in the functional device setting area A02 is limited, the first distance S1 and the second distance S2 are negatively correlated: the smaller the second distance S2, the larger the first distance S1; and vice versa.

[0031] It is understandable that the first distance S1 and the second distance S2 are both the center distances of the two second pixel circuits PC2. The center distance of the two second pixel circuits PC2 can be determined based on the center of the region where the second pixel circuit PC2 is located (the region where the transistor, the active region of the transistor, or the active structure of the second pixel circuit PC2 is located). Alternatively, the region where the second pixel circuit PC2 is located can be approximated as a regular shape, such as a circle, a rectangle, or a square, and the geometric center of this regular shape is the center of the pixel circuit.

[0032] Specifically, if the first distance S1 is less than the second distance S2, then any first distance S1 is less than any second distance S2. That is, the maximum value of the first distance S1 can be less than the minimum value of the second distance S2, which can limit the maximum value of the first distance S1 to a small range (less than the minimum value of the second distance S2). The maximum center distance between any two second pixel circuits PC2 connected to the same scan signal line SL in the second direction Y does not exceed the minimum value of the second distance S2. This can reduce the angle between the part of the scan signal line SL located in the functional device setting area A02 and the first direction X, reduce the degree of bending of the scan signal line SL in the functional device setting area A02, thereby reducing the design difficulty, improving the product yield, and avoiding excessive bending of the scan signal line SL in the functional device setting area A02, which would result in sharp or dense angles of the scan signal line SL in the functional device setting area A02. This would make the scan signal line SL prone to deformation during fabrication, causing open circuits or short circuits, and affecting the reliability of the display panel 001.

[0033] For example, a portion of the main display area A01 can be arranged along the first direction X with the functional device setting area A02. The scan signal line SL, which passes through the functional device setting area A02 and is electrically connected to the second pixel circuit PC2, also passes through the main display area A01 and is electrically connected to the first pixel circuit PC1. When this portion of the scan signal line SL is located in the main display area A01, it can extend along the first direction X and connect to the first pixel circuit PC arranged along the first direction X. In the functional device setting area A02, the arrangement of the second pixel circuit PC2 is different from that of the first pixel circuit PC1, and the extension direction of this portion of the scan signal line SL changes. The angle between the extension direction before the change and the extension direction after the change is the bending angle α, which can also be called the turning angle α. When the extension direction of the scan signal line SL changes multiple times, there can be multiple bending angles α. The turning angle α at different positions of the same scan signal line SL can be the same or different.

[0034] By setting a smaller first distance S1, the angle between the extension direction of the scan signal line SL in the functional device setting area A02 and the first direction X can be reduced. When the extension direction of the scan signal line SL changes, the angle between the extension direction of the scan signal line SL and the first direction X before and / or after the change in extension direction can be reduced, which helps to reduce the bending angle α of the scan signal line SL and reduce the degree of bending of the scan signal line SL in the functional device setting area A02. Thus, when designing the scan signal line SL in the functional device setting area A02, the bending angle α of the scan signal line SL is smaller, that is, the angle between the scan signal line SL before and after the change in extension direction is larger, closer to 180°. The angle position of the scan signal line SL before and after the change in extension direction is not easily deformed, and there is no need to consider the deformation problem caused by the angle of the scan signal line SL, which helps to reduce the design difficulty. At the same time, the larger angle of the scan signal line SL before and after the change in extension direction, and the less prone to deformation, can also reduce open circuits or short circuits, which helps to improve product yield and the reliability of the display panel 001.

[0035] For example, refer to Figure 2 and Figure 3 In the functional device setting area A02, multiple second pixel circuits PC2 connected to the same scan signal line SL are located at the angle between the scan signal line SL and the second pixel circuit PC2. Based on the orientation of the angle between the scan signal lines SL and the second pixel circuit PC2, these second pixel circuits PC2 can be divided into third-part second pixel circuits PC2 and fourth-part second pixel circuits PC2, for example... Figure 2 and Figure 3 In this diagram, the angle between the scanning signal line SL of the second pixel circuit PC2 connected to the second color light-emitting device LG and the scanning signal line SL of the second pixel circuit PC2 connected to the first color light-emitting device LR and the third color light-emitting device GB has a different orientation. Among the multiple second pixel circuits PC2 connected to the same scanning signal line SL, the center distance between the third and fourth part second pixel circuits PC2 is larger than the center distance between any two third part second pixel circuits PC2 or any two fourth part second pixel circuits PC2 along the second direction Y.

[0036] The first distance S1 can be reduced by decreasing the center distance between the third and fourth portions of the second pixel circuit PC2, which are connected to the same scan signal line SL, in the second direction Y. Among the multiple second pixel circuits PC2 connected to the same scan signal line SL, the third portion of the second pixel circuit PC2 can be moved closer to the fourth portion of the second pixel circuit PC2 along the second direction Y, and / or the fourth portion of the second pixel circuit PC2 can be moved closer to the third portion of the second pixel circuit PC2, that is... Figure 2 and Figure 3 The second pixel circuit PC2, which is connected to the second color light-emitting device LG, is moved in the downward direction shown in the figure, and / or, the second pixel circuit PC2 is moved in the downward direction shown in the figure. Figure 2 and Figure 3 The second pixel circuit PC2, which is connected to the first color light-emitting device LR and the third color light-emitting device GB, moves in the upward direction shown in the figure. This effectively reduces the first distance S1, thereby reducing the bending angle α of the scan signal line SL in the functional device setting area A02, reducing design difficulty, improving product yield and the reliability of the display panel 001.

[0037] In this embodiment, by placing the second light-emitting device in the functional device setting area, the functional device setting area can also display an image. Placing the second pixel circuit, which is electrically connected to the second light-emitting device, in the functional device setting area also helps reduce film layer setup and fabrication processes, thus lowering production costs. Simultaneously, reducing the density of the second sub-pixels in the functional device setting area helps increase the light transmittance of the functional device setting area and optimizes the layout of signal lines, simplifying the design of signal lines. Furthermore, since the first distance is smaller than the second distance, the center distance of the second pixel circuit PC2 connected to the same scanning signal line SL in the second direction Y can be reduced, which helps reduce the bending degree of the scanning signal line SL in the functional device setting area A02, thereby reducing design difficulty and improving product yield.

[0038] In an optional implementation, the scan signal line SL may include multiple signal lines of different types ( Figure 2 and Figure 3(Not shown in the image) are used to connect the gates of different transistors in the pixel circuit. For example, in the embodiments of this application, both the first pixel circuit PC1 and the second pixel circuit PC2 include a 7T1C circuit. The multiple signal lines included in the scan signal line SL can transmit signals such as SP signal and EMIT signal respectively. The pixel circuit can connect multiple signal lines simultaneously, and the multiple signal lines connected to the same pixel circuit can be arranged sequentially along the second direction Y. By reducing the bending degree of the scan signal line SL and reducing the bending angle α of the scan signal line SL, it is beneficial to reduce the distance between the multiple signal lines connected to the same pixel circuit in the second direction Y, increase the number of scan signal lines SL passing through the functional device setting area A02, increase the density of the second pixel circuit PC2 in the functional device setting area A02, and achieve high resolution in the functional device setting area A02.

[0039] For example, such as Figure 2 As shown, the first sub-circuit PC_1 and the third sub-circuit PC_3 are located in the same pixel circuit column, and the second sub-circuit PC_2 is located in the pixel circuit column adjacent to the first sub-circuit PC_1 and the third sub-circuit PC_3. In other examples, such as Figure 3 As shown, the first sub-circuit PC_1, the second sub-circuit PC_2, and the third sub-circuit PC_3 are located in three adjacent pixel circuit columns, respectively.

[0040] It is understood that in the embodiments of this application, the centers of the second pixel circuits corresponding to the second light-emitting devices of the same color are located on a straight line in each second pixel circuit connected to the same scanning signal line.

[0041] In an alternative embodiment, reference continues. Figure 2 and Figure 3 The color of the second light-emitting device D2 electrically connected to the first sub-circuit PC_1 is different from the color of the second light-emitting device D2 electrically connected to the second sub-circuit PC_2. The first sub-circuit PC_1 and the second sub-circuit PC_2 are arranged along a third direction X', which is parallel to the plane where the display panel 001 is located. The third direction X' intersects with the first direction X and the second direction Y. The color of the second light-emitting device D2 electrically connected to the first sub-circuit PC_1 is the same as the color of the second light-emitting device D2 electrically connected to the third sub-circuit PC_3.

[0042] For example, the first sub-circuit PC_1 and the second sub-circuit PC_2 are electrically connected to the second color light-emitting device LG and the first color light-emitting device LR, respectively. The arrangement direction (third direction X') of the first sub-circuit PC_1 and the second sub-circuit PC_2 intersects with the first direction X. This makes the first distance S1 greater than the center distance in the second direction Y of two second pixel circuits PC2 corresponding to the same color second light-emitting device D2 (e.g., first color light-emitting device LR and first color light-emitting device LR, second color light-emitting device LG and second color light-emitting device LG, third color light-emitting device LB and third color light-emitting device LB) among the multiple second pixel circuits PC2 connected to the same scan signal line SL. It is also greater than the center distance in the second direction Y of two second pixel circuits PC2 arranged along the first direction X among the multiple second pixel circuits PC2 connected to the same scan signal line SL. In this way, the first distance S1 can be a larger value.

[0043] In other words, the first distance S1 can be the center distance in the second direction Y between the second pixel circuit PC2 corresponding to the second color light-emitting device LG and the second pixel circuit PC2 corresponding to the first color light-emitting device LR among the multiple second pixel circuits PC2 connected to the same scan signal line SL. In this case, the first distance S1 can be a large value. When the first distance S1 is a large value, it can be greater than the center distance in the second direction Y between the second pixel circuit PC2 corresponding to the second color light-emitting device LG and the second pixel circuit PC2 corresponding to the second color light-emitting device LG among the multiple second pixel circuits PC2 connected to the same scan signal line SL, such as... Figure 2 and Figure 3 As shown; when the first distance S1 is a large value, it can also be greater than the center distance in the second direction Y between the second pixel circuit PC2 corresponding to the first color light-emitting device LR and the second pixel circuit PC2 corresponding to the first color light-emitting device LR among the multiple second pixel circuits PC2 connected to the same scanning signal line SL, such as Figure 2 As shown; when the first distance S1 is a large value, it can also be greater than the center distance in the second direction Y between the second pixel circuit PC2 corresponding to the third color light-emitting device LB and the second pixel circuit PC2 corresponding to the third color light-emitting device LB among the multiple second pixel circuits PC2 connected to the same scanning signal line SL, such as Figure 2 As shown; when the first distance S1 is a large value, it can also be greater than the center distance in the second direction Y of the second pixel circuit PC2 corresponding to the first color light-emitting device LR and the second pixel circuit PC2 corresponding to the third color light-emitting device LB among the multiple second pixel circuits PC2 connected to the same scanning signal line SL, such as Figure 3 As shown.

[0044] In one embodiment, among the plurality of second pixel circuits PC2 connected to the same scan signal line SL, two second pixel circuits PC2 corresponding to the same color second light-emitting device D2 (e.g., first color light-emitting device LR and first color light-emitting device LR, second color light-emitting device LG and second color light-emitting device LG, third color light-emitting device LB and third color light-emitting device LB) can be arranged along the first direction X; in another embodiment, among the plurality of second pixel circuits PC2 connected to the same scan signal line SL, the second pixel circuit PC2 corresponding to the first color light-emitting device LR and the second pixel circuit PC2 corresponding to the third color light-emitting device LB can be arranged along the first direction X.

[0045] In other embodiments, the first sub-circuit PC_1 and the second sub-circuit PC_2 can also be electrically connected to the second color light-emitting device LG and the third color light-emitting device LB, respectively. In this case, the first distance S1 can also be a large value. The principle is the same as before, and will not be repeated here.

[0046] When the first distance S1 is large, the color of the second light-emitting device D2 electrically connected to the third sub-circuit PC_3 is the same as the color of the second light-emitting device D2 electrically connected to the first sub-circuit PC_1, which allows the second distance S2 to be a smaller value, for example, referencing... Figure 3 Taking a first sub-circuit PC_1 electrically connected to a second-color light-emitting device LG, and a second sub-circuit PC_2 electrically connected to a first-color light-emitting device LR as an example, the second distance S2 when the third sub-circuit PC_3 is also electrically connected to the second-color light-emitting device LG is less than the second distance S2 when the second light-emitting device D2 connected to the third sub-circuit PC_3 is of another color (first color R or third color B). In one embodiment, along the second direction Y, the third sub-circuit PC_3 is located on the side of the second sub-circuit PC_2 away from the first sub-circuit PC_1.

[0047] By setting the first distance S1 to a larger value and the second distance S2 to a smaller value, and with the first distance S1 being smaller than the second distance S2, the maximum value of the first distance S1 can be less than the minimum value of the second distance S2. This limits the first distance S1 to a smaller range, which helps to reduce the angle between the third direction X' and the first direction X, thereby reducing the bending angle α of the scan signal line SL in the functional device setting area A02 and reducing the degree of bending of the scan signal line SL in the functional device setting area A02.

[0048] In another alternative embodiment, reference continues... Figure 2 and Figure 3 Along the second direction Y, the length of the second pixel circuit PC2 is less than the length of the first pixel circuit PC1.

[0049] Along the second direction Y, the length of the first pixel circuit PC1 or the second pixel circuit PC2 can also be called the size of the first pixel circuit PC1 or the second pixel circuit PC2 in the second direction Y. It can be the length or size of the area occupied by all transistors, capacitors and other structures in the pixel circuit along the second direction Y. For example, it can be the length or size of the active structure in the pixel circuit.

[0050] Specifically, compared to the size of the first pixel circuit PC1 in the second direction Y, the size of the second pixel circuit PC2 in the second direction Y can be reduced, which is beneficial to further increase the light transmittance of the functional device setting area A02.

[0051] In an alternative implementation, Figure 4 This is a schematic diagram of the circuit structure of a second pixel circuit provided in an embodiment of this application. Figure 5 This is a top view schematic diagram of a second pixel circuit provided in an embodiment of this application. Figure 6 This is a schematic diagram of the active structure of a second pixel circuit provided in an embodiment of this application, with reference to... Figures 4-6 The display panel 001 includes a semiconductor layer SMC; the semiconductor layer SMC located in the functional device setting area CUP includes an active structure AS of the second pixel circuit PC2; the active structure AS of the second pixel circuit PC2 includes a channel AC3 of the driving transistor M3 in the second pixel circuit PC2; wherein, the channel AC3 of the driving transistor M3 of the second pixel circuit PC2 is a linear structure.

[0052] For example, the second pixel circuit PC2 has a 7T1C structure. PC2 includes a driving transistor M3, an initialization transistor M5, a write transistor M2, a compensation transistor M4, a first light-emitting control transistor M1, a second light-emitting control transistor M6, a reset transistor M7, and a storage capacitor Cst. The gates of the initialization transistor M5 and the reset transistor M7 can both receive the SP1 signal; the gates of the write transistor M2 and the compensation transistor M4 can both receive the SP2 signal; and the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can both receive the EIMT signal. The scan signal line SL can be used to transmit the SP1, SP2, or EIMT signal. Furthermore, the first light-emitting control transistor M1 can also receive the VDD signal, which, along with the VDD signal, can jointly drive the second light-emitting device D2. The write transistor M2 can also receive DATA to control the current when the driving transistor M3 is turned on. The initialization transistor M5 and the reset transistor M7 can also receive the REF signal for initializing and resetting the driving transistor M3 and the second light-emitting device D2. The first pixel circuit PC1 can use the same circuit as the second pixel circuit PC2, which will not be described in detail here.

[0053] The active structure AS of the second pixel circuit PC2 includes the channels of each transistor in the second pixel circuit PC2, such as the channel AC3 of the driving transistor M3, the channel AC5 of the initialization transistor M5, the channel AC2 of the write transistor M2, the channel AC4 of the compensation transistor M4, the channel AC1 of the first light-emitting control transistor M1, the channel AC6 of the second light-emitting control transistor M6, and the channel AC7 of the reset transistor M7. By setting the channel AC3 of the driving transistor M3 to a linear structure, it is beneficial to reduce the size of the channel AC3 of the driving transistor M3 in the second direction Y, thereby reducing the length of the second pixel circuit PC2 along the second direction Y, so as to further increase the light transmittance of the functional device setting area A02.

[0054] Based on the above implementation, the linear structure of the channel AC3 of the driving transistor M3 extends along the first direction X; along the first direction X, the maximum size of the active structure AS of the second pixel circuit PC2 is LM1; along the second direction Y, the maximum size of the active structure AS of the second pixel circuit PC2 is LM2; wherein, 0.9×LM1≤LM2≤1.1×LM1.

[0055] For example, the channel AC3 of the driving transistor M3 of the second pixel circuit PC2 is a linear structure extending along the first direction X, which helps to reduce the size of the channel AC3 of the driving transistor M3 in the second direction Y. At the same time, 0.9×LM1≤LM2≤1.1×LM1 makes the size of the active structure AS of the second pixel circuit PC2 in the first direction X and the size in the second direction Y approximately equal, so that the top view of the second pixel circuit PC2 is approximately circular or approximately square. Compared with the conventional rectangular pixel circuit structure, it saves more space and helps to further improve the light transmittance of the functional device setting area A02.

[0056] It is understandable that, along the first direction X, the maximum size LM1 of the active structure AS of the second pixel circuit PC2 is the size of the entire space occupied by the active structure AS of the second pixel circuit PC2 in the first direction X. The active structure AS may be discontinuous; when the maximum size LM1 is limited, the middle part of the region may not have an active structure AS. Similarly, along the second direction Y, the maximum size LM2 of the active structure AS of the second pixel circuit PC2 is the size of the entire space occupied by the active structure AS of the second pixel circuit PC2 in the second direction Y. The active structure AS may also be discontinuous; when the maximum size LM2 is limited, the middle part of the region may not have an active structure AS. For example, Figure 6The edge of the channel AC2 of the writing transistor M2 away from the channel AC4 of the compensation transistor M4 is the first edge E1, and the edge of the channel AC4 of the compensation transistor M4 away from the channel AC2 of the writing transistor M2 is the second edge E2. The distance from the first edge E1 to the second edge E2 is LM1. There is a part of the region between the first edge E1 and the second edge E2 where no active structure AS is provided. The active structure AS also includes a third edge E3 and a fourth edge E4. The distance from the third edge E3 to the fourth edge E4 is LM2, and there is a part of the region between the third edge E3 and the fourth edge E4 where no active structure AS is provided.

[0057] In yet another alternative embodiment, reference continues to... Figure 2 and Figure 3 In the same second sub-pixel P02, the orthographic projection of the second pixel circuit PC2 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second light-emitting device D2 on the plane where the display panel 001 is located; the first pixel circuit PC1 includes a fourth sub-circuit PC_4 and a fifth sub-circuit PC_5, which are connected to the same scanning signal line SL; along the second direction Y, the maximum center distance between the first light-emitting device D1 electrically connected to the fourth sub-circuit PC_4 and the first light-emitting device D1 electrically connected to the fifth sub-circuit PC_5 is the third distance S3, and the maximum center distance between the second light-emitting device D2 electrically connected to the first sub-circuit PC_1 and the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 is the fourth distance S4, which is less than the third distance S3.

[0058] The overlap between the orthographic projection of the second pixel circuit PC2 on the plane of the display panel 001 and the orthographic projection of the electrically connected second light-emitting device D2 on the plane of the display panel 001 is beneficial to increasing light transmittance and reducing the distance between the center of the orthographic projection of the second pixel circuit PC2 on the plane of the display panel 001 and the center of the orthographic projection of the electrically connected second light-emitting device D2 on the plane of the display panel 001, thereby shortening the connection between them. The third distance S3 refers to the maximum center distance between any two first light-emitting devices D1 in the second direction Y of the first sub-pixel P01 connected to the same scan signal line SL. The fourth distance S4 refers to the maximum center distance between any two second light-emitting devices D2 in the second direction Y of the second sub-pixel P02 connected to the same scan signal line SL.

[0059] Specifically, since the fourth distance S4 is less than the third distance S3, compared to the main display area A01, the center distance of the second light-emitting device D2 of the second sub-pixel P02 connected to the same scan signal line SL in the functional device setting area A02 is reduced in the second direction Y. At the same time, the orthographic projection of the second pixel circuit PC2 on the plane of the display panel 001 overlaps with the orthographic projection of the second light-emitting device D2 electrically connected to it on the plane of the display panel 001, which helps to reduce the first distance S1, thereby reducing the bending angle α of the scan signal line SL and reducing the degree of bending of the scan signal line SL in the functional device setting area A02.

[0060] For example, compared to the first light-emitting device D1 electrically connected to the fourth sub-circuit PC_4 and the first light-emitting device D1 electrically connected to the fifth sub-circuit PC_5, along the second direction Y, the second light-emitting device D2 electrically connected to the first sub-circuit PC_1 and the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 can be moved towards each other, thus effectively reducing the fourth distance S4. Simultaneously, the orthographic projection of the second light-emitting device D2 on the plane of the display panel 001 overlaps with the orthographic projection of its electrically connected second pixel circuit PC2 on the plane of the display panel 001, effectively reducing the first distance S1. In the same second sub-pixel P02, when the distance between the center of the orthographic projection of the second pixel circuit PC2 on the plane of the display panel 001 and the center of the orthographic projection of the second light-emitting device D2 on the plane of the display panel 001 is zero or very close, the fourth distance S4 is equal to or approximately equal to the first distance S1. By reducing the fourth distance S4, the first distance S1 can be reduced, thereby reducing the bending degree of the scan signal line SL in the functional device setting area A02, reducing design difficulty, and improving product yield.

[0061] For example, continue to refer to Figure 2 and Figure 3Along the first direction X, the length of the first light-emitting device D1 may be greater than the length of the first pixel circuit PC1. To avoid overlap in the orthographic projection of the first light-emitting devices D1 electrically connected to the first pixel circuit PC1 arranged adjacently along the first direction X on the plane of the display panel 001, the arrangement direction of the first light-emitting devices D1 electrically connected to the first pixel circuit PC1 arranged adjacently along the first direction X is usually arranged to intersect with the first direction X. Therefore, based on the above embodiment, the color of the first light-emitting device D1 electrically connected to the fourth sub-circuit PC_4 is set to be different from the color of the first light-emitting device D1 electrically connected to the fifth sub-circuit PC_5, and the fourth sub-circuit PC_4 and the fifth sub-circuit PC_5 are arranged adjacently. This allows the center distance between the first light-emitting devices D1 electrically connected to the fourth sub-circuit PC_4 and the first light-emitting devices D1 electrically connected to the fifth sub-circuit PC_5 in the second direction Y to be the first sub-pixel P0 connected to the same scanning signal line SL. In step 1, the maximum center distance between any two first light-emitting devices D1 in the second direction Y (i.e., the third distance S3); setting the color of the second light-emitting device D2 electrically connected to the first sub-circuit PC_1 to be different from the color of the second light-emitting device D2 electrically connected to the second sub-circuit PC_2, and arranging the second light-emitting devices D2 electrically connected to the first sub-circuit PC_1 and the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 along the third direction X' (the third direction X' is parallel to the plane where the display panel 001 is located, the third direction X' intersects with the first direction X, and the third direction X' also intersects with the second direction Y), so that the center distance between the second light-emitting devices D2 electrically connected to the first sub-circuit PC_1 and the second light-emitting devices D2 electrically connected to the second sub-circuit PC_2 in the second direction Y is the maximum center distance between any two second light-emitting devices D2 in the second sub-pixel P02 connected to the same scanning signal line SL in the second direction Y (i.e., the fourth distance S4).

[0062] It is understandable that, as described above, the third direction X' is the arrangement direction of the first sub-circuit PC_1 and the second sub-circuit PC_2. In the same second sub-pixel circuit PC2, when the orthographic projection of the second pixel circuit PC2 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second light-emitting device D2 on the plane where the display panel 001 is located, the arrangement direction of the second light-emitting device D2 electrically connected to the first sub-circuit PC_1 and the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 can be the third direction X' or a direction close to the third direction X'.

[0063] In one implementation, continue to refer to Figure 2 and Figure 3The first pixel circuit PC1 also includes a sixth sub-circuit PC_6. The scanning signal line SL connected to the fifth sub-circuit PC_5 and the scanning signal line SL connected to the sixth sub-circuit PC_6 are arranged adjacently, that is, the sixth sub-circuit PC_6 and the fifth sub-circuit PC_5 are respectively connected to different and adjacent scanning signal lines SL. Along the second direction Y, the minimum center distance between the first light-emitting device D1 electrically connected to the fifth sub-circuit PC_5 and the first light-emitting device D1 electrically connected to the sixth sub-circuit PC_6 is the fifth distance S5. The minimum center distance between the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 and the second light-emitting device D2 electrically connected to the third sub-circuit PC_3 is the sixth distance S6. The sixth distance S6 is greater than the fifth distance S5.

[0064] Wherein, the fifth distance S5 refers to the minimum center distance of the first light-emitting devices D1 of any two first sub-pixels P01 connected by adjacent scanning signal lines SL in the second direction Y, and the sixth distance S6 refers to the minimum center distance of the second light-emitting devices D2 of any two second sub-pixels P02 connected by adjacent scanning signal lines SL in the second direction Y.

[0065] Specifically, since the sixth distance S6 is greater than the fifth distance S5, compared to the main display area A01, in the functional device setting area A02, the center distance of the second light-emitting device D2 electrically connected to the second pixel circuit PC2 connected to the adjacent scan signal line SL in the second direction Y is increased. At the same time, the orthographic projection of the second pixel circuit PC2 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second light-emitting device D2 electrically connected to it on the plane where the display panel 001 is located, which helps to increase the second distance S2, thereby reducing the first distance S1 and reducing the degree of bending of the scan signal line SL in the functional device setting area A02.

[0066] For example, compared to the first light-emitting device D1 electrically connected to the fifth sub-circuit PC_5 and the first light-emitting device D1 electrically connected to the sixth sub-circuit PC_6, along the second direction Y, the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 and the second light-emitting device D2 electrically connected to the third sub-circuit PC_3 can be moved in a direction away from each other, thus effectively increasing the sixth distance S6. Simultaneously, the orthographic projection of the second light-emitting device D2 onto the plane of the display panel 001 overlaps with the orthographic projection of its electrically connected second pixel circuit PC2 onto the plane of the display panel 001, effectively increasing the second distance S2. In the same second sub-pixel P02, when the distance between the center of the orthographic projection of the second pixel circuit PC2 onto the plane of the display panel 001 and the center of the orthographic projection of the second light-emitting device D2 onto the plane of the display panel 001 is zero or very close, the sixth distance S6 is equal to or approximately equal to the second distance S2. By increasing the sixth distance S6, the second distance S2 can be increased, thereby reducing the first distance S1 and decreasing the bending degree of the scan signal line SL in the functional device setting area A02.

[0067] Based on the above implementation, the color of the first light-emitting device D1 electrically connected to the sixth sub-circuit PC_6 is set to be the same as the color of the first light-emitting device D1 electrically connected to the fourth sub-circuit PC_4. This makes the center distance between the first light-emitting device D1 electrically connected to the sixth sub-circuit PC_6 and the first light-emitting device D1 electrically connected to the fifth sub-circuit PC_5 in the second direction Y the minimum center distance (i.e., the fifth distance S5) between the first light-emitting devices D1 electrically connected to any two first sub-pixels P01 connected to adjacent scanning signal lines SL in the second direction Y. The color of the second light-emitting device D2 electrically connected to the third sub-circuit PC_3 is set to be the same as the color of the second light-emitting device D2 electrically connected to the first sub-circuit PC_1. This makes the center distance between the second light-emitting device D2 electrically connected to the third sub-circuit PC_3 and the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 in the second direction Y the minimum center distance (i.e., the sixth distance S6) between the second light-emitting devices D2 electrically connected to the third sub-circuit PC_3 and the second light-emitting device D2 electrically connected to the second sub-circuit PC_2 in the second direction Y.

[0068] In yet another alternative embodiment, Figure 7 This is a top view of the third type of display panel provided in the embodiments of this application. Figure 8 This is a top view structural diagram of the fourth type of display panel provided in the embodiments of this application, wherein, Figure 7 and Figure 2 same, Figure 8 and Figure 3 The same, the difference is, Figure 7 and Figure 8 Some new reference numerals have been added to the attached figures; this section primarily explains these newly added reference numerals. (References) Figure 7 and Figure 8 The display panel 001 includes first pixel circuit rows PU1 and second pixel circuit rows PU2 extending along a first direction X and alternately arranged along a second direction Y, and first pixel circuit columns PV1 and second pixel circuit columns PV2 extending along the second direction Y and alternately arranged along the first direction X; adjacent first pixel circuit rows PU1 and second pixel circuit rows PU2 form a pixel circuit row group PU0; adjacent first pixel circuit columns PV1 and second pixel circuit columns PV2 form a pixel circuit column group PV0. In the main display area A01, the number of first pixel circuits PC1 located in the same pixel circuit row group PU0 and the same pixel circuit column group PV0 is a first number; in the functional device setting area A02, the number of second pixel circuits PC2 located in the same pixel circuit row group PU0 and the same pixel circuit column group PV0 is a second number; the first number is greater than the second number.

[0069] For example, Figure 7 and Figure 8 The pixel circuits within the dashed elliptical boxes are those located in the same pixel circuit row group PU0 and the same pixel circuit column group PV0. In the main display area A01, the first pixel circuits PC1 located in the same pixel circuit row group PU0 and the same pixel circuit column group PV0 constitute a first pixel circuit arrangement unit PW1, which includes four first pixel circuits PC1. In the functional device setting area A02, the second pixel circuits PC2 located in the same pixel circuit row group PU0 and the same pixel circuit column group PV0 constitute a second pixel circuit arrangement unit PW2, which includes one, two, or three second pixel circuits PC2. In an optional embodiment, pixel circuits located in the same pixel circuit row can be connected to the same scan signal line SL, and pixel circuits located in the same pixel column can be connected to the same data signal line (SL). Figure 7 and Figure 8 (Not shown in the image).

[0070] By reducing the number of second pixel circuits PC2 in the second pixel circuit arrangement unit PW2 located in the functional device setting area A02, and making the number of second pixel circuits PC2 in each second pixel circuit arrangement unit PW2 in the functional device setting area A02 the same (all are the second number), the number of second pixel circuits PC2 in the functional device setting area A02 can be reduced uniformly, which is beneficial to the uniform light transmission of the functional device setting area A02.

[0071] In one implementation, continue to refer to Figure 7 and Figure 8In the main display area A01, in the first pixel circuit arrangement unit PW1, the four first light-emitting devices D1 electrically connected to the four first pixel circuits PC1 can constitute the minimum repeating unit, that is, these four first light-emitting devices D1 include light-emitting devices of all colors. Similarly, in the second pixel circuit arrangement unit PW2 located in the functional device setting area A02, when the number of second pixel circuits PC2 is not reduced and remains four, the four second light-emitting devices D2 electrically connected to the four second pixel circuits PC2 in the second pixel circuit arrangement unit PW2 can also include light-emitting devices of all colors. This improves the display uniformity of the first pixel circuit arrangement unit PW1, thereby improving the display uniformity of the functional device setting area A02 when the number of second pixel circuits PC2 in the second pixel circuit arrangement unit PW2 located in the functional device setting area A02 is reduced.

[0072] In another embodiment, reference Figure 7 In the functional device setting area A02, the second pixel circuit arrangement unit PW2 includes a first sub-arrangement unit PW_1 and a second sub-arrangement unit PW_2. The first sub-arrangement unit PW_1 and the second sub-arrangement unit PW_2 can be arranged adjacent to each other along a first direction X, and / or, the first sub-arrangement unit PW_1 and the second sub-arrangement unit PW_2 can be arranged adjacent to each other along a second direction Y. The positions of the second pixel circuit PC2 in the first sub-arrangement unit PW_1 and the second sub-arrangement unit PW_2 are different. By setting the first sub-arrangement unit PW_1 and the second sub-arrangement unit PW_2 with different arrangement methods in the adjacent second pixel circuit arrangement unit PW2, it is also beneficial to improve the display uniformity of the functional device setting area A02 and avoid color shift.

[0073] Based on the above embodiments, refer to Figure 8 In the functional device setting area CUP, within the same pixel circuit row group PU0, the second pixel circuits PC2 located in the same pixel circuit column group PV0 are situated in different pixel circuit rows and columns. For example, in the second pixel circuit arrangement unit PW2 of the functional device setting area CUP, two second pixel circuits PC2 are provided, and these two second pixel circuits PC2 are diagonally distributed, which helps to increase light transmittance and ensure uniform light transmission.

[0074] In one implementation, continue to refer to Figure 8In the functional device setting area A02, the second pixel circuit arrangement unit PW2 includes a third sub-arrangement unit PW_3 and a fourth sub-arrangement unit PW_4. The positions of the second pixel circuit PC2 in the third sub-arrangement unit PW_3 and the fourth sub-arrangement unit PW_4 are different. Along the first direction X, the third sub-arrangement unit PW_3 can be arranged adjacent to both the third sub-arrangement unit PW_3 and the fourth sub-arrangement unit PW_4 at the same time, and the fourth sub-arrangement unit PW_4 can also be arranged adjacent to both the third sub-arrangement unit PW_3 and the fourth sub-arrangement unit PW_4 at the same time. That is, along the first direction X, the two third sub-arrangement units PW_3 and the two fourth sub-arrangement units PW_4 are arranged alternately along the first direction X.

[0075] For example, the scan signal line SL, which passes through the functional device setting area A02 and is electrically connected to the second pixel circuit PC2, includes a scan connection portion SB located in the functional device setting area A02 and connecting two adjacent second pixel circuits PC2. In two third sub-arrangement units PW_3 or two fourth sub-arrangement units PW_4 arranged adjacently along the first direction X, the scan connection portion SB between the two second pixel circuits PC2 connected to the same scan signal line SL can extend along the first direction X. By setting two third sub-arrangement units PW_3 and two fourth sub-arrangement units PW_4 to alternately arrange along the first direction X, it is possible to make one of the two adjacent scan connection parts SB in the same scan signal line SL extend along the first direction and the other extend along the direction intersecting with the first direction X. On the one hand, this helps to reduce the bending angle α between adjacent scan connection parts SB and reduce the degree of bending of the scan signal line SL in the functional device setting area A02. On the other hand, it helps to reduce light diffraction and avoid the diffraction effect that the regular arrangement of the high-density pixel circuit array can easily cause to the light, resulting in glare, starburst or fogging of the light passing through the functional device setting area A02.

[0076] Optional, Figure 9 This is a top view of the fifth type of display panel provided in this application embodiment. Figure 10 This is a top view structural diagram of the sixth type of display panel provided in the embodiments of this application, with reference to... Figure 9 and Figure 10 In the main display area A01, the distance between two first pixel circuits PC1 connected to the same scan signal line SL and located in adjacent pixel circuit columns along the first direction X is S01; in the functional device setting area A02, the distance between two second pixel circuits PC2 connected to the same scan signal line SL and located in adjacent pixel circuit columns along the first direction X is S02; S02 > S01.

[0077] For example, refer to Figure 9 and Figure 10Compared to the first pixel circuit PC1 located in the main display area A01 and corresponding to the second color light-emitting device LG, the second pixel circuit PC2 located in the functional device setting area A02 and corresponding to the second color light-emitting device LG can be moved to the left in the figure; and / or, compared to the first pixel circuit PC1 located in the main display area A01 and corresponding to the first color light-emitting device LR and the third color light-emitting device GB, the second pixel circuit PC2 located in the functional device setting area A02 and corresponding to the first color light-emitting device LR and the third color light-emitting device GB can be moved to the right in the figure, thus effectively increasing S02.

[0078] by Figure 9 and Figure 10 Taking the first sub-circuit PC_1 and the second sub-circuit PC_2 as examples, where the first sub-circuit PC_1 and the second sub-circuit PC_2 are located in adjacent pixel circuit columns, by adding S02, the angle between the extension direction of the scanning connection part SB connected between the first sub-circuit PC_1 and the second sub-circuit PC_2 and the first direction X can be reduced, thereby reducing the bending degree of the scanning signal line SL.

[0079] At the same time, combined Figure 2 and Figure 3 In the figure, the first distance S1 is smaller than the second distance S2. Compared with the first pixel circuit PC1 located in the main display area A01 and corresponding to the second color light-emitting device LG, the second pixel circuit PC2 located in the functional device setting area A02 and corresponding to the second color light-emitting device LG can move in the direction of lower left in the figure; and / or, compared with the first pixel circuit PC1 located in the main display area A01 and corresponding to the first color light-emitting device LR and the third color light-emitting device GB, the second pixel circuit PC2 located in the functional device setting area A02 and corresponding to the first color light-emitting device LR and the third color light-emitting device GB can move in the direction of upper right in the figure. This can effectively reduce the bending degree of the scanning signal line SL, reduce the design difficulty, improve the product yield and the reliability of the display panel 001.

[0080] In an optional embodiment, in the functional device setting area A02, the orthographic projection of the second pixel circuit PC2 on the plane of the display panel 001 overlaps with the orthographic projection of the second light-emitting device D2 electrically connected to it on the plane of the display panel 001. By adding S02, it is beneficial to increase the center distance of the second light-emitting devices D2 connected to the second pixel circuit PC2 in adjacent pixel circuit columns connected to the same scan signal line SL in the first direction X. This can avoid the second light-emitting devices D2 connected to the second pixel circuit PC2 in adjacent pixel circuit columns connected to the same scan signal line SL being too close, causing the second light-emitting devices D2 of different colors to overlap in the direction perpendicular to the plane of the display panel 001.

[0081] Optional, Figure 11 This is a top view of the seventh type of display panel provided in this application embodiment. Figure 12 This is a partial top view of the first type of functional device setting area provided in the embodiments of this application, with reference to... Figure 11 and Figure 12 A portion of the scan signal line SL includes a scan connection portion SB located in the functional device setting area A02 and connecting two adjacent second pixel circuits PC2; the scan connection portion SB includes a first scan connection portion SB1 and a second scan connection portion SB2; the scan signal line SL includes a first scan signal line SL1 and a second scan signal line SL; a portion of the first scan signal line SL1 includes the first scan connection portion SB1, and a portion of the second scan signal line SL2 includes the second scan connection portion SB2; the orthographic projection of the first scan connection portion SB1 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second scan connection portion SB2 on the plane where the display panel 001 is located.

[0082] Here, the first scan signal line SL1 and the second scan signal line SL are scan signal lines of different types. The first scan signal line SL1 and the second scan signal line SL can be connected to the same pixel circuit and control the conduction state of transistors at different positions or with different functions in the same pixel circuit. For example, the first scan signal line SL1 and the second scan signal line SL can be used to transmit data respectively. Figure 4 The SP1 and SP2 signals, or the first scan signal line SL1 and the second scan signal line SL, can also be used for transmission. Figure 4 The SP2 signal, EMIT signal, or the first scan signal line SL1 and the second scan signal line SL can also be used for transmission. Figure 4 The EMIT signal and SP1 signal in the data.

[0083] The scan signal line SL includes a first portion of the scan signal line SL that does not pass through the functional device setting area A02 and a second portion of the scan signal line SL that passes through the functional device setting area A02. The second portion of the scan signal line SL may include a scan connection portion SB. Similarly, the first scan signal line SL1 that passes through the second portion of the functional device setting area A02 includes a first scan connection portion SB1, and the second scan signal line SL2 that passes through the second portion of the functional device setting area A02 includes a second scan connection portion SB2. The first scan signal line SL1 and the second scan signal line SL2 can be connected to the same pixel circuit; therefore, the first scan connection portion SB1 and the second scan connection portion SB2 can be connected to the same two second pixel circuits PC2.

[0084] For details, please refer to Figure 11 and Figure 12 A pixel circuit can be electrically connected to multiple scan signal lines SL. Multiple pixel circuits connected to the same scan signal line SL can be connected to the same multiple scan signal lines SL simultaneously. In the functional device setting area A02, the second pixel circuit PC2 located in the same pixel circuit row can be electrically connected to multiple scan signal lines SL simultaneously. The orthographic projections of the multiple scan signal lines SL electrically connected to the second pixel circuit PC2 located in the same pixel circuit row overlap on the plane where the display panel 001 is located, so as to reduce the influence of the scan signal lines SL on the light transmittance of the functional device setting area A02.

[0085] For example, refer to Figure 11 and Figure 12 The first scanning connection part SB1 is located in the functional device setting area A02 and connects to two adjacent second pixel circuits PC2; the second scanning connection part SB2 is located in the functional device setting area A02 and connects to two adjacent second pixel circuits PC2; in the scanning connection parts SB that connect to the same two second pixel circuits PC2, the orthographic projection of the first scanning connection part SB1 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second scanning connection part SB2 on the plane where the display panel 001 is located.

[0086] In an optional embodiment, Figure 13 This is a partial cross-sectional structural diagram of the first type of functional device setting area provided in the embodiments of this application, with reference to... Figures 11-13The scan signal line SL also includes a third scan signal line SL3; the scan connection part SB also includes a third scan connection part SB3; a portion of the third scan signal line SL3 includes a third scan connection part SB3; the conductive layer where the third scan connection part SB3 is located is located between the conductive layer where the first scan connection part SB1 is located and the conductive layer where the second scan connection part SB2 is located; the orthographic projection of the third scan connection part SB3 on the plane where the display panel 001 is located overlaps with the orthographic projection of the first scan connection part SB1 on the plane where the display panel 001 is located, and the orthographic projection of the third scan connection part SB3 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second scan connection part SB2 on the plane where the display panel 001 is located.

[0087] For example, the first scanning connection portion SB1 may be located in the first metal conductive layer 110, the second scanning connection portion SB2 may be located in the third metal conductive layer 130, and the third scanning connection portion SB3 may be located in the second metal conductive layer 120. The first metal conductive layer 110 is located on the side of the third metal conductive layer 130 closest to the substrate 100, and the second metal conductive layer 120 is located between the first metal conductive layer 110 and the third metal conductive layer 130. In one embodiment, the orthographic projection of the first scanning connection portion SB1 onto the plane of the display panel 001 can completely overlap with the orthographic projection of the second scanning connection portion SB2 onto the plane of the display panel 001. The orthographic projection of the third scanning connection portion SB3 onto the plane of the display panel 001 partially overlaps with the orthographic projections of the first scanning connection portion SB1 and the second scanning connection portion SB2 onto the plane of the display panel 001. This helps to reduce parasitic capacitive coupling between the first scanning connection portion SB1 and the second scanning connection portion SB2, and also helps to reduce the impact of the scanning connection portions SB on the transmittance of the functional device setting area A02.

[0088] Based on the above embodiments, the second pixel circuit PC2 includes a driving transistor M3, a writing transistor M2, a light-emitting control transistor (M1 and / or M6), and a reset transistor M7; the driving transistor M3 is electrically connected to the reset transistor M7, the writing transistor M2, and the light-emitting control transistor (M1 and / or M6), respectively; the reset transistor M7 is used to transmit a reset signal REF when it is turned on, and the writing transistor M2 is used to transmit a data signal DATA when it is turned on; the light-emitting control transistor (M1 and / or M6) is used to control the driving transistor M3 to provide driving current when it is turned on; in the second pixel circuit PC2, the gate of the writing transistor M2 is electrically connected to the first scan signal line SL1, the gate of the light-emitting control transistor (M1 and / or M6) is electrically connected to the second scan signal line SL2, and the gate of the reset transistor M7 is electrically connected to the third scan signal line SL3.

[0089] For example, with Figure 4Taking the second pixel circuit PC2 as an example, the second pixel circuit PC2 includes a driving transistor M3, a writing transistor M2, a compensation transistor M4, a first light-emitting control transistor M1, a second light-emitting control transistor M6, an initialization transistor M5, and a reset transistor M7. The following description, in conjunction with the structural schematics of each metal conductive layer, provides an exemplary illustration of this embodiment.

[0090] Figure 14 This is a schematic diagram of the structure of the first metal conductive layer of a second pixel circuit provided in an embodiment of this application. (Refer to...) Figure 14 The first metal conductive layer 110 includes the gates of each transistor in the second pixel circuit PC2, such as the gate G3 of the driving transistor M3, the gate G5 of the initialization transistor M5, the gate G2 of the write transistor M2, the gate G4 of the compensation transistor M4, the gate G1 of the first light-emitting control transistor M1, the gate G6 of the second light-emitting control transistor M6, and the gate G7 of the reset transistor M7. The first scan connection portion SB1 located in the first metal conductive layer 110 can be directly connected to the gate G2 of the write transistor M2 and the gate G4 of the compensation transistor M4. Figure 14 (not shown in the image), enabling the first scan signal line SL1 to be electrically connected to the gate G2 of the write transistor M2 and the gate G4 of the compensation transistor M4 of the second pixel circuit PC2.

[0091] Figure 15 This is a schematic diagram of the structure of the second metal conductive layer of a second pixel circuit provided in an embodiment of this application. (Refer to...) Figure 14 and Figure 15 The first metal conductive layer 110 includes extensions H11 and H12 connected to the gate G5 of the initialization transistor M5 and the gate G7 of the reset transistor M7. Extensions H11 and H12 can be used to overlap other conductive layers. The second metal conductive layer 120 includes extensions H21 and H22. Extension H21 can overlap with extension H11 of the first metal conductive layer 110, and extension H22 can overlap with extension H12 of the first metal conductive layer 110. The third scan connection portion SB3 located in the second metal conductive layer 120 can be directly electrically connected to extension H21 or extension H22. Figure 15 (not shown in the image), and is electrically connected to the gate G5 of the initialization transistor M5 and the gate G7 of the reset transistor M7 via the extension H11 or extension H12, so that the third scan signal line SL3 can be electrically connected to the gate G2 of the write transistor M2 and the gate G4 of the compensation transistor M4 of the second pixel circuit PC2.

[0092] Figure 16 This is a schematic diagram of the structure of the third metal conductive layer of a second pixel circuit provided in an embodiment of this application. (Refer to...) Figure 14 and Figure 16 The first metal conductive layer 110 includes extensions H13 and H14 connected to the gate G1 of the first light-emitting control transistor M1 and the gate G6 of the second light-emitting control transistor M6. Extensions H13 and H14 can be used to overlap other conductive layers. The third metal conductive layer 130 includes extensions H33 and H34. Extension H33 can be electrically connected to extension H13 of the first metal conductive layer 110, and extension H34 can be electrically connected to extension H14 of the first metal conductive layer 110. The second scan connection portion SB2 located in the third metal conductive layer 130 can be directly electrically connected to extension H33 or extension H34. Figure 16 (not shown in the image), and is electrically connected to the gate G1 of the first light-emitting control transistor M1 and the gate G6 of the second light-emitting control transistor M6 through the extension portion H13 or the extension portion H14, so that the second scan signal line SL2 can be electrically connected to the gate G1 of the first light-emitting control transistor M1 and the gate G6 of the second light-emitting control transistor M6 of the second pixel circuit PC2.

[0093] Figure 17 This is a top view schematic diagram of the stacked first to third metal conductive layers of a second pixel circuit provided in an embodiment of this application, with reference to... Figures 14-17 The orthographic projection of the extension H11 of the first metal conductive layer 110 onto the plane of the display panel 001 overlaps with the orthographic projection of the extension H21 of the second metal conductive layer 120 onto the plane of the display panel 001. The extension H11 can overlap with the extension H21. Similarly, the extension H12 can overlap with the extension H22. Different third scanning connection parts SB3 connected to the same second pixel circuit PC2 can be connected to the extension H21 and the extension H22 respectively. The extension H21 and the extension H22 can be electrically connected through the first metal conductive layer 110. The orthographic projection of the extension H13 of the first metal conductive layer 110 onto the plane of the display panel 001 does not overlap with the orthographic projection of the extension H33 of the third metal conductive layer 130 onto the plane of the display panel 001. The extension H13 can be connected to the extension H33 via the lap electrode DJ1. Similarly, the extension H14 can be connected to the extension H34 via the lap electrode DJ2. Different second scan connection portions SB2 connected to the same second pixel circuit PC2 can be connected to the extension H33 and the extension H34 respectively. The extension H33 and the extension H34 can be electrically connected via the first metal conductive layer 110.

[0094] In an optional embodiment, a capacitor conductive layer may be further disposed between the first metal conductive layer 110 and the second metal conductive layer 120, the capacitor conductive layer including capacitor plates ( Figures 14-17(Not shown in the image) The orthographic projection of the capacitor plate onto the plane of the display panel 001 can overlap with the orthographic projection of the gate G3 of the driving transistor M3 onto the plane of the display panel 001 to form the storage capacitor Cst in the second pixel circuit PC2.

[0095] Optional, Figure 18 This is a partial top view of the structure of the second type of functional device setting area provided in the embodiments of this application, with reference to... Figure 18 ,refer to Figure 12 and Figure 18 The scan signal line SL includes a scan connection portion SB located in the functional device setting area A02 and connecting two adjacent second pixel circuits PC2; the scan signal line SL also includes a scan extension portion SY located in the functional device setting area A02 and connecting the scan connection portion SB and the second pixel circuit PC2 respectively; wherein, the extension direction of the scan extension portion SY intersects with the extension direction of the scan connection portion SB electrically connected to the scan extension portion SY.

[0096] Specifically, the scan extension SY can serve as a connection transition area for the scan connection SB, connecting to the second pixel circuit PC2. That is, the scan connection SB is electrically connected to the transistor in the second pixel circuit PC2 via the scan extension SY. The scan connection SB can be connected to any position of the scan extension SY. By setting the extension direction of the scan extension SY to intersect with the extension direction of the scan connection SB electrically connected to the scan extension SY, multi-angle extended scan connection SBs can be accommodated. Furthermore, by adjusting the position of the scan connection SB connected to the scan extension SY, the extension direction of the scan connection SB can be changed, which helps reduce the bending degree of the scan signal line SL in the functional device setting area A02, thereby improving product yield.

[0097] For example, the scanning extension SY and the scanning connection part SB, which is electrically connected to the scanning extension SY, can be arranged on the same layer and are an integral structure, as shown in the reference. Figures 11-18 The scanning connection portion SB includes a first scanning connection portion SB1 located on the first metal conductive layer 110, a third scanning connection portion SB3 located on the second metal conductive layer 120, and a second scanning connection portion SB2 located on the third metal conductive layer 130. The first metal conductive layer 110 also includes a first scanning extension portion SY1 connected to the first scanning connection portion SB1, the second metal conductive layer 120 also includes a third scanning extension portion SY3 connected to the third scanning connection portion SB3, and the third metal conductive layer 130 also includes a second scanning extension portion SY2 connected to the second scanning connection portion SB2. In other optional embodiments, the scanning extension portion SY may also be located on different conductive layers, and the scanning connection portions SB electrically connected to the scanning extension portion SY may be connected via vias. Figures 11-18 (Not shown in the image).

[0098] Continuing with the example of a single structure where the scanning extension SY and the scanning connection SB, which is electrically connected to the scanning extension SY, are arranged on the same layer, refer to... Figure 18 ,by Figure 18 With the center position as a reference, the second pixel circuit PC2 on the left is located in the upper part of the figure, and the second pixel circuit PC2 on the right is located in the lower part of the figure, between the second pixel circuit PC2 on the left and the second pixel circuit PC2 on the right. The scanning connection part SB connecting these two second pixel circuits PC2 needs to extend from the upper left to the lower right. This allows the scanning connection part SB to connect to the lower part of the scanning extension SY on the left (e.g., the bottom end) and to the upper part of the scanning extension SY on the right (e.g., the top end). This makes the angle between the scanning connection part SB and the scanning extension SY on the left and the scanning extension SY on the right larger, reducing the difficulty of the process.

[0099] It should be noted that the figure only shows an example of the scanning extension SY being an arc-shaped structure. In other embodiments, the scanning extension SY may also be a straight structure. Figure 18 (not shown in the image), for example, the linear structure of the scanning extension SY can extend along the second direction Y.

[0100] In an optional embodiment, the scanning extension SY has an arc-shaped structure and protrudes towards the scanning connection portion SB, which is electrically connected to the scanning extension SY. The scanning extension SY may protrude outwards from the second pixel circuit PC2 where it is located. This helps to increase the angle between the scanning extension SY and the scanning connection portion SB, avoiding an excessively small angle that would increase manufacturing complexity. Furthermore, an excessively small angle between the scanning extension SY and the scanning connection portion SB may increase the connection area, which is detrimental to increasing the light transmittance of the functional device placement area A02.

[0101] Optional, Figure 19 This is a top view of the eighth type of display panel provided in this application embodiment. Figure 20 This is a partial top view of the third type of functional device setting area provided in the embodiments of this application, for reference. Figure 19 and Figure 20The display panel 001 includes a first pixel circuit column PV1 and a second pixel circuit column PV2 that extend along a second direction Y and are alternately arranged along a first direction X. The display panel 001 also includes at least a data signal line DL that extends along the second direction Y. The data signal line DL includes a data connection portion DB located in the functional device setting area A02 and between two adjacent second pixel circuits PC2. The data connection portion DB includes a first data connection portion DB1 and a second data connection portion DB2. The data signal line DL includes a first data signal line DL1 electrically connected to the first pixel circuit PC1 in the first pixel circuit column PV1 and a second data signal line DL2 electrically connected to the first pixel circuit PC1 in the second pixel circuit column PV2. The first data signal line DL1 includes the first data connection portion DB1, and the second data signal line DL2 includes the second data connection portion DB2. The orthographic projection of the first data connection portion DB1 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second data connection portion DB2 on the plane where the display panel 001 is located.

[0102] The data signal line DL is used to transmit the data signal ADTA and provide the data signal ADTA to the pixel circuit electrically connected to the data signal line DL. The first data signal line DL1 and the second data signal line DL2 are data signal lines of the same type, and the first data signal line DL1 and the second data signal line DL2 can be connected to the write transistors in different pixel circuits, respectively. The data signal line DL includes a first part of the data signal line DL that does not pass through the functional device setting area A02 and a second part of the data signal line DL that passes through the functional device setting area A02. The second part of the data signal line DL may include a data connection part DB. Similarly, the first data signal line DL1 that passes through the second part of the functional device setting area A02 includes a first data connection part DB1, and the second data signal line DL2 that passes through the second part of the functional device setting area A02 includes a second data connection part DB2.

[0103] By ensuring that the orthographic projections of the portion of the first data signal line DL1 located in the functional device setting area A02 (first data connection part DB1) and the portion of the second data signal line DL2 located in the functional device setting area A02 (second data connection part DB2) overlap on the plane where the display panel 001 is located, the influence of the data signal line DL on the transmittance of the functional device setting area A02 can be reduced. In one embodiment, the orthographic projection of the first data connection part DB1 on the plane where the display panel 001 is located may overlap with the orthographic projection of the second data connection part DB2 on the plane where the display panel 001 is located, i.e., the two do not completely overlap, thereby reducing interference from parasitic capacitance.

[0104] For example, refer to Figure 19 and Figure 20Adjacent first pixel circuit columns PV1 and second pixel circuit columns PV2 form a pixel circuit column group PV0. The orthographic projections of the first data connection portion DB1 and the second data connection portion DB2 connected to the same pixel circuit column group PV0 overlap on the plane where the display panel 001 is located. When the first data connection portion DB1 and the second data connection portion DB2 pass through the same second pixel circuit PC2, one of them is electrically connected to the second pixel circuit PC2, while the other only passes through the second pixel circuit PC2 and is not electrically connected to it. In other words, a pixel circuit is only electrically connected to one data signal line DL. The first data signal line DL1 and the second data signal line DL2 are not electrically connected to the same pixel circuit. Therefore, in the functional device setting area A02, even if the first data connection portion DB1 and the second data connection portion DB2 can extend to the same second pixel circuit PC2, the first data connection portion DB1 and the second data connection portion DB2 will not be electrically connected to the same second pixel circuit PC2 at the same time. This allows the second pixel circuit PC2 to write accurate data signal DATA, preventing abnormal display in the functional device setting area A02, and also avoiding short circuits between the first data signal line DL1 and the second data signal line DL2, which could damage the circuit.

[0105] In an optional embodiment, the display panel 001 includes a first pixel circuit column PV1 and a second pixel circuit column PV2 extending along a second direction Y and alternately arranged along a first direction X; adjacent first pixel circuit columns PV1 and second pixel circuit columns PV2 form a pixel circuit column group PV0; the display panel 001 also includes at least a data signal line DL extending along the second direction Y; the data signal line DL includes adjacent first data signal lines DL1 and second data signal lines DL2; the first data signal line DL1 is electrically connected to the first pixel circuit PC1 in the first pixel circuit column PV1, and the second data signal line DL2 is electrically connected to the first pixel circuit PC1 in the second pixel circuit column PV2; the second pixel circuit PC2 located in the same pixel circuit column group PV0 is electrically connected to the first data signal line DL1.

[0106] Specifically, all second pixel circuits PC2 are electrically connected to the first data signal line DL1, and the second pixel circuits PC2 located in the same pixel circuit column group PV0 are electrically connected to the same first data signal line DL1. In one embodiment, the second data signal line DL2 does not need to be electrically connected to the second pixel circuit PC2, and all second data signal lines DL2 may not pass through the functional device setting area A02. The second data signal lines DL2 in the same pixel circuit column group PV0 connected to the first pixel circuit PC1 that passes through the functional device setting area A02 can bypass the functional device setting area A02. Figure 19(Not shown) to reduce the impact of the data signal line DL on the transmittance of the functional device setting area A02. In another embodiment, the second data signal line DL2 does not need to be electrically connected to the second pixel circuit PC2, and can also pass through the functional device setting area A02 but not be electrically connected to the second pixel circuit PC2. For example, the orthographic projection of the second data signal line DL2 passing through the functional device setting area A02 on the plane of the display panel 001 can overlap with the orthographic projection of the portion of the first data signal line DL1 located in the functional device setting area A02 (the first data connection portion DB1) on the plane of the display panel 001, so as to reduce the impact of the data signal line DL on the transmittance of the functional device setting area A02. Furthermore, the second pixel circuit PC2 is electrically connected to the first data signal line DL1, which allows the second pixel circuit PC2 to overlap with the conductive layer where the portion of the first data signal line DL11 located in the functional device setting area A02 (the first data connection portion DB1) is located, which is beneficial to simplify the film layer design.

[0107] For example, taking the second data signal line DL2 of the first pixel circuit PC1 in the same pixel circuit column group PV0 as the first data signal line DL1 that passes through the functional device setting area A02 as an example, which also passes through the functional device setting area A02. Figure 21 This is a partial cross-sectional structural diagram of the second type of functional device setting area provided in the embodiments of this application, with reference to... Figures 19-21 The first data signal line DL1 passing through the functional device setting area A02 includes a first data connection part DB1 located in the functional device setting area A02 and between two adjacent second pixel circuits PC2. The first data connection part DB1 may be located in the fourth metal conductive layer 140. The second data signal line DL2 passing through the functional device setting area A02 includes a second data connection part DB2 located in the functional device setting area A02 and between two adjacent second pixel circuits PC2. The second data connection part DB2 may be located in the third metal conductive layer 130.

[0108] Based on the above embodiments, Figure 22 This is a top view structural diagram of the ninth type of display panel provided in the embodiments of this application, with reference to... Figure 22The second pixel circuit PC includes a seventh sub-circuit PC_7, an eighth sub-circuit PC_8, and a ninth sub-circuit PC_9. The seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 are located in the same pixel circuit column group PV0. The pixel circuit column group where the ninth sub-circuit PC_9 is located is adjacent to the pixel circuit column group where the eighth sub-circuit PC_8 is located. The seventh sub-circuit PC_7 and the ninth sub-circuit PC_9 are both located in the first pixel circuit column PV1, and the eighth sub-circuit PC_8 is located in the second pixel circuit column PV2. Along the first direction X, the center distance between the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 is the seventh distance S7, and the center distance between the eighth sub-circuit PC_8 and the ninth sub-circuit PC_9 is the eighth distance S8. The seventh distance S7 is less than the eighth distance S8.

[0109] In the same pixel circuit group PV0 of the functional device setting area A02, the seventh sub-circuit PC_7 can be any second pixel circuit PC2 located in the first pixel circuit group PV1, and the eighth sub-circuit PC_8 can be any second pixel circuit PC2 located in the second pixel circuit group PV2; the ninth sub-circuit PC_9 can be any second pixel circuit PC2 located in the first pixel circuit group PV1 adjacent to the second pixel circuit group PV2 where the eighth sub-circuit PC_8 is located, and the ninth sub-circuit PC_9 and the eighth sub-circuit PC_8 are located in different pixel circuit group PV0. In the same pixel circuit group PV0 of the functional device setting area A02, there are multiple second pixel circuits PC2 located in the first pixel circuit group PV1 and multiple second pixel circuits PC2 located in the second pixel circuit group PV2. Any one of the second pixel circuits PC2 in the first pixel circuit group PV1 is selected as the seventh sub-circuit PC_7, and any one of the second pixel circuits PC2 in the second pixel circuit group PV2 is selected as the eighth sub-circuit PC_8. When the selected second pixel circuits PC2 are different, the seventh distance S7 can be different: for example, in the first pixel circuit group PV1 and the second pixel circuit group PV2, the second pixel circuit PC2 that is farthest from the second pixel circuit group PV2 along the first direction X is selected as the seventh... When sub-circuit PC_7 and the second pixel circuit PC2, which is furthest from the first pixel circuit column PV1, are selected as the eighth sub-circuit PC_8, the center distance between the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 along the first direction X is the maximum value of the seventh distance S7. For example, in the first pixel circuit column PV1 and the second pixel circuit column PV2, when the second pixel circuit PC2, which is closest to the second pixel circuit column PV2 along the first direction X, is selected as the seventh sub-circuit PC_7 and the second pixel circuit PC2, which is closest to the first pixel circuit column PV1, is selected as the eighth sub-circuit PC_8, the center distance between the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 along the first direction X is the minimum value of the seventh distance S7. Similarly, there are multiple second pixel circuits PC2 located in the second pixel circuit column PV2, and any one of them can be selected as the eighth sub-circuit PC_8; the first pixel circuit column PV1 in the pixel circuit column group PV0 adjacent to the pixel circuit column group PV0 where the second pixel circuit column PV2 is located also has multiple second pixel circuits PC2, and any one of them can be selected as the ninth sub-circuit PC_9; when the selected second pixel circuit PC2 is different, the eighth distance S8 can be different, and the eighth distance S8 also has a minimum value and a maximum value.

[0110] Generally, the larger the seventh distance S7, the larger the angle between the arrangement direction of the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 and the second direction Y, and the greater the bend in the first data signal line DL1 connecting the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8; conversely, the smaller the seventh distance S7, the smaller the angle between the arrangement direction of the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 and the second direction Y, and the less bend in the first data signal line DL1 connecting the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8. Since the space in the functional device setting area A02 is limited, the seventh distance S7 and the eighth distance S8 are negatively correlated: the smaller the eighth distance S8, the larger the seventh distance S7; and vice versa.

[0111] It is understandable that the seventh distance S7 and the eighth distance S8 are both the center distances of the two pixel circuits PC2. The center distance between the two second pixel circuits PC2 can be determined based on the center of the region where the second pixel circuit PC2 is located (the region where the transistor, the active region of the transistor, or the active structure is located in the second pixel circuit PC2). Alternatively, the region where the second pixel circuit PC2 is located can be approximated as a regular shape, such as a circle, rectangle, or square, and the geometric center of this regular shape is the center of the pixel circuit.

[0112] Specifically, if the seventh distance S7 is less than the eighth distance S8, then any seventh distance S7 is less than any eighth distance S8. That is, the maximum value of the seventh distance S7 can be less than the minimum value of the eighth distance S8, which can limit the maximum value of the seventh distance S7 to a small range (less than the minimum value of the eighth distance S8). The maximum center distance between any two second pixel circuits PC2 connected to the same first data signal line DL1 in the first direction X does not exceed the minimum value of the eighth distance S8. This can reduce the angle between the portion of the first data signal line DL1 located in the functional device setting area A02 and the second direction Y, reduce the degree of bending of the first data signal line DL1 in the functional device setting area A02, thereby reducing the design difficulty, improving the product yield, and avoiding excessive bending of the first data signal line DL1 in the functional device setting area A02, which would result in sharp or dense angles of the first data signal line DL1 in the functional device setting area A02. This would make the fabrication of the first data signal line DL1 prone to deformation, causing open circuits or short circuits, and affecting the reliability of the display panel 001.

[0113] For example, by setting a smaller seventh distance S7, the angle between the extension direction of the first data signal line DL1 located in the functional device setting area A02 and the second direction Y can be reduced. When the extension direction of the first data signal line DL1 changes, the angle between the extension direction of the first data signal line DL1 and the second direction Y before and / or after the change in extension direction can be reduced, which is beneficial to reduce the bending angle of the first data signal line DL1 and reduce the degree of bending of the first data signal line DL1 in the functional device setting area A02. Thus, when designing the first data signal line DL1 located in the functional device setting area A02, the bending angle of the first data signal line DL1 is small. That is, the included angle of the first data signal line DL1 before and after the change of extension direction is larger, closer to 180°. The included angle position of the first data signal line DL1 before and after the change of extension direction is not easily deformed. It is not necessary to consider the deformation problem caused by the included angle of the first data signal line DL1 too much, which helps to reduce the design difficulty. At the same time, the included angle of the first data signal line DL1 before and after the change of extension direction is larger and not easily deformed, which can also reduce open circuits or short circuits, which helps to improve product yield and the reliability of display panel 001.

[0114] For example, continue to refer to Figure 22 Compared to the first pixel circuit PC1 in the main display area A01, in the functional device setting area A02, the center distance between the second pixel circuit PC2 located in the first pixel circuit column PV1 and the second pixel circuit PC2 located in the second pixel circuit column PV2 in the same pixel circuit column group PV0 along the first direction X can be reduced, thereby reducing the seventh distance S7. In the same pixel circuit column group PV0, along the first direction X, the second pixel circuit PC2 located in the first pixel circuit column PV1 can be moved towards the direction closer to the second pixel circuit PC2 located in the second pixel circuit column PV2, and / or, the second pixel circuit PC2 located in the second pixel circuit column PV2 can be moved towards the direction closer to the second pixel circuit PC2 located in the first pixel circuit column PV1, that is... Figure 22 The second pixel circuit PC2, which corresponds to the second color light-emitting device LG, is moved to the left in the figure, and / or... Figure 2 and Figure 3 The second pixel circuit PC2, which corresponds to the first color light-emitting device LR and the third color light-emitting device GB, moves to the right in the figure. This effectively reduces the seventh distance S7, thereby reducing the bending degree of the first data signal line DL1 in the functional device setting area A02, reducing design difficulty, improving product yield and the reliability of the display panel 001.

[0115] In one implementation, continue to refer to Figure 22The color of the second light-emitting device D2 electrically connected to the seventh sub-circuit PC_7 is different from the color of the second light-emitting device D2 electrically connected to the eighth sub-circuit PC_8, and the arrangement direction of the seventh sub-circuit PC_7 and the eighth sub-circuit PC_8 intersects the second direction Y; the color of the second light-emitting device D2 electrically connected to the seventh sub-circuit PC_7 is the same as the color of the second light-emitting device D2 electrically connected to the ninth sub-circuit PC_9. This allows the seventh distance S7 to be a larger value and the eighth distance S8 to be a smaller value. Simultaneously, the seventh distance S7 is smaller than the eighth distance S8, ensuring that the maximum value of the seventh distance S7 is less than the minimum value of the eighth distance S8. This limits the seventh distance S7 to a smaller range, which is beneficial for reducing the bending degree of the first data signal line DL1 in the functional device setting area A02. In an optional embodiment, along the first direction X, the ninth sub-circuit PC_9 is located on the side of the eighth sub-circuit PC_8 away from the seventh sub-circuit PC_7.

[0116] In another embodiment, continue to refer to Figure 22 Along the first direction X, the maximum center distance between the first pixel circuits PC1 of the same pixel circuit column group PV0 is the ninth distance S9. The maximum value of the seventh distance S7 is less than the ninth distance S9. Therefore, compared with the main display area A01, the center distance between the pixel circuits of different pixel circuit columns in the same pixel circuit column group PV0 in the first direction X is reduced in the functional device setting area A02. This is beneficial to reduce the seventh distance S7 and reduce the degree of bending of the first data signal line DL1 in the functional device setting area A02.

[0117] In yet another implementation, continue to refer to Figure 22 Along the first direction X, the maximum center distance between adjacent first pixel circuits PC1 in adjacent pixel circuit column group PV0 is the tenth distance S10. The minimum value of the eighth distance S8 is greater than the tenth distance S10. Therefore, compared with the main display area A01 and the functional device setting area A02, the center distance of the pixel circuits in adjacent pixel circuit columns in adjacent pixel circuit column group PV0 in the first direction X has increased. This is beneficial to increase the eighth distance S8, thereby reducing the seventh distance S7 and reducing the degree of bending of the first data signal line DL1 in the functional device setting area A02.

[0118] It should be noted that the above description only illustrates, by way of example, that when the second pixel circuits PC2 located in the same pixel circuit group PV0 are all electrically connected to the first data signal line DL1, the seventh distance S7 is less than the eighth distance S8, the seventh distance S7 is less than the ninth distance S9, and the eighth distance S8 is greater than the tenth distance S10, which is beneficial to reducing the bending degree of the first data signal line DL1 in the functional device setting area A02. In other optional embodiments, the orthographic projection of the first data connection part DB1 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second data connection part DB2 on the plane where the display panel 001 is located, which is also beneficial to reducing the bending degree of the second data signal line DL2 in the functional device setting area A02; based on this, when the second pixel circuits PC2 in the same pixel circuit group PV0 are electrically connected to the first data signal line DL1 and the second data signal line DL2 respectively, the seventh distance S7 is less than the eighth distance S8, the seventh distance S7 is less than the ninth distance S9, and the eighth distance S8 is greater than the tenth distance S10, which is also beneficial to the bending degree of the first data signal line DL1 and / or the second data signal line DL2.

[0119] Optional, Figure 23 This is a partial top view of the fourth type of functional device setting area provided in the embodiments of this application, for reference. Figure 22 and Figure 23 The display panel 001 further includes a data signal line DL extending at least partially along the second direction Y; the data signal line DL includes a data connection portion DB located in the functional device setting area A02 and between two adjacent second pixel circuits PC2; the data signal line DL also includes a data extension portion DY located in the functional device setting area A02 and connected to the data connection portion DB and the second pixel circuit PC2 respectively; wherein the extension direction of the data extension portion DY intersects with the extension direction of the data connection portion DB electrically connected to the data extension portion DY.

[0120] Specifically, the data extension section DY can serve as a connection transition area for the data connection section DB, connecting to the second pixel circuit PC2. That is, the data connection section DB is electrically connected to the transistor in the second pixel circuit PC2 via the data extension section DY. The data connection section DB can be connected to any position of the data extension section DY. By setting the extension direction of the data extension section DY to intersect with the extension direction of the data connection section DB electrically connected to it, multi-angle extensions of the data connection section DB can be accommodated. Furthermore, by adjusting the position of the data connection section DB connected to the data extension section DY, the extension direction of the data connection section DB can be changed, which helps to reduce the bending degree of the data signal line DL in the functional device setting area A02, thereby improving product yield.

[0121] For example, taking the second pixel circuits PC2 located in the same pixel circuit column group PV0 as an example, all of which are electrically connected to the first data signal line DL1, and some of the second data signal lines DL2 can pass through the second pixel circuits PC2 but are not electrically connected to them, as an example. Figure 24 This is a schematic diagram of the structure of the fourth metal conductive layer of a second pixel circuit provided in an embodiment of this application. (Refer to...) Figure 16 , Figure 21 , Figure 23 and Figure 24 The data extension portion DY and the data connection portion DB electrically connected to it can be disposed on the same layer and form an integral structure. The data connection portion DB includes a first data connection portion DB1 located on the fourth metal conductive layer 140 and a second data connection portion DB2 located on the third metal conductive layer 130. The fourth metal conductive layer 140 also includes a first data extension portion DY1 connected to the first data connection portion DB1, and the third metal conductive layer 130 also includes a second data extension portion DY2 connected to the second data connection portion DB2. In other optional embodiments, the data extension portion DY and the data connection portion DB electrically connected to it can also be located on different conductive layers and overlapped by the extension portion. Figure 16 , Figure 21 , Figure 23 , Figure 24 (Not shown in the image).

[0122] Continuing with the example of a data extension section DY and a data connection section DB electrically connected to it being arranged on the same layer as a single structure, refer to... Figure 23 ,by Figure 23 With the center position as a reference, the data connection part DB, which is located above the second pixel circuit PC2 on the right and is electrically connected to the second pixel circuit PC2 on the right, can extend to the upper right. This allows the data connection part DB to connect to the rightmost position (e.g., the rightmost end) of the data extension part DY on the right. In this way, the angle between the data connection part DB and the data extension part DY on the right can be larger, reducing the difficulty of the process.

[0123] It should be noted that the figure only shows an example of the data extension DY having an arc-shaped structure. In other embodiments, the data extension DY may also have a straight-line structure. Figure 16 , Figure 23 , Figure 24 (not shown in the image), for example, the linear structure of the data extension DY can extend along the first direction X.

[0124] In an alternative implementation, refer to Figure 16 , Figure 23 and Figure 24The data extension portion DY has an arc-shaped structure and protrudes towards the data connection portion DB that is electrically connected to it. The data extension portion DY can protrude outwards from the second pixel circuit PC2 where it is located. This helps to increase the angle between the data extension portion DY and the data connection portion DB, avoiding an excessively small angle that would increase manufacturing complexity. Furthermore, an excessively small angle between the data extension portion DY and the data connection portion DB might increase the connection area, which is detrimental to increasing the light transmittance of the functional device placement area A02.

[0125] In another alternative implementation, the functional device setting area A02 may also pass through other signal lines, such as... Figure 23 The orthographic projection of signal line L'' on the plane of display panel 001 may overlap with the orthographic projection of data connection part DB on the plane of display panel 001, and / or the orthographic projection of signal line L'' on the plane of display panel 001 may overlap with the orthographic projection of scan connection part SB on the plane of display panel 001, so as to reduce the influence of signal line L'' passing through functional device setting area A02 on the transmittance of functional device setting area A02.

[0126] Optional, Figure 25 This is a top view structural diagram of the tenth type of display panel provided in the embodiments of this application, with reference to... Figure 25 The display panel 001 also includes a power signal line PL and a reset signal line RL, as well as a transparent conductive layer 210; part of the power signal line PL includes a first power part PB1 located in the functional device setting area A02; part of the reset signal line RL includes a first reset part RB1 located in the functional device setting area A02; the transparent conductive layer 210 includes the first power part PB1 and / or the first reset part RB1.

[0127] For example, refer to Figure 4 and Figure 25 The power signal line PL can be used to transmit the VDD signal and transmit it to the first transistor M1 and storage capacitor Cst of the second pixel circuit PC2; the reset signal line RL can be used to transmit the REF signal and transmit it to the initialization transistor M5 and reset transistor M7 of the second pixel circuit PC2. By making the portions of the power signal line PL and the reset signal line RL that are electrically connected to the second pixel circuit PC2 located in the functional device setting area A02 (first power supply part PB1, first reset part RB1) transparent traces, it is beneficial to increase the light transmittance of the functional device setting area A02.

[0128] In one embodiment, both the power signal line PL and the reset signal line RL are used to transmit signals at a fixed potential. For example, the conductivity of the transparent conductive layer 210 is typically lower than that of the metal conductive layer. By using the power signal line PL and the reset signal line RL to transmit signals at a fixed potential, it is beneficial to reduce the impact of setting the first power supply section PB1 and the first reset section RB1 as transparent traces on signal transmission. Simultaneously, setting the portions of the scan signal line SL and the data signal line DL, which are electrically connected to the second pixel circuit PC2, located in the functional device setting area A02 (scan connection section SB and data connection section DB) as metal traces helps to reduce signal delay and improve the charging speed of the second pixel circuit PC2.

[0129] In an alternative embodiment, reference continues. Figure 25 Both the first power supply unit PB1 and the first reset unit RB1 are located in the transparent conductive layer 210; the extension direction of the first power supply unit PB1 is the same as that of the first reset unit RB1. In this way, short circuits between the first power supply unit PB1 and the first reset unit RB1 can be avoided, and only one transparent conductive layer 210 needs to be provided, eliminating the need for multiple transparent conductive layers 210. This helps to reduce the number of film layers and preparation steps, and lower production costs.

[0130] It is understood that the first power supply unit PB1 and the first reset unit RB1 may both extend along the first direction X, or both extend along the second direction Y, or both extend along the third direction X'. The embodiments of this application do not specifically limit the extension direction of the first power supply unit PB1 and the first reset unit RB1.

[0131] In another alternative embodiment, Figure 26 This is a partial cross-sectional structural diagram of the third type of functional device setting area provided in the embodiments of this application, with reference to... Figure 25 and Figure 26 The display panel 001 also includes a first driving unit DR1 and a second driving unit DR2 disposed in the functional device setting area A02; the orthographic projection of the first driving unit DR1 on the plane where the display panel 001 is located overlaps with the orthographic projection of the second driving unit DR2 on the plane where the display panel 001 is located, and the overlapping area is the first area; the transparent conductive layer 210 is located between the conductive layer where the first driving unit DR1 is located and the conductive layer where the second driving unit DR2 is located; the orthographic projection of the transparent conductive layer 210 on the plane where the display panel 001 is located overlaps with the first area.

[0132] In this context, the first driving unit DR1 and the second driving unit DR2 refer to structures located in the functional device setting area A02, used for transmitting signals to drive the second pixel circuit PC2. In one embodiment, the first driving unit DR1 and the second driving unit DR2 may include a scan connection portion SB of the scan signal line SL; in another embodiment, the first driving unit DR1 and the second driving unit DR2 may include a data connection portion DB of the data signal line DL; in yet another embodiment, the first driving unit DR1 and the second driving unit DR2 may include a scan extension portion SY of the scan signal line SL; and in still another embodiment, the first driving unit DR1 and the second driving unit DR2 may include a data extension portion DY of the data signal line DL.

[0133] For example, the transparent conductive layer 210 includes a first power supply portion PB1 and a first reset portion RB1, both of which extend along the second direction Y; the first driving portion DR1 includes a first scan connection portion SB1 and / or a third scan connection portion SB3, which are located on the side of the transparent conductive layer 210 closer to the substrate 100; the second driving portion DR2 includes a second scan connection portion SB2, which is located on the side of the transparent conductive layer 210 away from the substrate 100. Along the direction perpendicular to the plane of the display panel 001, the first power supply portion PB1 and / or the first reset portion RB1 can overlap with the overlapping area (first area) of the first driving portion DR1 and the second driving portion DR2, which helps to reduce parasitic capacitance interference between the first driving portion DR1 and the second driving portion DR2.

[0134] Figure 27 This is a partial top view of the fifth type of functional device setting area provided in the embodiments of this application, for reference. Figure 27 The first driving unit DR1 may further include a first scanning extension SY1 and / or a third scanning extension SY3, wherein the first scanning extension SY1 and / or the third scanning extension SY3 are located on the side of the transparent conductive layer 210 near the substrate 100; the second driving unit DR2 may further include a second scanning extension SY2, wherein the second scanning extension SY2 is located on the side of the transparent conductive layer 210 away from the substrate 100. In other embodiments, the first power supply unit PB1 and the first reset unit RB1 may both extend along the first direction X, the first driving unit DR1 may further include a first data connection unit DB1 and / or a first data extension DY1, and the second driving unit DR2 may further include a second data connection unit DB2 and / or a second data extension DY2. Figures 25-27 (Not shown in the image).

[0135] The structure of the second pixel circuit PC2 will be illustrated below with reference to the structural diagrams of each film layer. For example, Figure 28This is a schematic diagram of the transparent conductive layer structure of a second pixel circuit provided in an embodiment of this application, with an active structure AS (such as...). Figure 6 As shown), the first metal conductive layer 110 (as shown) Figure 14 As shown), the second metal conductive layer 120 (as shown) Figure 15 As shown), transparent conductive layer 210 (as shown) Figure 28 As shown), the third metal conductive layer 130 (as shown) Figure 16 (as shown) and the fourth metal conductive layer 140 (as shown) Figure 24 (As shown) can be sequentially formed on one side of the substrate 100. Referring to the reference... Figure 4 The fourth metal conductive layer 140 also includes an extension portion H45, which is electrically connected to the first data extension portion DY1. The extension portion H45 can be electrically connected to the source or drain region near the channel AC2 of the write transistor M2 through the lap electrode DJ3 of the third metal conductive layer 130, the lap electrode DJ3' of the transparent conductive layer 210, and the lap electrode DJ3'' of the second metal conductive layer 120. The fourth metal conductive layer 140 also includes a lap electrode DJ4, which can be used to connect to the first light-emitting electrode of the second light-emitting device D2. The lap electrode DJ4 can also be electrically connected to the source or drain region near the channel AC6 of the second light-emitting control transistor M6 and the source or drain region near the channel AC7 of the reset transistor M7 through the lap electrode DJ4' of the third metal conductive layer 130, the lap electrode DJ4'' of the transparent conductive layer 210, and the lap electrode D67 of the second metal conductive layer 120.

[0136] The second scanning extension SY2 of the third metal conductive layer 130 can be electrically connected to the gate G1 of the first light-emitting control transistor M1 and the gate G6 of the second light-emitting control transistor M6 through the extension H33 and extension H34, the lap electrode DJ1 and lap electrode DJ2 of the transparent conductive layer 210, and the extension H13 and extension H14 of the first metal conductive layer 110; the second data extension DY2 of the third metal conductive layer 130 only passes through the second pixel circuit PC2 and is not electrically connected to the second pixel circuit PC2.

[0137] The transparent conductive layer 210 also includes an extension H07 connected to the first power supply unit PB1 and an extension H08 connected to the first reset unit RB1. The extension H07 can be electrically connected to the capacitor plate of the capacitor conductive layer through the lap electrode DJC1 of the second metal conductive layer 120. Figures 14-16(Not shown) and the source or drain region near the channel AC1 of the first light-emitting control transistor M1; the extension H08 can be electrically connected to the source or drain region near the channel AC5 of the initialization transistor M5 and the source or drain region near the channel AC7 of the reset transistor M7 via the lap electrode DJ57 of the second metal conductive layer 120.

[0138] The third scan extension SY3 of the second metal conductive layer 120 can be electrically connected to the gate G5 of the initialization transistor M5 and the gate G7 of the reset transistor M7 through extensions H21 and H22, and through extensions H11 and H12 of the first metal conductive layer 110. The second metal conductive layer 120 also includes a bridging electrode DJ234, which includes at least two extensions to respectively bridging the gate G3 of the driving transistor M3, the source or drain region near the channel AC4 of the compensation transistor M4, and the source or drain region near the channel AC5 of the initialization transistor M5. The first scan extension SY1 of the first metal conductive layer 110 can be connected to the gate G2 of the write transistor M2 and the gate G4 of the compensation transistor M4.

[0139] It should be noted that the above description of the structure of the second pixel circuit PC2, in conjunction with the structural diagrams of each film layer, is merely an illustrative example. The structure of the second pixel circuit PC2 is not limited thereto, and the embodiments of this application do not specifically limit the structure of the second pixel circuit PC2.

[0140] Optional, Figure 29 This is a schematic diagram of the structure of a light-shielding layer in a functional device setting area provided in an embodiment of this application. Figure 30 This is a partial cross-sectional structural diagram of the fourth type of display panel provided in the embodiments of this application, with reference to... Figure 21 , Figure 26 , Figure 29 and Figure 30 The display panel 001 further includes a bottom light-shielding structure BSM disposed in the functional device setting area A02 and a light-shielding connecting portion BB connecting adjacent bottom light-shielding structures BSM; the orthographic projection of the bottom light-shielding structure BSM on the plane of the display panel 001 overlaps with the orthographic projection of the second pixel circuit PC2 on the plane of the display panel 001. The display panel 001 also includes at least a data signal line DL extending along the second direction Y; the orthographic projection of the light-shielding connecting portion BB on the plane of the display panel 001 overlaps with the orthographic projection of the scan signal line SL on the plane of the display panel 001, and / or, the orthographic projection of the light-shielding connecting portion BB on the plane of the display panel 001 overlaps with the orthographic projection of the data signal line DL on the plane of the display panel 001.

[0141] The light-shielding connector BB is used to connect the bottom light-shielding structure BSM. The bottom light-shielding structures BSM are independent of each other. In one embodiment, the light-shielding connector BB and the bottom light-shielding structure BSM can be an integral structure.

[0142] For example, the display panel 001 includes a light-shielding layer 200, which is located on the side of the active structure AS, the first metal conductive layer 110, the second metal conductive layer 120, the third metal conductive layer 130, and the fourth metal conductive layer 140 of the second pixel circuit PC2 near the substrate 100. The light-shielding layer 200 includes a bottom light-shielding structure BSM and a light-shielding connection portion BB. The bottom light-shielding structure BSM can block at least part of the light transmitted from the substrate 100 to the active structure AS to prevent the light from affecting the carriers in the channel. In one embodiment, the light-shielding connection portion BB can transmit signals, which is beneficial for fixing the potential of the bottom light-shielding structure BSM, adjusting the threshold voltage of the transistor, and storing the potential of the floating conductive layer, thereby improving the performance and reliability of the second pixel circuit PC2. By setting independent bottom light-shielding structures BSM and light-shielding connecting parts BB that connect these independent bottom light-shielding structures BSM, and by having the bottom light-shielding structures BSM and the light-shielding connecting parts BB overlap with the second pixel circuit PC2 and the signal line respectively in a direction perpendicular to the plane where the display panel 001 is located, the light transmittance of the functional device setting area A02 can be improved while improving the performance and reliability of the second pixel circuit PC2, and the influence of the light-shielding layer 200 on the light transmittance of the functional device setting area A02 can be reduced.

[0143] Optional, Figure 31 This is a schematic diagram of the structure of the second electrode layer in a functional device setting area provided in an embodiment of this application. Figure 32 This is a partial cross-sectional structural diagram of the fifth type of functional device setting area provided in the embodiments of this application. Figure 33 This is a partial cross-sectional structural schematic diagram of the sixth type of functional device setting area provided in the embodiments of this application, with reference to... Figures 30-33The display panel 001 includes a substrate 100, a circuit layer 300 located on one side of the substrate 100, and a first electrode layer 410 and a second electrode layer 420 located on the side of the circuit layer 300 away from the substrate 100; the second electrode layer 420 is located on the side of the first electrode layer 410 away from the substrate 100. The circuit layer 300 includes a first pixel circuit PC1 located in the main display area A01 and a second pixel circuit PC2 located in the functional device setting area A02; the first electrode layer 410 includes at least a first light-emitting electrode E01 located in the functional device setting area A02, and the second electrode layer 420 includes at least a second light-emitting electrode EO2 located in the functional device setting area A02; the first light-emitting electrode E01 located in the functional device setting area A02 is electrically connected to the second pixel circuit PC2; in the functional device setting area A02, the second electrode layer 420 also includes an electrode connection portion EB connecting the second light-emitting electrode EO2. The display panel 001 also includes at least a data signal line DL extending along the second direction Y; the orthographic projection of the electrode connection portion EB on the plane where the display panel 001 is located overlaps with the orthographic projection of the scan signal line SL on the plane where the display panel 001 is located; and / or, the orthographic projection of the electrode connection portion EB on the plane where the display panel 001 is located overlaps with the orthographic projection of the data signal line DL on the plane where the display panel 001 is located.

[0144] The electrode connection part EB is used to connect the second light-emitting electrode EO2. The second light-emitting electrode EO2 is independent of each other. In one embodiment, the electrode connection part EB and the second light-emitting electrode EO2 can be an integral structure.

[0145] For example, the first light-emitting electrode E01 can receive the driving current provided by the second pixel circuit PC2, and the second light-emitting electrode E02 can receive a common electrical signal, such as a VEE signal. The electrode connection portion EB can make the potential of each second light-emitting electrode E02 the potential of the VEE signal. Independent second light-emitting electrodes E02 and electrode connection portions EB connecting these independent second light-emitting electrodes E02 are provided in the functional device setting area A02. Furthermore, along a direction perpendicular to the plane of the display panel 001, the second light-emitting electrodes E02 and the electrode connection portions EB overlap with the second pixel circuit PC2 and the signal lines, respectively, which helps to reduce the impact of the second electrode layer 420 on the light transmittance of the functional device setting area A02.

[0146] Based on the same inventive concept, embodiments of this application also provide a display device. Figure 34 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 34 As shown, the display device 002 includes the display panel 001 provided in any embodiment of this application. The display device 002 provided in the embodiments of this application can be... Figure 34The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0147] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: A functional device setting area and a main display area that at least partially surrounds the functional device setting area; The display panel further includes a plurality of first sub-pixels and a plurality of second sub-pixels; the first sub-pixel includes a first light-emitting device and a first pixel circuit located in the main display area; the second sub-pixel includes a second light-emitting device and a second pixel circuit located in the functional device setting area; the density of the first sub-pixels in the main display area is greater than the density of the second sub-pixels in the functional device setting area; The display panel also includes at least a portion of scan signal lines extending along the first direction; The plurality of second pixel circuits include a first sub-circuit, a second sub-circuit, and a third sub-circuit; the first sub-circuit and the second sub-circuit are connected to the same scan signal line, and the scan signal line connected to the second sub-circuit and the scan signal line connected to the third sub-circuit are arranged adjacent to each other. Along the second direction, the center distance between the first sub-circuit and the second sub-circuit is a first distance, and the center distance between the second sub-circuit and the third sub-circuit is a second distance, wherein the first distance is less than the second distance; wherein the first direction intersects the second direction, and both the first direction and the second direction are parallel to the plane on which the display panel is located.

2. The display panel according to claim 1, characterized in that, The color of the second light-emitting device electrically connected to the first sub-circuit is different from the color of the second light-emitting device electrically connected to the second sub-circuit. The first sub-circuit and the second sub-circuit are arranged along a third direction, which is parallel to the plane where the display panel is located. The third direction intersects with the first direction and also intersects with the second direction. The color of the second light-emitting device electrically connected to the first sub-circuit is the same as the color of the second light-emitting device electrically connected to the third sub-circuit.

3. The display panel according to claim 1, characterized in that, Along the second direction, the length of the second pixel circuit is less than the length of the first pixel circuit.

4. The display panel according to claim 3, characterized in that, The display panel includes a semiconductor layer; the semiconductor layer located in the functional device setting area includes an active structure of the second pixel circuit; the active structure of the second pixel circuit includes a channel for driving transistors in the second pixel circuit; In this circuit, the channel of the driving transistor in the second pixel circuit has a linear structure.

5. The display panel according to claim 4, characterized in that, The linear structure extends along the first direction; Along the first direction, the maximum size of the active structure of the second pixel circuit is LM1; Along the second direction, the maximum size of the active structure of the second pixel circuit is LM2; Where 0.9×LM1≤LM2≤1.1×LM1.

6. The display panel according to claim 1, characterized in that, In the same second sub-pixel, the orthographic projection of the second pixel circuit on the plane where the display panel is located overlaps with the orthographic projection of the second light-emitting device on the plane where the display panel is located; The first pixel circuit includes a fourth sub-circuit and a fifth sub-circuit; the fourth sub-circuit and the fifth sub-circuit are connected to the same scan signal line; Along the second direction, the maximum center distance between the first light-emitting device electrically connected to the fourth sub-circuit and the first light-emitting device electrically connected to the fifth sub-circuit is the third distance, and the maximum center distance between the second light-emitting device electrically connected to the first sub-circuit and the second light-emitting device electrically connected to the second sub-circuit is the fourth distance, which is less than the third distance.

7. The display panel according to claim 6, characterized in that, The color of the first light-emitting device electrically connected to the fourth sub-circuit is different from the color of the first light-emitting device electrically connected to the fifth sub-circuit, and the fourth sub-circuit and the fifth sub-circuit are arranged adjacent to each other; The color of the second light-emitting device electrically connected to the first sub-circuit is different from the color of the second light-emitting device electrically connected to the second sub-circuit. The second light-emitting devices electrically connected to the first sub-circuit and the second light-emitting devices electrically connected to the second sub-circuit are arranged along a third direction, which is parallel to the plane where the display panel is located. The third direction intersects with the first direction and also intersects with the second direction.

8. The display panel according to claim 1, characterized in that, The display panel includes a first pixel circuit row and a second pixel circuit row that extend along the first direction and are alternately arranged along the second direction, and a first pixel circuit column and a second pixel circuit column that extend along the second direction and are alternately arranged along the first direction. Adjacent rows of the first pixel circuit and the second pixel circuit form a pixel circuit row group; adjacent columns of the first pixel circuit and the second pixel circuit form a pixel circuit column group. In the main display area, the number of first pixel circuits located in the same pixel circuit row group and the same pixel circuit column group is a first number; in the functional device setting area, the number of second pixel circuits located in the same pixel circuit row group and the same pixel circuit column group is a second number; the first number is greater than the second number.

9. The display panel according to claim 8, characterized in that, In the functional device setting area, within the same pixel circuit row group, the second pixel circuits located in the same pixel circuit column group are located in different pixel circuit rows and different pixel circuit columns.

10. The display panel according to claim 1, characterized in that, The scan signal line includes a scan connection portion located in the functional device setting area and connecting two adjacent second pixel circuits; the scan connection portion includes a first scan connection portion and a second scan connection portion; The scanning signal line includes a first scanning signal line and a second scanning signal line; part of the first scanning signal line includes a first scanning connection portion, and part of the second scanning signal line includes a second scanning connection portion, wherein the orthographic projection of the first scanning connection portion on the plane where the display panel is located overlaps with the orthographic projection of the second scanning connection portion on the plane where the display panel is located.

11. The display panel according to claim 10, characterized in that, The scanning signal line further includes a third scanning signal line; the scanning connection part further includes a third scanning connection part; The third scan signal line includes the third scan connection portion; the conductive layer where the third scan connection portion is located is located between the conductive layer where the first scan connection portion is located and the conductive layer where the second scan connection portion is located. The orthographic projection of the third scanning connection part on the plane where the display panel is located overlaps with the orthographic projection of the first scanning connection part on the plane where the display panel is located, and the orthographic projection of the third scanning connection part on the plane where the display panel is located overlaps with the orthographic projection of the second scanning connection part on the plane where the display panel is located.

12. The display panel according to claim 11, characterized in that, The second pixel circuit includes a driving transistor, a writing transistor, a light-emitting control transistor, and a reset transistor; The driving transistor is electrically connected to the reset transistor, the write transistor, and the light-emitting control transistor, respectively; the reset transistor is used to transmit a reset signal when it is turned on, the write transistor is used to transmit a data signal when it is turned on, and the light-emitting control transistor is used to control the driving transistor to provide driving current when it is turned on. In the second pixel circuit, the gate of the write transistor is electrically connected to the first scan signal line, the gate of the light-emitting control transistor is electrically connected to the second scan signal line, and the gate of the reset transistor is electrically connected to the third scan signal line.

13. The display panel according to claim 1, characterized in that, The scan signal line includes a scan connection portion located in the functional device setting area and connecting two adjacent second pixel circuits; The scanning signal line also includes a scanning extension located in the functional device setting area, which connects the scanning connection portion and the second pixel circuit respectively; wherein the extension direction of the scanning extension portion intersects with the extension direction of the scanning connection portion to which the scanning extension portion is electrically connected.

14. The display panel according to claim 13, characterized in that, The scanning extension has an arc-shaped structure and protrudes toward the scanning connection portion that is electrically connected to the scanning extension.

15. The display panel according to claim 1, characterized in that, The display panel includes a first pixel circuit column and a second pixel circuit column that extend along the second direction and are alternately arranged along the first direction; The display panel further includes at least a portion of a data signal line extending along the second direction; the data signal line includes a data connection portion located in the functional device setting area and between two adjacent second pixel circuits; the data connection portion includes a first data connection portion and a second data connection portion; The data signal line includes a first data signal line electrically connected to the first pixel circuit in the first pixel circuit column, and a second data signal line electrically connected to the first pixel circuit in the second pixel circuit column; A portion of the first data signal line includes the first data connection portion, and a portion of the second data signal line includes the second data connection portion. The orthographic projection of the first data connection portion onto the plane where the display panel is located overlaps with the orthographic projection of the second data connection portion onto the plane where the display panel is located.

16. The display panel according to claim 1, characterized in that, The display panel includes a first pixel circuit column and a second pixel circuit column that extend along the second direction and are alternately arranged along the first direction; adjacent first pixel circuit columns and second pixel circuit columns form a pixel circuit column group; The display panel further includes at least a portion of data signal lines extending along the second direction; the data signal lines include adjacent first data signal lines and second data signal lines; the first data signal lines are electrically connected to the first pixel circuit in the first pixel circuit column, and the second data signal lines are electrically connected to the first pixel circuit in the second pixel circuit column; The second pixel circuits located in the same pixel circuit group are all electrically connected to the first data signal line.

17. The display panel according to claim 16, characterized in that, The second pixel circuit includes a seventh sub-circuit, an eighth sub-circuit, and a ninth sub-circuit; the seventh sub-circuit and the eighth sub-circuit are located in the same pixel circuit column group, the pixel circuit column group where the ninth sub-circuit is located is arranged adjacent to the pixel circuit column group where the eighth sub-circuit is located, the seventh sub-circuit and the ninth sub-circuit are both located in the first pixel circuit column, and the eighth sub-circuit is located in the second pixel circuit column; Along the first direction, the center distance between the seventh sub-circuit and the eighth sub-circuit is the seventh distance, and the center distance between the eighth sub-circuit and the ninth sub-circuit is the eighth distance. The seventh distance is less than the eighth distance.

18. The display panel according to claim 1, characterized in that, The display panel further includes at least a portion of a data signal line extending along the second direction; the data signal line includes a data connection portion located in the functional device setting area and between two adjacent second pixel circuits; The data signal line also includes a data extension located in the functional device setting area, which is connected to the data connection portion and the second pixel circuit respectively; wherein the extension direction of the data extension portion intersects with the extension direction of the data connection portion to which the data extension portion is electrically connected.

19. The display panel according to claim 1, characterized in that, The display panel also includes power signal lines and reset signal lines, as well as a transparent conductive layer; Some of the power signal lines include a first power supply section located in the functional device setting area; The reset signal line includes a first reset section located in the functional device setting area; The transparent conductive layer includes the first power supply section and / or the first reset section.

20. The display panel according to claim 19, characterized in that, Both the first power supply unit and the first reset unit are located in the transparent conductive layer; The extension direction of the first power supply unit is the same as the extension direction of the first reset unit.

21. The display panel according to claim 19, characterized in that, The display panel further includes a first driving part and a second driving part disposed in the functional device setting area; The orthographic projection of the first driving unit onto the plane where the display panel is located overlaps with the orthographic projection of the second driving unit onto the plane where the display panel is located, and the overlapping area is the first area; The transparent conductive layer is located between the conductive layer where the first driving part is located and the conductive layer where the second driving part is located; The orthographic projection of the transparent conductive layer onto the plane of the display panel overlaps with the first region.

22. The display panel according to claim 1, characterized in that, The display panel further includes a bottom light-shielding structure disposed in the functional device setting area and a light-shielding connecting part connecting adjacent bottom light-shielding structures; the orthographic projection of the bottom light-shielding structure on the plane where the display panel is located overlaps with the orthographic projection of the second pixel circuit on the plane where the display panel is located; The display panel also includes at least a portion of data signal lines extending along the second direction; The orthographic projection of the light-shielding connection portion onto the plane of the display panel overlaps with the orthographic projection of the scanning signal line onto the plane of the display panel; and / or, the orthographic projection of the light-shielding connection portion onto the plane of the display panel overlaps with the orthographic projection of the data signal line onto the plane of the display panel.

23. The display panel according to claim 1, characterized in that, The display panel includes a substrate, a circuit layer located on one side of the substrate, and a first electrode layer and a second electrode layer located on the side of the circuit layer away from the substrate; the second electrode layer is located on the side of the first electrode layer away from the substrate. The circuit layer includes a first pixel circuit located in the main display area and a second pixel circuit located in the functional device setting area; the first electrode layer includes at least a first light-emitting electrode located in the functional device setting area, and the second electrode layer includes at least a second light-emitting electrode located in the functional device setting area. The first light-emitting electrode located in the functional device setting area is electrically connected to the second pixel circuit; In the functional device setting area, the second electrode layer further includes an electrode connection portion that connects to the second light-emitting electrode; The display panel also includes at least a portion of data signal lines extending along the second direction; The orthographic projection of the electrode connection portion onto the plane of the display panel overlaps with the orthographic projection of the scan signal line onto the plane of the display panel; and / or, the orthographic projection of the electrode connection portion onto the plane of the display panel overlaps with the orthographic projection of the data signal line onto the plane of the display panel.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1-23.

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