Metal interlevel dielectric layer test structure

Abstract

This invention discloses a test structure for an inter-metal dielectric layer, comprising a test region structure and a pad region structure. The test region structure has first and second metal patterned structures spaced apart from each other to be tested IMD (Inter-Mechanical Diode) layer; no vias are formed in any of the via layers between the first and second metal patterned structures and the top surface of the semiconductor substrate. The pad region structure includes multiple layers of first and second PAD metal layers, with a first electrode and a second electrode respectively led out. No vias are formed in at least one or more via layers between the first PAD metal layer (connecting to the first metal patterned structure) and the first PAD metal layer (connecting to the second metal patterned structure) and the semiconductor substrate. This invention prevents breakdown of the inter-layer film between the upper and lower metal layers in the test structure, thus ensuring the normal testing of the inter-metal dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a metal interlayer dielectric (IMD) test structure. Background Technology

[0002] Intermetallic dielectric (IMD) testing is a critical technology in semiconductor manufacturing processes, significantly impacting product yield and reliability. IMD test structures are used to characterize weak points in the intermetallic dielectric during back-end processes (BEOL). Commonly used IMD breakdown test structures can be categorized into three main types: MxMx, VxMx+1, and MOM.

[0003] like Figure 1 The diagram shows a schematic of an MxMx structure in an existing interlayer dielectric layer test structure. The MxMx structure includes patterns 101a, 102a, 101b, and 102b of the xth metal layer, where x represents the layer number to which the metal layer belongs, and is an integer. One end of multiple bar-finger-shaped patterns 102a is connected to pattern 101a, and one end of multiple bar-finger-shaped patterns 102b is connected to pattern 101b. Between patterns 101a and 101b, patterns 102a and 102b are arranged alternately to form an interdigitated structure.

[0004] like Figure 2 The diagram shows a schematic of the VxMx+1 structure in an existing interlayer dielectric layer test structure. The VxMx+1 structure includes patterns 101c and 102c of the xth metal layer, a via 103 of the xth layer located on pattern 102c, and patterns 101d and 102d of the (x+1)th metal layer. One end of multiple strip-finger-shaped patterns 102c is connected to pattern 101c, and one end of multiple strip-finger-shaped patterns 102d is connected to pattern 101d. In top view, patterns 102c and 102d are alternately arranged between patterns 101c and 101d to form an interdigitated structure.

[0005] like Figure 3 The diagram shown is a schematic of the MOM structure in existing inter-metal dielectric layer testing structures; the MOM structure includes multiple aligned MxMx structures. Figure 3 The image shows a three-layer MxMx structure. The topmost MxMx structure includes patterns 101e, 102e, 101f, and 102f. Between patterns 101e and 101f, patterns 102e and 102f, arranged in a bar-finger structure, alternate to form an interdigitated structure. On the top view, the bottom MxMx structures are identical to and aligned with the topmost MxMx structure. The aligned metal layer patterns and the interlayer film (ILD) between the metal layers form a MOM capacitor.

[0006] Different interlayer spacings (i.e., the distance between metal layers in an Integrated Device Modulation) result in different maximum operating voltages. Design rules stipulate that a larger interlayer spacing corresponds to a larger maximum operating voltage. With advancements in semiconductor technology and increasingly sophisticated manufacturing processes, not only are metal linewidths decreasing, but the spacing between upper and lower metal layers is also becoming closer. When the interlayer spacing is significantly larger than the spacing between upper and lower metal layers, dielectric breakdown may occur during reliability testing of the dielectric layer, affecting the reliability assessment of the IMD. Therefore, an effective structure is urgently needed to evaluate the reliability of dielectric layers with large spacing between metal layers.

[0007] like Figure 4 The diagram shown is a schematic of the breakdown of the interlayer film between the upper and lower metal layers in an existing interlayer dielectric layer test structure. Figure 4 The semiconductor substrate 201 is shown. The metal layers included in the inter-metal dielectric layer test structure are indicated by the symbol 204. In addition, the first to fourth metal layers are indicated by M1, M2, M3 and M4 respectively. Figure 4 The diagram also shows the zeroth metal layer 202 of the active region, which is also denoted by M0A; each via is denoted by 203, with the zeroth via also denoted by V0. It can be seen that there are conductive paths between the semiconductor substrate 201 and the top metal layers. Thus, during testing, when a positive voltage is applied to a certain electrode, for example, a voltage is applied to metal layer M4, a negative charge will be induced in the lower metal layer. When the voltage is very high, breakdown between the upper and lower layers will occur. Figure 4 In the middle, when a positive voltage is applied to the metal layer M4, it has a positive charge 206, while the metal layer M3 below it is induced with a negative charge, namely electrons 205b. When the voltage is very high, the interlayer film between the metal layers M4 and M3 is prone to breakdown as shown by mark 207. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a test structure for intermetallic dielectric layers that can prevent the breakdown of the interlayer film between the upper and lower metal layers in the test structure, thereby ensuring the normal testing of the intermetallic dielectric layer.

[0009] To solve the above-mentioned technical problems, the metal interlayer dielectric layer test structure provided by the present invention includes: a test area structure and a pad (PAD) area structure.

[0010] The test area structure has a first metal pattern structure and a second metal pattern structure, with a corresponding IMD layer to be tested spaced between the first metal pattern structure and the second metal pattern structure; no vias are formed in each via layer between the first metal pattern structure, the second metal pattern structure and the top surface of the semiconductor substrate, so that there is no conductive path between the first metal pattern structure and the semiconductor substrate and between the second metal pattern structure and the semiconductor substrate.

[0011] The PAD area structure includes multiple layers of first PAD metal layers and multiple layers of second PAD metal layers.

[0012] In the multilayer first PAD metal layer, there is a first PAD metal layer with interconnection layer connected to the first metal pattern structure. The first PAD metal layers above the first PAD metal layer are connected together through vias and lead out the first electrode of the first metal pattern structure. Between the first PAD metal layer with interconnection layer and the semiconductor substrate, at least one or more via layers do not form the vias, so that there is no conductive path between the first electrode and the semiconductor substrate.

[0013] In the multilayer second PAD metal layer, there is a second PAD metal layer with interconnection layer connected to the second metal pattern structure. The second PAD metal layers above the interconnection layer are connected together through vias and lead out the second electrode of the second metal pattern structure. Between the interconnection layer and the semiconductor substrate, at least one or more via layers do not form the vias, so that there is no conductive path between the second electrode and the semiconductor substrate.

[0014] A further improvement is that the test area structure includes an MxMx structure, where Mx represents the xth metal layer and x is an integer; in the MxMx structure, both the first metal pattern structure and the second metal pattern structure are patterns of the xth metal layer, and on the top view, the first metal pattern structure and the second metal pattern structure form an interdigitated structure.

[0015] A further improvement is that the test area structure includes a VxMx+1 structure, where Vx represents the xth via layer, Mx+1 represents the (x+1)th metal layer, and x is an integer; in the VxMx+1 structure, the first metal pattern structure includes the pattern of the xth metal layer, and the second metal pattern structure includes the (x+1)th metal layer. On the top view, the first metal pattern structure and the second metal pattern structure form an interdigitated structure; multiple xth vias are formed on the top of each of the strip fingers of the first metal pattern structure.

[0016] A further improvement is that the test area structure includes a MOM structure.

[0017] A further improvement is that, in the layout of the test area structure, a dummy via block layer is added to each of the via layers between the first metal pattern structure, the second metal pattern structure, and the top surface of the semiconductor substrate to prevent the via from being generated in the OPC.

[0018] A further improvement is that, in the PAD region structure, the layout of the vias in each of the via layers between the first PAD metal layer of the interconnect layer and the semiconductor substrate is deleted to eliminate the vias; the layout of the vias in each of the via layers between the second PAD metal layer of the interconnect layer and the semiconductor substrate is also deleted to eliminate the vias.

[0019] A further improvement is that the semiconductor substrate has P-type doping.

[0020] A further improvement is that an N-type well region is formed at least in the surface region of the semiconductor substrate directly below the PAD region structure.

[0021] A further improvement is that the width of the IMD layer to be tested, which is the gap between the first metal pattern structure and the second metal pattern structure, is greater than the thickness of the interlayer film between two adjacent metal layers.

[0022] In the intermetallic dielectric layer test structure of this invention, the vias at the bottom of the test area structure and the PAD area structure are eliminated. This prevents the first and second metal pattern structures of the test area structure, as well as the first and second electrodes of the PAD area structure, from forming conductive paths with the semiconductor substrate. This prevents electrons accumulated on the semiconductor substrate from moving upwards along the vias and metal layers during testing, and thus prevents the interlayer film between the upper and lower metal layers from being broken down by accumulated electrons. This ensures the normal testing of the IMD layer between the first and second metal pattern structures. Furthermore, this invention eliminates the vias in each via layer between the first and second metal pattern structures and the top surface of the semiconductor substrate, as well as the vias between the first PAD metal layer and the semiconductor substrate, and between the first PAD metal layer and the semiconductor substrate. Therefore, this invention prevents the breakdown of the interlayer film between the upper and lower metal layers in the test structure, thus ensuring the normal testing of the intermetallic dielectric layer. Attached Figure Description

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1This is a schematic diagram of the MxMx structure in the existing interlayer dielectric layer test structure; Figure 2 This is a schematic diagram of the VxMx+1 structure in the existing inter-metal dielectric layer test structure; Figure 3 This is a schematic diagram of the MOM structure in the existing interlayer dielectric layer test structure; Figure 4 This is a schematic diagram of the breakdown of the interlayer film between the upper and lower metal layers in an existing metal interlayer dielectric layer test structure; Figure 5 This is a top view of the test structure of the interlayer dielectric layer of the metal according to the first embodiment of the present invention; Figure 6 This is a side view of the test structure of the inter-metal dielectric layer according to the first embodiment of the present invention; Figure 7 This is a top view of the test structure of the inter-metal dielectric layer according to the second embodiment of the present invention; Figure 8 This is a side view of the test structure of the inter-metal dielectric layer according to the second embodiment of the present invention; Figure 9 This is a schematic diagram of the test structure for the interlayer dielectric layer of the metal layer in an embodiment of the present invention to prevent the breakdown of the interlayer film between the upper and lower metal layers. Detailed Implementation

[0024] like Figure 5 The image shown is a top view of the test structure for the inter-metal dielectric layer according to the first embodiment of the present invention; as shown... Figure 6 The image shown is a side view of the inter-metal dielectric layer test structure according to the first embodiment of the present invention; the inter-metal dielectric layer test structure 301a according to the first embodiment of the present invention includes: a test area structure 302 and a PAD area structure.

[0025] The test area structure 302 has a first metal pattern structure and a second metal pattern structure, with a corresponding IMD layer to be tested spaced between the first metal pattern structure and the second metal pattern structure; no vias 306 are formed in each via layer between the first metal pattern structure, the second metal pattern structure and the top surface of the semiconductor substrate 401, so that there is no conductive path between the first metal pattern structure and the semiconductor substrate 401 and between the second metal pattern structure and the semiconductor substrate 401.

[0026] In the first embodiment of the present invention, the test area structure 302 includes an MxMx structure, where Mx represents the xth metal layer and x is an integer; in the MxMx structure, the first metal pattern structure and the second metal pattern structure are both patterns of the xth metal layer, and on the top view, the first metal pattern structure and the second metal pattern structure form an interdigitated structure. Figure 5 In the first metal pattern structure, there are pattern 303a and multiple parallel patterns 304a, and the second metal pattern structure includes pattern 303b and multiple parallel patterns 304b. Between patterns 303a and 303b, patterns 304a and 304b, which are in the form of bar-finger structures, are alternately arranged to form the interdigitated structure.

[0027] The PAD area structure includes multiple layers of first PAD metal layers and multiple layers of second PAD metal layers. Mark 305a indicates multiple layers of the first PAD metal layer, and mark 305b indicates multiple layers of the second PAD metal layer.

[0028] like Figure 6 As shown, the first PAD metal layer in the multilayer structure includes a first PAD metal layer 305a1 with interconnecting layers connected to the first metal pattern structure. Because... Figure 6 This is a side view, therefore Figure 6 In the diagram, the test area structure 302 is shown as a metallic pattern structure. The first PAD metal layers above the first PAD metal layer 305a1 in the interconnect layer are connected together through vias 306, leading out the first electrode of the first metallic pattern structure. Between the first PAD metal layer 305a1 in the interconnect layer and the semiconductor substrate 401, at least one via layer does not form the via 306, so that there is no conductive path between the first electrode and the semiconductor substrate 401. Figure 6 In this configuration, no vias 306 are formed between the first PAD metal layer 305a1 of the interconnect layer and the semiconductor substrate 401. In the multilayer second PAD metal layer, an interconnect layer second PAD metal layer 305b1 connected to the second metal pattern structure is included. Each layer of the second PAD metal layer above the interconnect layer second PAD metal layer 305b1 is connected together through vias 306, leading out the second electrode of the second metal pattern structure. No vias 306 are formed in at least one or more via layers between the interconnect layer second PAD metal layer 305b1 and the semiconductor substrate 401, so that there is no conductive path between the second electrode and the semiconductor substrate 401. Figure 6As can be seen, in the first embodiment of the present invention, outside the inter-metal dielectric layer test structure 301a (not shown), there are vias 306 in each of the via layers between the metal layer corresponding to the first PAD metal layer 305a1 of the interconnect layer and the semiconductor substrate 401. However, the vias 306 are not formed in the region of the inter-metal dielectric layer test structure 301a. Therefore, it is possible to prevent the charge accumulation generated on the semiconductor substrate 401 from moving to each metal layer of the inter-metal dielectric layer test structure 301a, thereby preventing the breakdown of the inter-metal layer film (ILD) generated therefrom.

[0029] In the first embodiment of the present invention, in the layout of the test area structure 302, a pseudo-via blocking layer is added in each of the via layers between the first metal pattern structure, the second metal pattern structure and the top surface of the semiconductor substrate 401 to prevent the via 306 from being generated in the OPC.

[0030] In the PAD region structure, the layout of the vias 306 in each of the via layers between the first PAD metal layer 305a1 of the interconnect layer and the semiconductor substrate 401 is deleted to eliminate the vias 306; the layout of the vias 306 in each of the via layers between the second PAD metal layer 305b1 of the interconnect layer and the semiconductor substrate 401 is deleted to eliminate the vias 306.

[0031] In other embodiments, the test area structure 302 may also include a VxMx+1 structure, where Vx represents the x-th via layer, Mx+1 represents the (x+1)-th metal layer, and x is an integer; the VxMx+1 structure may also refer to Figure 2 As shown, in the VxMx+1 structure, the first metal pattern structure includes a pattern of the xth metal layer, and the second metal pattern structure includes the x+1th metal layer. On the top view, the first metal pattern structure and the second metal pattern structure form an interdigitated structure; multiple xth layer through holes are formed on the top of each strip finger of the first metal pattern structure. Figure 2 In the diagram, the xth metal layer includes patterns 101c and 102c, and the (x+1)th metal layer includes patterns 101d and 102d. Between patterns 101c and 101d, patterns 102c and 102d, which are in the form of bar-finger structures, are alternately arranged to form an interdigitated structure. Multiple through-holes 103 are formed on the top of pattern 102c.

[0032] In other embodiments, the test area structure 302 may also include a MOM structure. Please also refer to the MOM structure. Figure 3 As shown, the MOM structure includes multiple aligned MxMx structures. Figure 3The image shows a 4-layer MxMx structure. The top MxMx structure includes patterns 101e, 102e, 101f, and 102f. Between patterns 101e and 101f, patterns 102e and 102f, which are bar-finger structures, are arranged alternately to form an interdigitated structure.

[0033] In the first embodiment of the present invention, the semiconductor substrate 401 is P-type doped. In other embodiments, the semiconductor substrate 401 may also be N-type doped. Figure 6 In this context, the semiconductor substrate 401 is also referred to as Substrate.

[0034] In the first embodiment of the present invention, the width of the IMD layer to be tested, which is the gap between the first metal pattern structure and the second metal pattern structure, is greater than the thickness of the interlayer film between two adjacent metal layers. In this case, the IMD layer to be tested is a large-pitch IMD layer. Existing large-pitch IMD layer test structures are prone to defects where the interlayer film between two adjacent metal layers breaks down before the large-pitch IMD layer, thus making it impossible to measure the large-pitch IMD layer.

[0035] In the metal interlayer dielectric layer test structure of the first embodiment of the present invention, the vias 306 at the bottom of the test area structure 302 and the PAD area structure are eliminated. This prevents the first and second metal pattern structures of the test area structure 302, as well as the first and second electrodes of the PAD area structure, from forming conductive paths with the semiconductor substrate 401. This prevents electrons accumulated on the semiconductor substrate 401 from moving upwards along the vias 306 and the metal layers during testing, and also prevents the interlayer film between the upper and lower metal layers from being broken down by accumulated electrons. This ensures that the testing of the IMD layer between the first and second metal pattern structures can proceed normally. Furthermore, the first embodiment of the present invention eliminates the vias 306 in each via layer between the first and second metal pattern structures and the top surface of the semiconductor substrate 401, as well as the vias 306 between the first PAD metal layer 305a1 and the semiconductor substrate 401, and between the first PAD metal layer 305a1 and the semiconductor substrate 401. Therefore, the first embodiment of the present invention can prevent the breakdown of the interlayer film between the upper and lower metal layers in the test structure, thereby ensuring the normal testing of the interlayer dielectric layer.

[0036] like Figure 7 The image shown is a top view of the test structure for the inter-metal dielectric layer according to the second embodiment of the present invention; as shown... Figure 8 The image shown is a side view of the inter-metal dielectric layer test structure according to the second embodiment of the present invention; the difference between the second embodiment and the inter-metal dielectric layer test structure 301a is that, in the second embodiment of the inter-metal dielectric layer test structure 301b: An N-type well region 402 is formed at least in the surface region of the semiconductor substrate 401 directly below the PAD region structure.

[0037] and Figure 5 Compared to the top view, Figure 7 The N-type well region 402 is shown in the image, but the semiconductor substrate 401 is not shown.

[0038] and Figure 6 compared to, Figure 8 In the diagram, the multilayer first PAD metal layer corresponding to mark 305c and Figure 6 The number of layers of the first PAD metal layer corresponding to mark 305a has changed, and the number of layers of the second PAD metal layer corresponding to mark 305d has changed. Figure 6 The number of layers in the second PAD metal layer corresponding to mark 305b has changed. Additionally, Figure 8 In the interconnect layer, the via 306 is further formed in the bottom via layer of the first PAD metal layer 305c1 and the second PAD metal layer 305d1. In other embodiments, the multilayer first PAD metal layer corresponding to 305c can be connected to... Figure 6 The structure of the multilayer first PAD metal layer corresponding to mark 305a is the same, and the structure of the multilayer second PAD metal layer corresponding to mark 305d is the same as that of the first PAD metal layer. Figure 6 The structure of the multilayer second PAD metal layer corresponding to mark 305b is the same.

[0039] like Figure 9 The diagram shown is a schematic representation of a test structure for preventing breakdown of the interlayer dielectric layer between upper and lower metal layers according to an embodiment of the present invention. Figure 9 The text shows and Figure 6 Using the same semiconductor substrate 401, the metal layers included in the inter-metal dielectric layer test structure 301a are designated by 402. Furthermore, the first to fourth metal layers are designated by M1, M2, M3, and M4, respectively. It can be seen that electrons 404 accumulated on the top surface of the semiconductor substrate 401 will not move into the metal layers, especially onto the metal layer M3 below the metal layer M4 where holes 405 have accumulated. Therefore, this embodiment of the invention can prevent... Figure 4 Breakdown of the ILD layer between the upper and lower metal layers corresponding to mark 207.

[0040] In the first embodiment of the present invention, a dummy via block layer is added to the inter-metal dielectric layer test structure to ensure that the dummy metal layer, i.e., the metal layer of the test area structure 302, will not be grounded; the vias below the interconnecting metals such as the first PAD metal layer 305a1 and the second PAD metal layer 305b1 of the interconnecting layer are removed from the PAD area structure to ensure that the pad will not break down with the substrate.

[0041] In a second embodiment of the present invention, an N well is further added below the test structure to isolate the structure from the substrate.

[0042] Compared to existing test structures: When evaluating the high-voltage TDDB of the VxMx+1 test results on a platform, T63% was around 10s, indicating a lifetime fail, meaning the life test failed. The final slice results showed breakdown between the upper and lower layers.

[0043] In this embodiment of the invention, by establishing a short loop flow that skips the zeroth layer via and the zeroth layer metal (V0 / M0), the metal layer M1 is kept away from the substrate, preventing charge accumulation below the structure under test during testing and avoiding breakdown between the upper and lower layers. A T63% value of approximately 1000s is achieved, indicating a successful lifetime test.

[0044] Therefore, the embodiments of the present invention, through a structural design with the same effect, can avoid high voltage breakdown of the upper and lower layers, thereby ensuring accurate reliability assessment results.

[0045] In addition, the large-pitch metal interlayer dielectric layer test structure of this invention does not require the construction of an additional short loop, saving on production and testing resources and shortening the process development and improvement cycle.

[0046] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A test structure for a metal interlayer dielectric layer, characterized in that, include: Test area structure and PAD area structure; The test area structure has a first metal pattern structure and a second metal pattern structure, with a corresponding IMD layer to be tested spaced between the first metal pattern structure and the second metal pattern structure; no vias are formed in each via layer between the first metal pattern structure, the second metal pattern structure and the top surface of the semiconductor substrate, so that there is no conductive path between the first metal pattern structure and the semiconductor substrate and between the second metal pattern structure and the semiconductor substrate. The PAD area structure includes multiple first PAD metal layers and multiple second PAD metal layers; In the multilayer first PAD metal layer, there is an interconnect layer first PAD metal layer connected to the first metal pattern structure. The first PAD metal layers above the interconnect layer first PAD metal layer are connected together through vias and lead out the first electrode of the first metal pattern structure. Between the interconnect layer first PAD metal layer and the semiconductor substrate, at least one or more via layers do not form the vias, so that there is no conductive path between the first electrode and the semiconductor substrate. In the multilayer second PAD metal layer, there is a second PAD metal layer with interconnection layer connected to the second metal pattern structure. The second PAD metal layers above the interconnection layer are connected together through vias and lead out the second electrode of the second metal pattern structure. Between the interconnection layer and the semiconductor substrate, at least one or more via layers do not form the vias, so that there is no conductive path between the second electrode and the semiconductor substrate.

2. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: The test area structure includes an MxMx structure, where Mx represents the xth metal layer and x is an integer. In the MxMx structure, both the first metal pattern structure and the second metal pattern structure are patterns of the xth metal layer. On the top view, the first metal pattern structure and the second metal pattern structure form an interdigitated structure.

3. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: The test area structure includes a VxMx+1 structure, where Vx represents the xth via layer, Mx+1 represents the (x+1)th metal layer, and x is an integer. In the VxMx+1 structure, the first metal pattern structure includes the pattern of the xth metal layer, and the second metal pattern structure includes the (x+1)th metal layer. On the top view, the first metal pattern structure and the second metal pattern structure form an interdigitated structure. Multiple xth vias are formed on the top of each of the strip fingers of the first metal pattern structure.

4. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: The test area structure includes a MOM structure.

5. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: In the layout of the test area structure, a pseudo-via barrier layer is added to each of the via layers between the first metal pattern structure, the second metal pattern structure, and the top surface of the semiconductor substrate to prevent the via from being generated in OPC.

6. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: In the PAD region structure, the layout of the vias in each of the via layers between the first PAD metal layer of the interconnect layer and the semiconductor substrate is deleted to eliminate the vias; the layout of the vias in each of the via layers between the second PAD metal layer of the interconnect layer and the semiconductor substrate is deleted to eliminate the vias.

7. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: The semiconductor substrate is P-type doped.

8. The metal interlayer dielectric layer test structure as described in claim 7, characterized in that: An N-type well region is formed in at least the surface region of the semiconductor substrate directly below the PAD region structure.

9. The metal interlayer dielectric layer test structure as described in claim 1, characterized in that: The width of the IMD layer to be tested, which is the gap between the first metal pattern structure and the second metal pattern structure, is greater than the thickness of the interlayer film between two adjacent metal layers.

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