An integrated circuit chip intelligent detection and adaptive optimization method and system

Abstract

This invention relates to the field of integrated circuit manufacturing and testing technology, and particularly to an intelligent detection and adaptive optimization method and system for integrated circuit chips. The method includes: acquiring the chip under test, a chip testing socket, and a set of probes; performing rapid positioning, precise holding, detection image acquisition, voltage and current sampling, and integrated processing to obtain a first detection state; based on the first detection state and the detection record, generating a first multi-dimensional feature vector and a current dynamic resource evaluation matrix; then performing detection item dependency matching, reordering, working mode allocation, test signal allocation, test channel allocation, and detection item execution processing to generate a current dynamic detection record; subsequently performing associated anomaly judgment, anomaly chip marking, detection result sending, and detection result write-back processing to generate an updated detection record. This invention significantly improves the flexibility of the detection process and the accuracy of anomaly judgment, reducing the risk of misjudgment caused by equipment state fluctuations.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing and testing technology, and in particular to an intelligent detection and adaptive optimization method and system for integrated circuit chips. Background Technology

[0002] In the field of integrated circuit manufacturing and testing technology, existing solutions typically use a chip testing card holder, a set of probes, a tester, a voltage and current detection circuit, a sampling circuit, a detection image acquisition component, and a low-light signal detection component to form a testing station. The chip under test is then subjected to operations such as detection image acquisition, operating voltage detection, operating current detection, communication protocol testing, data conversion loop testing, normal operation status query, power consumption judgment, or low-light signal detection in sequence. This approach has limitations such as a fixed order of testing items, scattered testing records, and a broken link in the judgment of abnormal chips.

[0003] Existing methods often rely on preset test sequences and individual test results for judgment. Within the same chip testing station, the previous test result is difficult to directly participate in the selection and adjustment of the next test item.

[0004] In scenarios where abnormal chip judgment is achieved by matching the dependency relationship of detection items, reordering and associating them in the same working mode based on the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, it is easy for test channel calls to become disconnected from the current detection state and working mode switching to become disconnected from the current dynamic detection record, making it difficult to meet the requirement of stable implementation of abnormal chip judgment.

[0005] For the joint processing of the first multi-dimensional feature vector, the current dynamic resource evaluation matrix, the dependency relationship of the detection item, the current order of the detection item, the test channel record of the current working mode, and the current dynamic detection record, existing technologies generally lack a unified connection for the detection image, working voltage, working current, first voltage sample value, first current sample value, equipment status, real-time load, failure rate, detection record, and continuous working time of the equipment. It is difficult to form a consistent process of acquisition, matching, reordering, association processing, detection result sending and write-back update at the same chip detection station. This leads to difficulties in forming a unified judgment between communication protocol test failure, data conversion loop test failure, abnormal normal operation status, and mismatch between low light signal and working mode, which in turn affects the continuation of detection record in subsequent production lines, the connection of abnormal chip marking, and the update of the same batch detection process. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a method for intelligent detection and adaptive optimization of integrated circuit chips, comprising: S100: Acquire the chip under test, chip detection card holder and a set of probes, perform rapid positioning, precise holding, detection image acquisition, voltage and current sampling and integration processing to obtain the first detection state; Wherein, the chip under test is a chip object that enters the chip testing station and is ready to be connected to the testing process; the chip testing card holder is a fixed component that carries the chip under test and provides test channels, probe positions and interface access positions; the set of probes is a set of test contacts that make contact with the pins or interfaces of the chip under test. S200. Based on the first detection state, perform matching processing, and integrate device status with resource ID and evaluation index arrangement processing to generate a first multi-dimensional feature vector and the current dynamic resource evaluation matrix. S300. Based on the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, perform detection item dependency matching and reordering processing, and execute working mode allocation, test signal allocation, test channel allocation and detection item execution processing to generate the current dynamic detection record. S400. Based on the current dynamic detection record, perform associated anomaly judgment and anomaly chip marking, send detection results and write back detection results to generate updated detection records.

[0007] Furthermore, the process of rapid positioning, precise holding, detection image acquisition, and voltage and current sampling processing includes: The rapid positioning and precise holding process includes: placing the chip under test into the placement slot of the chip detection card holder; using a pressure rod, an adjustment plate, and a positioning plate to limit the position and hold the chip under test on the surface; and completing coarse and fine alignment according to the probe distribution position in the chip detection card holder, so that a group of probes enters a pressure contact state with the pins of the chip under test; and writing the position change, pressure state, probe contact state, and whether repositioning has occurred into the chip positioning contact record. The detection image acquisition and voltage and current sampling processing includes: based on the contact state in the chip positioning contact record, the camera acquires the detection image; the control circuit controls the voltage generation circuit to provide a test signal to the IO pin through the sampling circuit and acquire the first voltage sampling value and the first current sampling value; at the same time, the working voltage and working current are recorded; when there is a repositioning record or contact fluctuation record, the detection image acquisition is performed first and then the voltage and current sampling is performed; and the sudden change in the sampling result is compared with the contact state in the chip positioning contact record and then written into the first detection image sampling record.

[0008] Furthermore, the integration process includes: The integration process includes: matching and merging the detection images, working voltage, working current, first voltage sample value and first current sample value obtained by the same chip under test in the same chip detection card socket, the same pressure state and the same test channel; when there is a repositioning record, the record after the pressure bar is stably pressed down is selected as the valid record to form the first detection state.

[0009] Furthermore, the matching process includes: The matching process includes: detecting the image, operating voltage, operating current, first voltage sample value, and first current sample value; The matching process includes: the control circuit matching the detection image with the working voltage, working current, first voltage sample value and first current sample value one by one according to the same chip under test, the same chip detection card socket, the same test channel and the same contact state, forming an effective matching record, and arranging it in a fixed order as a first multi-dimensional feature vector.

[0010] Furthermore, the process of integrating device status and arranging resource IDs and evaluation metrics includes: The equipment status integration and resource ID and evaluation index arrangement processing includes: accessing the detection records of the test machine, voltage and current detection circuit, sampling circuit, PD control circuit, AUX control circuit, low-light detection lens and a set of probes from the detection record positions in the first multi-dimensional feature vector; integrating the equipment status, real-time load, failure rate and continuous working time of each detection device into a dynamic resource evaluation basic record; establishing resource IDs according to the detection resource type; and arranging the contents of the dynamic resource evaluation basic record into the current dynamic resource evaluation matrix according to the resource ID, wherein the equipment status, real-time load, failure rate, detection record and continuous working time of the same resource ID are arranged in the same direction.

[0011] Furthermore, the process of detecting dependency matching and reordering includes: The detection item dependency matching and reordering process includes: the control circuit reads the detection image position, working voltage position, working current position, first voltage sample value position, first current sample value position, and detection record position from the first multi-dimensional feature vector, and reads the device status, real-time load, failure rate, detection record, and continuous working duration of each resource ID in the current dynamic resource evaluation matrix. Based on the sequential calling relationship between detection items, the detection order of the current chip under test is generated in real time. Specifically, when the working voltage fluctuates while the working current is stable in the first multi-dimensional feature vector, the normal operation status query is prioritized. When the correspondence between the first voltage sample value and the first current sample value is abnormal, the correspondence between voltage and current is prioritized. When the failure rate of a certain test channel in the current dynamic resource evaluation matrix is ​​higher than that of other resource IDs in the same batch, the test channel is moved to the back, thereby generating the current detection item order.

[0012] Furthermore, the processes of work mode allocation, test signal allocation, test channel allocation, and test item execution processing include: The working mode, test signal and test channel allocation process includes: the control circuit determines the working mode, test signal and test channel corresponding to each test item according to the current test item sequence. The working mode includes running working mode, pre-charging working mode and test mode. The test channel includes voltage and current detection channel, communication protocol test channel, data conversion loop test channel and corresponding channel for low light signal detection. The execution process of the detection item includes: the test machine, control circuit, PD control circuit, AUX control circuit, voltage and current detection circuit, video interface conversion circuit and low light detection lens execute the corresponding detection items according to the current working mode test channel record, and merge the communication protocol test record, data conversion loop test record, normal operation status record, power consumption record, low light signal record, and the working mode record and test channel record corresponding to each detection item into the current dynamic detection record according to the execution order.

[0013] Furthermore, the process of identifying and handling association anomalies includes: The associated anomaly judgment processing includes: the control circuit and the judgment module read corresponding records from the current dynamic detection record according to the same chip under test, the same working mode, the same test channel and the same execution sequence window, and perform parallel comparison and correspondence. Among them, when the voltage and current correspondence anomaly and the normal operation state anomaly occur simultaneously in the same execution sequence window, they are written into the first associated anomaly item; when the communication protocol test fails and the data conversion loop test fails or the bit error rate is abnormal, they are written into the second associated anomaly item; when the low light signal does not match the current working mode, they are written into the third associated anomaly item, thereby forming an associated anomaly judgment record.

[0014] Furthermore, the process of anomaly chip marking, detection result transmission, and detection result write-back includes: The abnormal chip marking and detection result sending process includes: when the judgment module marks the chip under test as an abnormal chip in the same working mode of the associated abnormal judgment record, or when the associated abnormal items appear consecutively in the same execution sequence window and are accompanied by the same test channel abnormal record, the judgment module sends the chip number, chip detection card slot position, associated abnormal items, working mode record and test channel record to the host computer through the communication interface; The detection result write-back process includes: the control circuit locates the current dynamic detection record corresponding to the current chip under test based on the abnormal chip marking record, writes back the detection result, detection record, detection duration, working voltage, working current and power consumption to the same batch of detection record set, and synchronously updates the detection record, failure rate and continuous working duration of each resource ID in the current dynamic resource evaluation matrix to obtain the updated detection record.

[0015] Furthermore, an intelligent detection and adaptive optimization system for integrated circuit chips includes: a chip positioning contact record generation unit, a first detection state generation unit, a first multi-dimensional feature vector generation unit, a dynamic resource evaluation matrix generation unit, a detection item sequence generation unit, a working mode test channel record generation unit, and a dynamic detection record generation unit; the units are connected in sequence to implement the method described in any of the above-mentioned embodiments.

[0016] The key innovations of this invention include: (1) Obtain the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, perform detection item dependency matching and reordering processing to obtain the current detection item order, and based on the current detection item order, perform working mode, test signal and test channel allocation processing to obtain the current working mode test channel record. The detection image, working voltage, working current, first voltage sample value, first current sample value and detection record in the first multi-dimensional feature vector, together with the device status, real-time load, failure rate, detection record and device continuous working time in the current dynamic resource evaluation matrix, are used as the basis for generating the detection process.

[0017] (2) Obtain the current dynamic detection record, perform correlation processing on voltage and current correspondence abnormality, normal operation status abnormality, communication protocol test failure, data conversion loop test failure and micro-light signal and working mode mismatch, obtain the correlation abnormality judgment record, and match the multiple detection results in the current dynamic detection record according to the same working mode, test channel and execution order to form the correlation abnormality judgment link for abnormal chip mark.

[0018] (3) Based on the abnormal chip marking record, perform write-back processing of detection results, detection record, detection duration, working voltage, working current and power consumption to obtain the updated detection record, and connect the updated detection record with the detection record, the current dynamic resource evaluation matrix and the subsequent chip detection process to form a continuous update link of the chip positioning contact record, the first detection state, the first multi-dimensional feature vector, the current detection item order, the current dynamic detection record and the associated abnormal judgment record.

[0019] The following are its main beneficial effects: (1) In view of the problem that the order of the test items is fixed in the existing scheme and the previous test result is difficult to directly participate in the selection of the next test item, the present invention uses the first multi-dimensional feature vector and the current dynamic resource evaluation matrix to jointly participate in the test item dependency matching and reordering process, so that the current test item order corresponds to the current chip under test state and the current chip test station state. The working mode, test signal and test channel are adjusted in linkage with the current test item order, and the test process forms a continuous connection within the same chip test station.

[0020] (2) In view of the problem that the detection image, working voltage, working current, first voltage sample value, first current sample value and equipment status, real-time load, failure rate, detection record and continuous working time of the equipment are processed separately in the existing solution, the present invention enables the detection process to read the current chip status and the current detection resource status at the same time through the joint input link of the first multi-dimensional feature vector and the current dynamic resource evaluation matrix. The test machine, test channel, sampling circuit, voltage and current detection circuit, low light detection lens, configuration channel control circuit, auxiliary channel control circuit and a set of probes are called in the same processing link.

[0021] (3) In view of the problem that the judgment of abnormal chips in the existing schemes depends on a single detection result and there is no unified correspondence between different detection results, the present invention forms a correlation processing of the current dynamic detection record to form a correlation between voltage and current, abnormal normal operation status, communication protocol test failure, data conversion loop test failure and mismatch between light signal and working mode, so that the judgment of abnormal chips is based on the correlation of abnormal judgment records under the same working mode, test channel and execution order, and the abnormal chip marking and detection result sending have a unified judgment basis.

[0022] (4) In view of the problem that communication protocol testing, data conversion loop testing, normal operation status query, power consumption judgment and low light signal detection are separated in the existing solution, the present invention organizes the execution order of each detection item through the current working mode test channel record, so that the communication protocol testing, the data conversion loop testing, the normal operation status query, the power consumption judgment and the low light signal detection form a unified current dynamic detection record, and the calling relationship between the detection results remains consistent.

[0023] (5) In view of the problem that the detection results in the existing scheme are stuck at a single output and the subsequent chips under test are difficult to inherit the previous detection records, the present invention performs write-back processing on the detection results, detection records, detection duration, working voltage, working current and power consumption through the abnormal chip marking record to obtain the updated detection record, so that the subsequent chips under test have the previous detection content when calling the detection record and the current dynamic resource evaluation matrix, and the detection process is continuously updated in the same batch of detection links. Attached Figure Description

[0024] Figure 1 A flowchart illustrating an intelligent detection and adaptive optimization method for integrated circuit chips provided in this application embodiment; Figure 2 This is a structural block diagram of an intelligent detection and adaptive optimization system for integrated circuit chips provided in an embodiment of this application. Detailed Implementation

[0025] Example 1: Refer to Figure 1 This is a flowchart illustrating an intelligent detection and adaptive optimization method for integrated circuit chips provided in an embodiment of the present invention. The process may include at least steps S100-S400: S100: Acquire the chip under test, chip detection card holder and a set of probes, perform rapid positioning, precise holding, detection image acquisition, voltage and current sampling and integration processing to obtain the first detection state; S200. Based on the first detection state, perform matching processing, and integrate device status with resource ID and evaluation index arrangement processing to generate a first multi-dimensional feature vector and the current dynamic resource evaluation matrix. S300. Based on the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, perform detection item dependency matching and reordering processing, and execute working mode allocation, test signal allocation, test channel allocation and detection item execution processing to generate the current dynamic detection record. S400. Based on the current dynamic detection record, perform associated anomaly judgment and anomaly chip marking, send detection results and write back detection results to generate updated detection records.

[0026] Step S100 includes at least steps S110-S130: S110: Acquire the chip under test, the chip detection card holder, and a set of probes; perform rapid positioning and precise holding processing to obtain the chip positioning contact record.

[0027] Specifically, the chip under test is a chip object that enters the chip testing station and is ready to be connected to the testing process. The chip testing card holder is a fixed component that carries the chip under test and provides test channels, probe positions and interface access positions. The set of probes is a set of test contacts that make contact with the pins or interfaces of the chip under test.

[0028] In this step, the chip under test is first placed into the placement slot or testing box corresponding to the chip testing card holder. Then, the pressure rod, reset plate, adjustment plate, positioning plate, support column, and spring assembly limit the position and hold the surface of the chip under test. The rapid positioning refers to the adjustment plate and positioning plate aligning the outer edge of the chip under test along the position corresponding to the guide hole or sleeve. The precise holding refers to the pressure rod, driven by the cylinder, lifting seat, fixing plate, or pressure plate, pressing down on the upper surface of the chip under test and keeping the chip under test in a stable posture within the chip testing card holder.

[0029] In practice, the set of probes does not make direct, disordered contact. Instead, coarse alignment is first achieved based on the probe distribution within the chip detection socket, followed by fine alignment through a small-stroke movement of the adjustment plate. Once the pin area of ​​the chip under test aligns with the contact position of the set of probes, the pressure rod continues to press down, bringing the probes into a pressure contact state with the pins or interface. If skewness, insufficient springback, or contact position shift occurs during the pressing process, the reset plate and spring assembly first release part of the pressure, then the adjustment plate pushes the chip under test again, followed by another press.

[0030] During this process, the position changes, pressure states, probe contact states, and reset states are all written into the chip positioning contact record. The chip positioning contact record is the output field name for this step, and its content includes at least the placement state of the chip under test in the chip testing card holder, the pressure bar pressure state, the contact state of a set of probes with pins or interfaces, and a detection record of whether repositioning has occurred.

[0031] Furthermore, in a feasible engineering embodiment, after the chip under test is placed into the chip detection card holder, the fixing plate is driven by a cylinder to move downward. The pressure rod first presses down on the upper surface of the chip under test, and the adjustment plate then pushes against the side of the chip under test along the corresponding direction of the guide hole. The support column supports the bottom of the chip under test. After a set of probes and pins enter the pressing contact state, the contact process is written into the chip positioning contact record. The chip positioning contact record is called as input by S120 in subsequent steps for detection image acquisition and voltage and current sampling processing. In addition, the contact state in the chip positioning contact record also provides a preliminary detection record for the detection item dependency matching in the subsequent S300.

[0032] The chip detection card holder, pressure bar, placement slot, cylinder, fixing plate, adjustment plate and probe arrangement described above are all connected to the mature workstation structure in existing chip detection equipment. However, in this invention, these components jointly undertake the functions of establishing the first layer of input and generating contact records, rather than the final detection and judgment function.

[0033] S120. Based on the chip positioning contact record, perform detection image acquisition and voltage and current sampling processing to obtain the first detection image sampling record.

[0034] Specifically, the input source for this step is the aforementioned chip positioning contact record. The probe contact state, holding state, and repositioning record in the chip positioning contact record are used to determine whether the detection image acquisition path and the voltage and current sampling path are simultaneously activated. The detection image acquisition refers to imaging the surface of the chip under test using a camera, or imaging the surface under test using a microscope, reflection module, image conversion module, and image output module. The voltage and current sampling refers to the control circuit controlling the voltage generation circuit to provide test signals to the input / output (IO) pins through the sampling circuit, and sampling the electrical signals in the output or input state of the chip under test to obtain the first voltage sampling value and the first current sampling value.

[0035] During implementation, it is first determined whether there is a poor contact record in the chip positioning contact record. When there is no poor contact record, the camera and sampling circuit work synchronously. The camera performs a surface image of the outer surface of the chip under test, and the sampling circuit samples the electrical signals output by the IO pins of the chip under test to form a batch of records of detection image, working voltage, working current, first voltage sample value and first current sample value. When there is a repositioning record or probe contact fluctuation record in the chip positioning contact record, a detection image is acquired first, and then voltage and current sampling is performed, and the two acquisitions are mapped to the same chip under test number.

[0036] Furthermore, the acquisition of the detection image is not just ordinary shooting, but corresponding imaging is performed in combination with the fixed position in the chip detection card holder; when the camera is fixed to the position of the fixing plate or microscope, the overall detection image of the outer surface of the chip to be tested is acquired first, and then the pin area or interface area is acquired locally; if the image output module displays that the outline of the surface to be tested is not clear, the focus of the objective lens is adjusted by the focusing knob and the detection image is reacquired.

[0037] The voltage and current sampling is performed by the control circuit according to the test channel sequence in the chip detection socket. The voltage generation circuit outputs a test signal, and the sampling circuit acquires the first voltage sample value and the first current sample value, while recording the working voltage and working current. If a sudden change occurs in the sampling result, the control circuit calls the contact state in the chip positioning contact record to determine whether the sudden change is due to a change in the contact state or a change in the output state of the chip under test itself, and writes the determination result into the first detection image sampling record.

[0038] In one engineering embodiment, after the chip under test completes rapid positioning and precise holding, the camera first acquires a detection image of the chip surface, and then the control circuit provides a test signal to the IO pin. The sampling circuit records the first voltage sampling value and the first current sampling value. If the working voltage is stable but the first current sampling value fluctuates in this round of sampling, the control circuit immediately reads the pressure bar pressing state and probe contact state in the chip positioning contact record. If there is fluctuation in the corresponding state, it is marked as a contact fluctuation sampling record in the first detection image sampling record for integration processing by S130.

[0039] The first detection image sampling record is the output field name of this step. Its content includes at least the detection image, working voltage, working current, first voltage sampling value, first current sampling value, and contact state reference information corresponding to the chip positioning contact record. The first detection image sampling record is called as input by S130 in subsequent steps for the integrated processing of detection image, working voltage, working current, first voltage sampling value, and first current sampling value. Furthermore, the sampling record in the first detection image sampling record also provides direct input for the detection image and sampling value matching processing in the subsequent S210.

[0040] S130. Based on the first detection image sampling record, perform integrated processing of the detection image, working voltage, working current, first voltage sampling value and first current sampling value to obtain the first detection state.

[0041] Specifically, the input source for this step is the aforementioned first detection image sampling record. The detection image, operating voltage, operating current, first voltage sampling value, first current sampling value, and contact state reference information in the first detection image sampling record are uniformly read into the same integrated processing link.

[0042] The integration process refers to matching, filtering, and merging the image records and sampling records obtained by the same chip under test in the same chip test socket, under the same pressure state, and in the same test channel to form a complete status record that can be directly called for subsequent matching processing.

[0043] Furthermore, the integration process first reads the detection image according to the chip number under test, then reads the working voltage, working current, first voltage sample value, and first current sample value corresponding to the chip number under test, and then determines whether these records are in the same contact state; when they are in the same contact state, they are directly integrated into a complete state record; when there are repositioning records, repeated sampling records, or contact fluctuation sampling records for the same chip under test, the detection image and sampling record after the pressure bar is stably pressed down are read first, and then written as the current valid record into the first detection state.

[0044] Understandably, the first detection state is not the final judgment of the detection result, but rather a unified input carrier for the chip under test before it enters the subsequent multi-dimensional feature vector generation. What it contains, what it is composed of, and how it will be called in the future are all fixed in this step.

[0045] Specifically, the first detection state includes at least three parts: the first part is the detection image content, which is used to characterize the imaging situation of the outer surface or the surface under test of the chip; the second part is the working voltage and working current content, which is used to characterize the power supply and sampling status under the current test channel; and the third part is the first voltage sampling value and the first current sampling value content, which is used to characterize the basic record of the correspondence between the voltage and current of the IO pin under the action of the test signal.

[0046] If multiple sets of local detection images exist simultaneously in the first detection image sampling record, the pin area or interface area is first mapped to the probe contact position in the chip detection card socket, and then the first detection state is written; if there are two or more sets of first voltage sampling values ​​or first current sampling values, the current valid record is selected in the order of the same down-voltage state, the same test channel, and the most recent stable sampling.

[0047] Furthermore, in a practical scenario embodiment, after the chip under test completes one surface detection image acquisition and one voltage and current sampling in the chip detection socket, the system will list the detection image and the working voltage, working current, first voltage sampling value and first current sampling value in parallel according to the chip number; if there are two rounds of sampling under the same number, the record of the second round with stable contact state will be read, the priority of the fluctuation sampling of the previous round in the integration will be deleted, and the detection image and sampling result will be merged and written into the first detection state.

[0048] The first detection state is the output field name of this step. This field is directly input as "first detection state" in subsequent steps S210 and is used for matching processing of detection image, working voltage, working current, first voltage sample value and first current sample value. At the same time, the detection record in the first detection state continues to be integrated with the device status, real-time load, failure rate and device continuous working time in subsequent S220, and participates in the detection item dependency matching in S310.

[0049] Therefore, the chip positioning contact record formed in S110 is converted into the first detection image sampling record in S120, and then converged into the first detection state through this step, completing the continuous transmission from workstation contact, image sampling to unified state input.

[0050] In summary, this step integrates camera imaging and sampling circuit recording into a single integrated link, unifying repositioning recording, contact fluctuation recording, and effective sampling recording into the first detection state. The existing problem of separating image observation and voltage / current sampling is resolved here by unifying them into a single input state. This first detection state is not a single detection result, but rather a prerequisite input for matching the dependencies of subsequent detection items. Subsequent steps no longer read scattered records from scratch, but directly call upon the unified state record.

[0051] Step S200 includes at least steps S210-S230: S210. Obtain the first detection state and detection record, and perform matching processing on the detection image, working voltage, working current, first voltage sample value and first current sample value to obtain the first multi-dimensional feature vector.

[0052] Specifically, the input source for this step is the first detection state output from the aforementioned steps and the detection record retained along with the first detection state. The first detection state includes the detection image, operating voltage, operating current, first voltage sample value, and first current sample value. The detection record includes the chip detection card slot position, test channel position, probe contact state, sampling timing, and repositioning record.

[0053] The matching process is not a simple splicing, but rather the control circuit matches the detection image, working voltage, working current, first voltage sample value and first current sample value one by one according to the same chip under test, the same chip detection card socket, the same test channel and the same contact state.

[0054] First, read the detection image in the first detection state to determine the test surface area, pin area or interface area corresponding to the detection image, and then read the working voltage and working current records corresponding to the area; then read the first voltage sampling value and the first current sampling value under the corresponding timing, and determine whether the set of sampling values ​​is consistent with the probe contact state when the detection image was acquired.

[0055] If they match, the set of detection images, operating voltage, operating current, first voltage sample value, and first current sample value are taken as a set of valid matching records; if they do not match, the repositioning record and contact state record in the detection record are called up to replace and match the next round of sampling of the same chip under test until a valid record corresponding to the current contact state is obtained.

[0056] Furthermore, the first multi-dimensional feature vector is the result of arranging the above-mentioned valid matching records in a fixed order, and the fixed order includes at least the detection image position, the working voltage position, the working current position, the first voltage sample value position, the first current sample value position, and the detection record position.

[0057] Understandably, in one engineering embodiment, when the same chip under test generates two sets of first voltage sampling values ​​and first current sampling values, the control circuit first compares the operating voltage and operating current corresponding to the two sets of sampling values, and then, in conjunction with the probe contact state in the detection record, selects a set of sampling values ​​that are consistent with the stable contact state for arrangement processing, and writes the other set of sampling values ​​as a reserved detection record into the detection record of the same chip under test.

[0058] After the above matching process, the output field name is the first multi-dimensional feature vector. The first multi-dimensional feature vector is called as a direct input in the subsequent steps by S220 for the integrated processing of device status, real-time load, failure rate, detection records and device continuous working time. At the same time, the first multi-dimensional feature vector will also participate in the detection item dependency matching and reordering process together with the current dynamic resource evaluation matrix in S310.

[0059] S220. Based on the first multi-dimensional feature vector, integrate the device status, real-time load, failure rate, detection records and device continuous working time to obtain the basic record of dynamic resource evaluation.

[0060] Specifically, the input source for this step is the first multi-dimensional feature vector. The detection image position, working voltage position, working current position, first voltage sampling value position, first current sampling value position, and detection record position in the first multi-dimensional feature vector are used to indicate the detection resources that the chip under test has occupied or is about to occupy.

[0061] The equipment status refers to the current operating status of the tester, voltage and current detection circuit, sampling circuit, PD control circuit, AUX control circuit, low-light detection lens, and a set of probes corresponding to the chip under test in the chip testing station; the real-time load refers to the occupancy status of the detection channels undertaken by the aforementioned testing equipment at the current testing moment; the failure rate refers to the proportion of records of abnormal interruption, sampling fluctuation, test failure, or repeated reset of the aforementioned testing equipment in the continuous testing records; the continuous working time of the equipment refers to the cumulative continuous working record time of the corresponding testing equipment since the last reset, switch, or shutdown.

[0062] In this step, the control circuit first extracts the detection record position from the first multi-dimensional feature vector, and then accesses the detection records currently stored in the test machine, sampling circuit, voltage and current detection circuit and chip detection card slot according to the position; subsequently, the detection record is integrated item by item with the equipment status, real-time load, failure rate and continuous working time of each detection device.

[0063] If a certain testing device has records of repeated resampling, repeated repositioning, or fluctuations in the same test channel, the failure rate of that testing device will be updated in the current integrated result. If a certain testing device continuously undertakes testing items for multiple chips under test, the real-time load and continuous working time of that testing device will be written into the current integrated result.

[0064] Furthermore, the dynamic resource assessment basic record is not an abstract record, but a basic arrangement record of each detection resource in the current chip detection station before the current chip under test enters the next detection item. Its content includes at least the equipment status corresponding to the detection equipment, the real-time load corresponding to the test channel, the detection record corresponding to a set of probes, the failure rate corresponding to the test machine, and the continuous working time of the equipment corresponding to the voltage and current detection circuit, PD control circuit, AUX control circuit and low light detection lens.

[0065] Understandably, in one operable embodiment, when the first multi-dimensional feature vector shows that the chip under test has two resampling records, the control circuit reads the detection records of the corresponding sampling circuit and test channel, increases the failure rate record of the sampling circuit, and reads the real-time load and continuous working time of the test machine, and writes the result into the dynamic resource evaluation basic record; if the low-light detection lens has not been called, its device status and continuous working time are still written according to the current idle record.

[0066] After the integration process, the output field name is Dynamic Resource Evaluation Basic Record. The Dynamic Resource Evaluation Basic Record is directly called by S230 in subsequent steps for resource ID and evaluation index arrangement processing. The Dynamic Resource Evaluation Basic Record also provides a resource-side input basis for the subsequent detection item order matching and dynamic adjustment in S300.

[0067] S230. Based on the aforementioned dynamic resource evaluation basic records, perform resource ID and evaluation index arrangement processing to obtain the current dynamic resource evaluation matrix.

[0068] Specifically, the input source for this step is the dynamic resource assessment basic record. The equipment status, real-time load, failure rate, detection record, and continuous working time of the equipment in the dynamic resource assessment basic record correspond to the test machine, voltage and current detection circuit, sampling circuit, chip detection card socket, a set of probes, PD control circuit, AUX control circuit, low light detection lens, and test channel in the current chip detection station, respectively.

[0069] The resource ID refers to the record location that identifies each of the above-mentioned detection resources one by one, and the evaluation index refers to the device status, real-time load, failure rate, detection records, and continuous working time of the device corresponding to each resource ID.

[0070] In this step, the control circuit first establishes resource IDs according to the type of detected resource, and then arranges the contents of the dynamic resource evaluation basic record into the evaluation index positions according to the resource IDs, forming a row and column corresponding arrangement result. Among them, the device status, real-time load, failure rate, detection record and continuous working time of the device under the same resource ID are arranged in the same direction, and the different resource IDs are arranged in the order of chip detection card socket, test channel, test machine, voltage and current detection circuit, sampling circuit, PD control circuit, AUX control circuit and low light detection lens.

[0071] Furthermore, the arrangement process also includes trigger condition judgment: when the failure rate corresponding to a certain resource ID is higher than that of other resource IDs in the same batch of detection records, the position of that resource ID in the current dynamic resource evaluation matrix is ​​still retained, but the current failure rate record is added to its evaluation index position; when the continuous working time of the device corresponding to a certain resource ID is close to the preset constraint, the continuous working time record of the device is retained in its evaluation index position for subsequent detection item dependency matching and calling. If a certain resource ID is in an idle state before the current chip under test is detected, its device status is written to the idle record, the real-time load is written to the current idle record, and the detection record is written to the most recent detection retention record.

[0072] Understandably, in one engineering embodiment, the control circuit can first assign a resource ID to the chip detection card socket, assign a resource ID to the test channel, and then assign resource IDs to the test machine, voltage and current detection circuit, sampling circuit, PD control circuit, AUX control circuit and low light detection lens respectively. Then, the corresponding device status, real-time load, failure rate, detection record and continuous working time of the device are filled into the corresponding positions to finally form the current dynamic resource evaluation matrix.

[0073] The current dynamic resource evaluation matrix is ​​the output field name of this step. In subsequent steps, this field is directly input by S310 as the "current dynamic resource evaluation matrix" and used to perform detection item dependency matching and reordering processing together with the first multi-dimensional feature vector. Furthermore, the current dynamic resource evaluation matrix will be updated after S430 completes the write-back of the detection results, forming the basic matrix for continued use by the same batch of chips under test.

[0074] In summary, this step consolidates the device status and test records scattered across the test machine, sampling circuit, chip testing socket, and test channels into a current dynamic resource evaluation matrix. This allows subsequent test item generation to no longer rely solely on the sampling results of the chip under test, but simultaneously reads the current status of the testing resources within the workstation. Compared to existing fixed testing procedures, subsequent steps, when calling the current dynamic resource evaluation matrix, can directly identify which test channel, which testing device, which low-light detection lens, or which group of probes is under high real-time load, high failure rate, or long continuous equipment operation time, thereby changing the generation path of the test item sequence.

[0075] Step S300 includes at least steps S310-S330: S310. Obtain the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, perform dependency matching and reordering of detection items, and obtain the current order of detection items.

[0076] Specifically, the input sources for this step are the first multi-dimensional feature vector output from the aforementioned steps and the current dynamic resource evaluation matrix. The first multi-dimensional feature vector is used to characterize the combined state of the detection image, operating voltage, operating current, first voltage sample value, first current sample value, and detection record of the chip under test in the same chip testing socket. The current dynamic resource evaluation matrix is ​​used to characterize the equipment status, real-time load, failure rate, detection record, and continuous working time of the test machine, voltage and current detection circuit, sampling circuit, test channel, PD control circuit, AUX control circuit, low-light detection lens, and a set of probes in the current chip testing station.

[0077] The dependency relationship of the detection items refers to the sequential calling relationship between each detection item. Specifically, it includes the correspondence between the detection image judgment and the voltage and current correspondence judgment, the correspondence between the working voltage and working current judgment and the normal operation status query, the correspondence between the communication protocol test and the data conversion loop test, and the calling relationship between the current detection result and the low light signal detection.

[0078] The reordering refers to the control circuit not executing all detection items according to a fixed procedure, but first reading the detection image position and sample value position in the first multi-dimensional feature vector, and then combining the resource ID and evaluation index in the current dynamic resource evaluation matrix to determine the detection items that the chip under test should execute first.

[0079] Furthermore, the control circuit first determines whether the operating voltage and operating current in the first multi-dimensional feature vector are in a stable record; when the operating voltage fluctuates but the operating current remains stable, the normal operation status query and power consumption judgment are prioritized; when there is an abnormal record in the correspondence between the first voltage sample value and the first current sample value, the voltage and current correspondence judgment is prioritized, and the ADC circuit reference calibration, digital IO port scan chain test or memory BIST test are retained as subsequent extended detection items in the same rearranged link; when there is a contamination record on the test surface corresponding to the detection image or a repositioning record in the detection record, the detection record corresponding to the chip detection card and a set of probes is called first, and then it is decided whether to postpone the communication protocol test, data conversion loop test or low light signal detection.

[0080] Understandably, the minimum set in this step is the first multi-dimensional feature vector, the current dynamic resource evaluation matrix, the detection item dependency relationship, and the reordering. The aforementioned contents directly determine the detection process of the current chip under test. The ADC circuit benchmark calibration, digital IO port scan chain test, and memory BIST test are extended detection items that can be accessed through the same reordered link. They are loaded into the current order when the first multi-dimensional feature vector shows an abnormal record corresponding to the internal digital circuit.

[0081] In an operational engineering embodiment, when an abnormal record is found in the pin area of ​​the detection image of a chip under test, and the first voltage sampling value and the first current sampling value corresponding to the same chip under test show a sudden change, the control circuit first compares the failure rate of the test channel and the sampling circuit in the current dynamic resource evaluation matrix. If the failure rate is low, the correspondence between voltage and current is ranked first, the normal operation status query is ranked second, the communication protocol test is ranked third, and the low-light signal detection is reserved for the subsequent order. If the failure rate is high, the current test channel is moved to the back, and the test channel corresponding to the resource ID with the lower failure rate is moved to the front.

[0082] Through the above-mentioned detection item dependency matching and reordering process, the output product obtained is the current detection item order. The current detection item order is sent as the output field name of this step to the "current detection item order" in the subsequent S320 for invocation. Furthermore, the current detection item order also directly corresponds to the detection item execution scope in the subsequent S330.

[0083] S320. Based on the current detection item order, perform working mode, test signal and test channel allocation processing to obtain the current working mode test channel record.

[0084] Specifically, the input source for this step is the current detection item sequence, which already gives the sequential relationship of the detection items of the chip under test. Based on this sequential relationship, this step further determines which test channel undertakes each detection item, in what working mode it is executed, and which test signal is called.

[0085] The operating modes include a running operating mode, a pre-charge operating mode, and a test mode. The test signals include a first test signal and a second test signal. The test channels include a voltage and current detection channel connected to the chip detection card socket, a communication protocol test channel, a data conversion loop test channel, and a corresponding channel for low-light signal detection.

[0086] Specifically, the control circuit first reads the first sequential detection item of the current detection item order. If the detection item is a normal operation status query or power consumption judgment, the digital adjustable power supply circuit is called to provide the working voltage to the chip under test and the chip under test is put into test mode. At the same time, the test channel corresponding to the voltage and current detection circuit is designated as the current channel. If the detection item is a communication protocol test, the PD control circuit and AUX control circuit are respectively connected to the CC channel and AUX channel and the corresponding test signal is allocated. If the detection item is a data conversion loop test, the video interface conversion circuit is called to connect to the current test channel to form a data conversion loop. If the detection item is a low-light signal detection, the device status and continuous working time of the low-light detection lens in the current dynamic resource evaluation matrix are first judged. If the calling conditions are met, the chip under test is switched to the running working mode or the pre-charging working mode and the first test signal or the second test signal is allocated.

[0087] Furthermore, the allocation process is not a one-time fixed allocation, but rather unfolds sequentially according to the current detection item.

[0088] After each detection item is assigned, the control circuit reads whether the subsequent sequential detection item shares the same test channel as the current sequential detection item. If they share, the current test channel is retained and only the test signal is switched. If they do not share, the current test channel is released, the test channel corresponding to the next resource ID is called, and a channel switching record is written to the test channel record of the current working mode.

[0089] The content recorded in the current working mode test channel includes at least the current detection item name, the corresponding working mode, the corresponding test signal, the corresponding test channel, and the corresponding resource ID.

[0090] Furthermore, in a practical scenario embodiment, when the current detection items are in the following order: voltage and current correspondence determination, normal operation status query, communication protocol test, and low-light signal detection, the control circuit first allocates a test mode and voltage and current detection channel for voltage and current correspondence determination, then retains the test channel and adjusts the operating voltage for normal operation status query, then switches to the CC channel and AUX channel when entering the communication protocol test, and finally releases the communication protocol test channel and calls the corresponding channel of the low-light detection lens when entering the low-light signal detection, while making a selection between the operating mode and the pre-charging mode based on the aforementioned detection results.

[0091] After processing the working mode, test signal, and test channel allocation, the output product is the current working mode test channel record. The current working mode test channel record is sent to the "current working mode test channel record" in the subsequent S330 as the output field name of this step. The working mode and test channel information in this record also provide the detection source correspondence for the associated anomaly judgment in the subsequent S410.

[0092] S330. Based on the current working mode test channel record, perform communication protocol testing, data conversion loop testing, normal operation status query, power consumption judgment or low light signal detection processing to obtain the current dynamic detection record.

[0093] Specifically, the input source for this step is the current working mode test channel record. The current working mode test channel record provides the working mode, test signal, test channel, and resource ID corresponding to each sequential test item. This step is performed by the test machine, control circuit, PD control circuit, AUX control circuit, voltage and current detection circuit, video interface adapter circuit, and low-light detection lens in the recorded order to execute the corresponding test items.

[0094] The communication protocol test refers to detecting the physical performance and communication protocol process of the chip under test after establishing a connection between the CC channel and the AUX channel, and outputting a pass or fail record; the data conversion loop test refers to detecting the video data conversion loop of the chip under test after the video interface adapter circuit is connected, and outputting a bit error rate record; the normal operation status query refers to the control circuit querying whether the chip under test is in a normal operation state after the digitally adjustable power supply circuit provides the working voltage; the power consumption judgment refers to the power consumption detection circuit collecting power consumption sampling values ​​and generating corresponding power consumption records; the low-light signal detection refers to the low-light signal of the chip under test being detected from the back of the transparent stage by a low-light detection lens in the operating mode or pre-charge mode, and recording the position of the low-light signal and the corresponding state of the low-light signal with the current operating mode.

[0095] Furthermore, the execution order in this step is strictly constrained by the current working mode test channel record.

[0096] If the first test item in the record is a communication protocol test, the tester first calls the PD control circuit and AUX control circuit to establish a communication protocol test path and writes the test result into the current dynamic test record. If the subsequent test item is a data conversion loop test, the control circuit calls the video interface conversion circuit and reads the bit error rate record. If the subsequent test item is a normal operation status query and power consumption judgment, the digital adjustable power supply circuit maintains the working voltage output, and the voltage and current detection circuit and power consumption detection circuit write the normal operation status record and power consumption record in sequence. If the subsequent test item is a low-light signal detection, the chip under test is placed face up on the transparent stage, and the low-light detection lens is facing the back of the transparent stage. The control circuit transmits the corresponding test signal to the chip under test, so that the chip under test enters the operating mode or pre-charge operating mode and then collects the low-light signal.

[0097] Understandably, the current dynamic detection record is not the result of a single detection item, but a sequential detection record formed after the current chip under test is executed continuously in the current detection item sequence.

[0098] This record includes at least communication protocol test records, data conversion loop test records, normal operation status records, power consumption records, low-light signal records, and corresponding operating mode and test channel records for each test item. If a test channel experiences an interruption, resource ID switch, or operating mode change during execution, the control circuit will immediately write this change into the current dynamic detection record, enabling subsequent anomaly judgments to accurately trace the source of the anomaly.

[0099] In a complete engineering embodiment, the current working mode test channel record first specifies the voltage and current detection channel in the test mode to perform normal operation status query and power consumption judgment, then specifies the CC channel and AUX channel to perform communication protocol test, then specifies the video interface conversion circuit to perform data conversion loop test, and finally calls the low light detection lens in the pre-charge working mode to perform low light signal detection; after each execution is completed, the test machine, control circuit and detection module merge their respective results into the current dynamic detection record according to the execution order.

[0100] The current dynamic detection record is used as the output field name for this step and is directly input and called by the "current dynamic detection record" in the subsequent S410. At the same time, the power consumption record, normal operation status record and low light signal record in it also correspond to the detection result write-back field in the subsequent S430.

[0101] Summary of the technical effects of this step: This step changes the execution of multiple test items in a fixed test platform to the order driven by the test channel record in the current working mode. Communication protocol testing, data conversion loop testing, normal operation status query, power consumption judgment, and low-light signal detection of the same chip under test are converged into the same dynamic record. Compared with the existing method of executing test items separately and judging them separately, the current dynamic test record output by this step already has the sequence relationship, working mode relationship, and test channel relationship required for subsequent correlation anomaly judgment. Subsequent steps can directly complete the mismatch judgment within the same record.

[0102] In one specific embodiment, the input sources for this step are the first multi-dimensional feature vector output from the preceding steps and the current dynamic resource evaluation matrix. The first multi-dimensional feature vector characterizes the combined state of the detection image, operating voltage, operating current, first voltage sample value, first current sample value, and detection record of the chip under test in the same chip testing socket. The current dynamic resource evaluation matrix characterizes the equipment status, real-time load, failure rate, detection record, and continuous operating time of the testing machine, voltage and current detection circuit, sampling circuit, test channel, PD control circuit, AUX control circuit, low-light detection lens, and a set of probes within the current chip testing station. The control circuit first performs abnormal feature extraction and quantization on the first multi-dimensional feature vector. It reads the image abnormality confidence from the detection image location, reads the voltage fluctuation amplitude and current stability flag from the operating voltage location and operating current location respectively, extracts the sampling deviation degree from the first voltage sample value location and the first current sample value location, and extracts the number of repositioning attempts and contact fluctuation counts from the detection record location. Meanwhile, the control circuit reads the device status, real-time load, failure rate and continuous working time of the device item by item from the current dynamic resource evaluation matrix according to the resource ID. The device status is discretized into three levels: idle, occupied and awaiting maintenance. The real-time load is normalized to the number of currently accepted detection channels. The failure rate is given as the ratio of the number of historical detection failures to the total number of detections. The continuous working time of the device is recorded in minutes.

[0103] To unify the aforementioned two-sided information into quantitative indicators that can be used for ranking decisions, the control circuit constructs an anomaly feature score vector and a resource constraint penalty vector, and generates a basic score for the priority of detection items through weighted fusion.

[0104] Formula ① is used to map the multi-source anomaly representation in the first multi-dimensional feature vector to the anomaly feature score vector of a single chip under test at the current time:

[0105] Variable and symbol definition: : Abnormal feature score scalar, the larger the value, the more significant the abnormal signs of the chip under test; : Preset weighting factors, all of which are positive real numbers, satisfying It is read from the weight configuration table in the storage module; Image anomaly confidence score, value range The detected image position is extracted from the first multi-dimensional feature vector and normalized by the image output module after detecting the surface visual feature edges. Voltage fluctuation amplitude, a non-negative real number, extracted from the working voltage position in the first multi-dimensional feature vector; Current stability indicator, value or The operating current position is extracted from the first multi-dimensional feature vector. When the deviation between adjacent sampling points is less than a preset threshold, the position is selected. ; Sampling deviation degree, value range The positions of the first voltage sample value and the first current sample value are extracted from the first multi-dimensional feature vector, and the result is the normalized result of the absolute value of the deviation between the sampling ratio and the standard operating point ratio. : Number of repositioning attempts, a non-negative integer, extracted from the detection record positions in the first multi-dimensional feature vector; Contact fluctuation count, a non-negative integer, extracted from the detection record position in the first multi-dimensional feature vector.

[0106] Simple numerical example: Suppose the image anomaly confidence level of a certain chip under test. Voltage fluctuation amplitude Current stability indicator Sampling deviation Number of repositionings Contact fluctuation count Next. Weighting , , , The calculation process is as follows: ; multiplied by have to ; ; Summing the four terms yields... This score will be used as a quantification of the chip-side anomaly intensity in subsequent rankings.

[0107] The anomaly feature score calculated by formula ① It only reflects the detection status of the chip under test itself, but another key constraint that determines the order of detection items comes from the resource-side status of the current chip detection station.

[0108] To this end, the control circuit further reads the status indicators of each detected resource according to the resource ID from the current dynamic resource evaluation matrix, constructs a resource constraint penalty vector, and converts the failure rate and continuous operating time of the equipment into a penalty factor for each candidate detection item through formula ②: ;

[0109] Variable and symbol definition: : Test channel penalty factor. The larger the value, the less suitable the channel is for high-priority detection tasks. The penalty weight coefficients are all positive real numbers, satisfying the following conditions: Typical values , ; : Test channel failure rate, value range Extracted from the failure rate field under the channel resource ID in the current dynamic resource evaluation matrix, it is defined as the ratio of the number of historical interruptions or anomalies to the total number of calls; : Continuous operating time of the device, a non-negative real number, extracted from the continuous operating time field of the device under the same resource ID in the current dynamic resource evaluation matrix; : Preset maximum recommended continuous working time, normal value, which is written into the storage module in advance by the device specifications.

[0110] Simple numerical example: Taking a voltage and current detection channel as an example, assume its failure rate Continuous operating time of equipment Preset maximum continuous working time Penalty weighting , Calculation process: First term ; Second item Summing the two terms yields .

[0111] The larger the penalty factor value, the more likely the detection items that depend on this channel should be delayed when generating the current detection item order, in order to avoid additional noise or misjudgment risks introduced by the device status.

[0112] The control circuit obtains scores for abnormal features. and penalty factors for each test channel Then, the detection items are reordered in real time based on the preset detection item dependency graph. The detection item dependency refers to the sequential calling relationship between each detection item, specifically including the correspondence between the detection image judgment and the voltage and current judgment, the correspondence between the working voltage and working current judgment and the normal operation status query, the correspondence between the communication protocol test and the data conversion loop test, and the calling relationship between the current detection result and the low-light signal detection. The sorting process does not traverse all possible detection item arrangements, but dynamically prunes the dependency graph based on the abnormal information in the first multi-dimensional feature vector: when the image abnormality confidence exceeds the first threshold or the sampling deviation exceeds the second threshold, the weight of the detection item node strongly correlated with visual and simulated sampling is moved forward; when the resource constraint penalty factor exceeds the third threshold, the detection item node corresponding to the test channel is moved backward or temporarily removed from the current order, and restored when the same batch of chips under test is tested later. The output of this step is the current detection item order, which records the name of the detection item to be executed by the current chip under test and its sequential relationship, and is sent to the "current detection item order" of the subsequent S320 for calling.

[0113] This section summarizes the technical effects: By combining the abnormal feature scores from both input sides with the resource constraint penalty factor, the originally fixed detection process is transformed into an adaptive reordering process based on the real-time status of the chip under test and the real-time status of the workstation resources. This makes the detection order respond to the directionality of the chip's abnormal signals and avoid noise interference that may be introduced by equipment with high failure rates or long-term operation.

[0114] Furthermore, following the anomaly feature scores obtained from formulas ① and ②, and penalty factors for each test channel The control circuit then enters the working mode, test signal, and test channel allocation processing stage. The input source for this stage is the current detection item sequence, which already indicates the order of detection items for the chip under test. The control circuit first reads the first-order detection item from the current detection item sequence and, combined with the penalty factor and channel function adaptability of each candidate test channel, makes a channel assignment decision. To uniformly describe the optimization logic of channel allocation, a detection item-test channel adaptability matrix is ​​introduced, and the comprehensive priority value for each detection item assigned to each candidate test channel is calculated using formula ③: ;

[0115] Variable and symbol definition: : Overall priority value; the higher the value, the better the allocation scheme. : Detection item sequence number, superscript, positive integer, taken from the sequence index of the current detection item; : Test channel resource ID number, superscript, positive integer, which corresponds one-to-one with the resource ID in the current dynamic resource evaluation matrix; : Assign weight coefficients, all of which are positive real numbers, with typical values. , ; Functional adaptability coefficient, a binary variable, with a range of values. or The control circuit determines the type of test item by looking up a preset matching table with the function of the test channel. : No. The penalty factor for each test channel is calculated using formula ②.

[0116] Simple numerical example: Suppose the current detection item to be assigned is the determination of the correspondence between voltage and current (denoted as...). Candidate test channels include voltage and current detection channels (denoted as...). ) and communication protocol test channel (denoted as Functionality compatibility can be obtained by looking up a table. , The penalty factor for the voltage and current sensing channel was calculated in the previous example. Weighting , .for , .for ,because Overall priority value Negative or meaningless values ​​are not considered. Therefore, the control circuit assigns the determination of the correspondence between voltage and current to the voltage and current detection channels.

[0117] After completing the channel allocation for the current priority detection item, the control circuit also needs to determine the operating mode and test signal for that detection item. Operating modes include running mode, pre-charge mode, and test mode; test signals include a first test signal and a second test signal. The selection of the operating mode is related to the type of detection item and the aforementioned abnormal feature score. The combined effect of abnormal feature scores. When the preset high anomaly threshold is exceeded, for detection items involving low-light signals, the pre-charge working mode is preferentially selected to capture the low-light emission characteristics of the static leakage path; when When in the intermediate range, the operating mode is selected to observe photon emission events during the dynamic switching process. After allocating each detection item, the control circuit reads whether the subsequent sequential detection item shares the same test channel as the current sequential detection item: if they share, the current test channel is retained and only the test signal is switched or the operating voltage is adjusted; if they do not share, the current test channel is released, the test channel corresponding to the next resource ID is called, and a channel switching record is written to the current operating mode test channel record. Through the above item-by-item allocation process, the control circuit generates a current operating mode test channel record, which includes at least the current detection item name, the corresponding operating mode, the corresponding test signal, the corresponding test channel, and the corresponding resource ID. This current operating mode test channel record is used as the output field name of this step and is called in the "Current Operating Mode Test Channel Record" of S330. The operating mode and test channel information in this record also provide the detection source correspondence for the associated anomaly judgment in S410.

[0118] This section summarizes the technical effects: By formalizing the channel allocation problem into a weighted selection process of fit and penalty factor, the allocation of working modes, test signals, and test channels not only ensures functional feasibility but also achieves dynamic avoidance of high-load, high-failure-rate channels, laying the foundation for the stability of subsequent test execution and the contextual consistency of recording.

[0119] Furthermore, following the aforementioned allocation and processing of the current operating mode test channel record, this stage involves the test machine, control circuit, PD control circuit, AUX control circuit, voltage and current detection circuit, video interface conversion circuit, and low-light detection lens executing the corresponding test items in the recorded order, and generating the current dynamic test record. The current operating mode test channel record provides the operating mode, test signal, test channel, and resource ID corresponding to each sequential test item, and the execution order is strictly constrained by this record. During execution, the raw results generated by each detection module must be written into the current dynamic test record according to a unified timing alignment mechanism to ensure that subsequent correlation anomaly judgments can perform spatiotemporal synchronous comparisons of the results of different test items within the same execution order window. To this end, the control circuit maintains a global detection timestamp counter, using the system clock cycle as the basic timing unit, recording the start and end times of each test item. For low-light signal detection, in addition to recording the presence and location of the low-light signal, a high-precision timestamp is used to mark the occurrence time of each photon emission event, and this is aligned with the electrical parameter sampling records within the same time window. Formula ④ defines a measure of the temporal correlation between low-light events and current spike events, used to generate a note field in the current dynamic detection record that characterizes the strength of the spatiotemporal correlation: ;

[0120] Variable and symbol definition: The maximum cross-correlation value between the low-light signal and the current spike is used to quantify the degree of timing synchronization. Time offset, within the preset range Internal value; : Preset maximum allowable time deviation, normal value, typical value ; : A binary sequence of photon counting pulses in micro-light, time The function, the time of photon arrival is taken Take the rest It is generated by pulse shaping from the output of the low-light detection lens; : Binarized sequence of current sampling rate of change, time The function, where the absolute value of the current difference exceeds the peak threshold. Take the rest It is generated by sampling circuit collecting current data and then comparing it with differential and threshold values; Operators Discrete cross-correlation operator, calculates the inner product of two sequences at different offsets; The maximum value function returns the maximum element in a given set.

[0121] Simple numerical example: Suppose in Within the observation window, the low-light detection lens is constantly... and If a photon emission event is detected at a certain location, then The sequence is in and Disposal Other treatments The synchronous current change rate sequence is shown in and A spike appears at a certain point, and after threshold determination... exist and Disposal Other treatments .Pick ,calculate Time cross-correlation value ; hour, and Alignment yields the product. ; and Alignment required At this point, the product is aligned. The maximum cross-correlation value among all offsets is (Before normalization), after normalization A higher value indicates a significant temporal correlation between low-light emission and current spikes.

[0122] During the execution of the test items, if the first test item in the record is a communication protocol test, the tester first calls the PD control circuit and AUX control circuit to establish a communication protocol test path, and writes the physical layer handshake status of the CC channel and AUX channel, the protocol version negotiation result, and the packet error rate into the current dynamic test record. If the subsequent test item is a data conversion loop test, the control circuit calls the video interface conversion circuit, sends the preset test pattern data to the transmitting end, reads it back from the receiving end after passing through the internal video data conversion loop of the chip under test, compares it pixel by pixel to generate a bit error rate record, and writes it into the current dynamic test record. If the subsequent test items are normal operation status query and power consumption judgment, the digital adjustable power supply circuit maintains the working voltage output, the control circuit reads the internal status register of the chip under test to determine whether it has entered the normal operation state, and the power consumption detection circuit collects the power supply loop current and multiplies it by the working voltage to obtain the power consumption sampling value. Both are written into the normal operation status record and the power consumption record in sequence. If the subsequent test item is low-light signal detection, the chip under test is placed face up on the transparent stage, and the low-light detection lens is aligned with the chip substrate area from the back of the transparent stage. The control circuit transmits the corresponding test signal to the chip under test according to the working mode specified in the current working mode test channel record. After the chip enters a stable working state, the low-light signal is continuously collected, and the timing correlation obtained by formula ④ is used. Write it into the current dynamic detection record.

[0123] To further standardize the organization of different types of detection records in the current dynamic detection record, the control circuit adopts a unified timestamp index structure. Formula ⑤ defines the timestamp index structure in the current dynamic detection record. Logical address mapping relationship of each record entry: ;

[0124] Variable and symbol definition: The current dynamic detection record is the first one. Each record entry is a data structure containing multiple fields; Record sequence number, superscript, positive integer, incremented in execution order; : Start execution timestamp, read from the system clock counter; The execution end timestamp is read by the system clock counter; : Detection item type enumeration value, text label, taken from the test channel record of the current working mode; : Test channel resource ID identifier, taken from the test channel record of the current working mode; : Working mode enumeration value, text label, values ​​include running working mode, precharge working mode, test mode; The core result value varies in type depending on the detection item, such as pass / fail flag, bit error rate value, power consumption value, and coordinates of the low light signal location. : No. The temporal correlation degree corresponding to each record is only valid when the detection item type is low-light signal detection. It is calculated by formula ④. In other types of detection items, this field is set to empty or default value.

[0125] Simple numerical example: Suppose the first Each record entry is for the detection of faint light signals, and its start timestamp is... Clock cycle, end timestamp Clock cycle, type "Low-light signal detection", channel Low-light detection lens corresponding channel resource ID, mode "Pre-charge working mode", core results Photon emission event location coordinates Temporal correlation This record entry then provides a complete description of the spatiotemporal context of this low-light detection.

[0126] After all test items are executed in the current test item order, the tester, control circuit, and each detection module merge their respective results according to the structure defined in Formula ⑤ and the execution order to form the current dynamic test record. This record serves as the output field name for this step and is directly input and called by the "Current Dynamic Test Record" in subsequent S410. At the same time, the power consumption record, normal operation status record, and low-light signal record in this record also correspond to the fields in the subsequent test result write-back in S430.

[0127] This section summarizes the technical effects: By introducing a temporal cross-correlation metric between micro-light events and electrical parameter peaks, and a unified timestamp index record structure, the previously isolated and scattered execution results of detection items are organized into sequential records with a spatiotemporal synchronization context. This provides a structured data foundation for subsequent anomaly identification, enabling precise tracing of anomaly sources and concurrency relationships. Formulas ④ and ⑤ together achieve a dimensionality upgrade from "single-point detection result records" to "multi-dimensional spatiotemporal correlation records," allowing subsequent steps to perform cross-modal comprehensive analysis based on multi-source data within the same execution sequence window.

[0128] Step S400 includes at least steps S410-S430: S410. Obtain the current dynamic detection record and perform correlation processing for voltage and current correspondence anomalies, normal operation status anomalies, communication protocol test failures, data conversion loop test failures, and low-light signal and working mode mismatches to obtain a correlation anomaly judgment record. Specifically, the input source for this step is the current dynamic detection record output from the previous steps. The current dynamic detection record includes communication protocol test records, data conversion loop test records, normal operation status records, power consumption records, low-light signal records, working mode records, test channel records, and resource ID records formed after execution in the order of the current detection items. The correlation processing is jointly executed by the control circuit and the judgment module. First, the corresponding records are read in the same window according to the same chip under test, the same working mode, the same test channel, and the same execution order. Then, the results of multiple detection items are compared side by side and correlated. The abnormal correspondence between voltage and current refers to a deviation in the correspondence between the working voltage, working current, first voltage sample value, and first current sample value in the current dynamic detection record under the same test channel; the abnormal normal operation state refers to the query result showing that it is not in normal operation state under the same working mode; the communication protocol test failure refers to the protocol failure record appearing in the current dynamic detection record for the Configuration Channel (CC) or Auxiliary Channel (AUX); the data conversion loop test failure refers to the failure record or abnormal bit error rate record appearing in the data conversion loop test corresponding to the video interface adapter circuit; the mismatch between the low light signal and the working mode refers to the inconsistency between the position, occurrence sequence, or occurrence state of the low light signal detected in the working mode or pre-charging working mode and the calling state corresponding to that working mode. Furthermore, the control circuit first extracts the working mode record and test channel record from the current dynamic detection record, and then reads the corresponding working voltage, working current, first voltage sample value and first current sample value to form a first association judgment group; then it reads the normal operation status record in the same execution sequence window, and judges whether the abnormal correspondence between the voltage and current occurs at the same time as the abnormal normal operation status. If they occur at the same time, the first association abnormal item is written.

[0129] Afterwards, the control circuit continues to read the communication protocol test records and data conversion loop test records of the CC channel and AUX channel corresponding to the same chip under test. If the communication protocol test fails and the data conversion loop test fails or the bit error rate is abnormal at the same time, the second associated exception item is written.

[0130] Next, the control circuit reads the low-light signal record, the low-light signal position, and the current working mode record, and determines whether the low-light signal does not match the current working mode. If they do not match, the third associated anomaly item is written.

[0131] Understandably, this step does not use a single test result for direct judgment. Instead, it requires that at least one associated anomaly be generated for the same chip under test in the same operating mode before proceeding to the next judgment link. If there are test channel switching records in the current dynamic detection record, the records before and after the switching point are associated separately to avoid mixing results from different test channels. If there are duplicate execution records, the most recent stable execution record is read first, and the previous fluctuation record is retained in the current dynamic detection record as reference content for the detection record.

[0132] In one engineering embodiment, after a chip under test completes normal operation status query, power consumption judgment, communication protocol test and low light signal detection in sequence, the control circuit first compares the correspondence between the working voltage, working current and the sampled value, and then reads the normal operation status record; when both are abnormal at the same time, the first associated abnormal item is written.

[0133] Subsequently, the protocol records of the CC channel and AUX channel, as well as the data conversion loop test records, are read. When the protocol fails and the bit error rate is abnormal, a second associated anomaly is written. If the same chip under test exhibits a mismatch between the low-light signal and the operating mode in the pre-charge mode, a third associated anomaly is written.

[0134] The output product formed by the above association processing is the association anomaly judgment record. The association anomaly judgment record is used as the output field name of this step and is directly called by the "association anomaly judgment record" in the subsequent S420. At the same time, the association anomaly items in the association anomaly judgment record also correspond one-to-one with the detection result write-back content in the subsequent S430.

[0135] S420. Based on the associated anomaly judgment record, perform anomaly chip marking and detection result sending processing to obtain anomaly chip marking record.

[0136] Specifically, the input source for this step is the associated anomaly judgment record output from the aforementioned steps. The associated anomaly judgment record includes a first associated anomaly item, a second associated anomaly item, or a third associated anomaly item formed by the same chip under test in the same working mode, as well as the corresponding test channel record, working mode record, and resource ID record.

[0137] This step is executed collaboratively by the judgment module, the test machine, and the communication interface. Specifically, the number and corresponding relationships of associated anomaly items in the associated anomaly judgment record are first read, and then it is determined whether the anomaly chip marking conditions are met. The anomaly chip marking conditions are that the same chip under test has at least two associated anomaly items in the same operating mode, or that the same chip under test has consecutive associated anomaly items within the same execution sequence window, accompanied by the same test channel anomaly record.

[0138] When the above conditions are met, the judgment module marks the chip under test as an abnormal chip and writes the chip detection card slot position, test channel position, working mode position and abnormal item position on the test machine side; when the above conditions are not met, the abnormal chip marking is not performed, and the associated abnormal judgment record is retained for subsequent test result sending processing.

[0139] Furthermore, the transmission of the detection results is performed by the communication interface. The communication interface reads the chip number under test, chip detection card slot position, associated anomaly items, working mode record, and test channel record from the associated anomaly judgment record, and then sends this set of contents to the host computer. After receiving the data, the host computer retains the detection results and transmission status records of the current chip under test. If the tester detects that the same chip detection card slot already has a record of the previous chip under test's audible and visual indicator not being reset when performing anomaly chip marking, it first writes the current mark, and then synchronously updates the transmission order of the current chip under test to avoid confusion between the anomaly chip mark positions of the current chip under test and the previous chip under test.

[0140] Understandably, the abnormal chip marking record is not a simple flag bit, but a formal output record formed by the chip under test after this round of association judgment. It includes at least the abnormal chip marking status, the content of the associated abnormal item, the detection result sending status, the chip detection card slot position, and the test channel position.

[0141] In an operational engineering embodiment, when a chip under test simultaneously possesses a first associated anomaly and a second associated anomaly in the same operating mode, the judgment module immediately marks the chip under test chip detection socket corresponding to the chip under test chip on the test machine as an abnormal chip, and sends the test result, operating mode record and test channel record of the chip under test chip to the host computer through the communication interface; after the sending is completed, the sending status and the abnormal chip marking status are written together into the abnormal chip marking record.

[0142] The output product formed after the above processing is the abnormal chip mark record. The abnormal chip mark record is used as the output field name of this step and is directly called by the "abnormal chip mark record" in the subsequent S430. In addition, the sending status and abnormal item content in it also provide input basis for the write-back order in the subsequent updated detection record.

[0143] S430. Based on the abnormal chip marking record, perform write-back processing of detection results, detection record, detection duration, operating voltage, operating current and power consumption to obtain the updated detection record.

[0144] Specifically, the input source for this step is the abnormal chip marking record output from the previous steps. The abnormal chip marking record already includes the abnormal chip marking status, detection result sending status, associated abnormal item content, chip detection card slot location, test channel location, working mode record, and corresponding resource ID record.

[0145] This step is jointly performed by the control circuit and the host computer for write-back processing. First, the current dynamic detection record corresponding to the current chip under test is located based on the abnormal chip mark record. Then, the detection result, detection record, detection duration, working voltage, working current and power consumption are read from the current dynamic detection record. Finally, the data is written back to the same batch of detection record set according to the current chip under test number.

[0146] The write-back of detection results refers to writing the marked or unmarked state of the abnormal chip back to the detection result position of the current chip under test; the write-back of detection records refers to writing the working mode record, test channel record, resource ID record, and associated abnormal item content in the current dynamic detection record back to the batch of detection records; the write-back of detection duration refers to writing the continuous execution duration from the current detection item sequence to the completion of abnormal chip marking back to the detection duration position; the write-back of working voltage, working current, and power consumption refers to writing the voltage, current, and power consumption records of the current chip under test in this round of detection back to the detection record set and the corresponding position of the current dynamic resource evaluation matrix.

[0147] Furthermore, during the write-back process, the control circuit simultaneously checks the corresponding resource ID in the current dynamic resource evaluation matrix. If a certain test channel continuously exhibits associated abnormal items in this round of testing, the corresponding test record and failure rate of that test channel are updated to the current dynamic resource evaluation matrix. If a certain testing device runs continuously in this round of testing, its continuous working time record is updated simultaneously.

[0148] In this way, the write-back process not only writes back the detection results of the chip under test itself, but also updates the resource record of the current chip detection station at the same time. This ensures that when the chip under test re-enters S210, the "detection record" that is called has already included the new content of this round of detection. Furthermore, S220 will re-integrate the device status, real-time load, failure rate and continuous working time of the device based on the updated detection record.

[0149] Understandably, the minimum set in this step is the detection result, detection record, detection duration, operating voltage, operating current, and power consumption. The aforementioned content directly forms the basis for the next round of detection process updates. The transmission status, chip detection card slot position, and operating mode records retained by the host computer are preferred extended records, which will be called again when it is necessary to trace the same batch of detection records.

[0150] In one engineering embodiment, when a chip under test is marked as an abnormal chip, the control circuit reads the chip detection card position and test channel position from the abnormal chip marking record, and then extracts the detection result, normal operation status record, power consumption record, operating voltage record and operating current record of the chip under test from the current dynamic detection record. Subsequently, these contents are written back to the detection record set of the current batch, and the detection record of the corresponding test channel and the continuous working time of the device are synchronously written into the current dynamic resource evaluation matrix.

[0151] The output product formed after the above processing is the updated detection record. The updated detection record is used as the output field name of this step. It is called by "Detection Record" in S210 in the subsequent process, and it also continues to affect the detection item dependency matching and reordering processing in S310 through the update of the current dynamic resource evaluation matrix.

[0152] In summary, this step integrates the abnormal chip marking results with the detection results, detection duration, operating voltage, operating current, and power consumption, writing them back to the same batch of detection records and the current dynamic resource evaluation matrix. This prevents the chip detection station from focusing solely on a single chip. Compared to existing methods that only output a single result after testing, this step converts the current round of detection content into updated detection records that can be directly accessed by subsequent chips under test. Subsequent processes can read these newly added records when entering S210 and S310, thus forming a continuously updated detection chain.

[0153] Example 2: Figure 2 A structural block diagram of an intelligent detection and adaptive optimization system for integrated circuit chips according to an embodiment of the present invention is shown. Figure 2 As shown, the structure may include: The chip positioning contact record generation unit 01 is used to acquire the chip under test, the chip detection card holder, and a set of probes, perform rapid positioning and precise holding processing, and obtain a chip positioning contact record. Specifically, the chip positioning contact record generation unit receives the chip under test, the chip detection card holder, and a set of probes as input objects. The chip detection card holder is provided with a placement slot, a detection box, a guide hole, a sleeve, and a test channel. The set of probes is arranged corresponding to the probe positions of the chip detection card holder. During processing, the chip under test is first placed in the placement slot or detection box, and then the alignment and holding are completed by the pressure rod, reset piece, adjustment plate, positioning plate, support column, and spring assembly. The rapid positioning corresponds to the relative correction of the edge of the chip under test with the adjustment plate and positioning plate. The precise holding corresponds to the chip under test maintaining a fixed contact state under the action of the pressure rod and spring assembly. If contact offset or insufficient reset occurs, the chip positioning contact record generation unit calls the reset piece and adjustment plate to redo the contact action, and then writes the redo process into the detection record. After processing, a chip positioning contact record is formed. The chip positioning contact record records the position of the chip under test, the probe contact state, the holding state, and the repositioning state. The chip positioning contact record is transmitted to the first detection state generation unit for use as the chip positioning contact record, while the corresponding detection record is retained for subsequent use by the first multi-dimensional feature vector generation unit.

[0154] The first detection state generation unit 02, connected to the chip positioning contact record generation unit, is used to acquire detection images and perform voltage and current sampling processing based on the chip positioning contact record to obtain a first detection image sampling record. Based on the first detection image sampling record, it integrates the detection image, working voltage, working current, first voltage sample value, and first current sample value to obtain a first detection state. Specifically, the first detection state generation unit receives the chip positioning contact record. The chip positioning contact record includes the probe contact state, test channel position, and holding state. The first detection state generation unit activates the corresponding acquisition components in the camera, microscope, image conversion module, and image output module according to the record to complete the acquisition of the detection image; simultaneously, it activates the control circuit, voltage generation circuit, and sampling circuit to complete the acquisition of the working voltage, working current, first voltage sample value, and first current sample value. If the chip positioning contact record shows contact fluctuations, a resampling is performed first, and then the two sampling states are written into the first detection image sampling record. During the integration phase, the first detection state generation unit organizes the detection image with the operating voltage, operating current, first voltage sample value, and first current sample value according to the same chip under test, the same test channel, and the same contact state to form a first detection state. The first detection state includes the detection image content, voltage and current content, and sample content. The first detection state is provided to the first multi-dimensional feature vector generation unit as a first detection state call, while retaining the first detection image sampling record and the detection record for subsequent correspondence verification.

[0155] The first multi-dimensional feature vector generation unit 03, connected to the first detection state generation unit, is used to acquire the first detection state and detection record, and perform matching processing on the detection image, working voltage, working current, first voltage sample value, and first current sample value to obtain the first multi-dimensional feature vector. Specifically, the first multi-dimensional feature vector generation unit receives the first detection state and detection record. During processing, the detection image, working voltage, working current, first voltage sample value, and first current sample value are first extracted from the first detection state, and then matched according to the same chip under test number, the same test channel position, and the same probe contact state. If there are multiple sets of sampling records for the same chip under test, the resampling state and contact state in the detection records are read, and a set of records corresponding to the stable contact state is screened out. After the screening is completed, the first multi-dimensional feature vector generation unit arranges the detection image, working voltage, working current, first voltage sample value, first current sample value, and detection record into the same data object in a fixed order to form the first multi-dimensional feature vector. The first multi-dimensional feature vector is passed to the current dynamic resource evaluation matrix generation unit and the current detection item sequence generation unit, respectively, and used as the first multi-dimensional feature vector. At the same time, the corresponding detection record is registered in this unit for subsequent verification.

[0156] The dynamic resource evaluation matrix generation unit 04, connected to the first multi-dimensional feature vector generation unit, is used to integrate equipment status, real-time load, failure rate, detection records, and continuous working time of the equipment based on the first multi-dimensional feature vector to obtain a dynamic resource evaluation basic record. Based on this basic record, resource identification and evaluation index arrangement are performed to obtain the current dynamic resource evaluation matrix. Specifically, the current dynamic resource evaluation matrix generation unit receives the first multi-dimensional feature vector. The detection record positions in the first multi-dimensional feature vector correspond to the usage status of the test machine, voltage and current detection circuit, sampling circuit, chip detection card holder, test channel, low-light detection lens, and a set of probes. During processing, the equipment status, real-time load, failure rate, detection records, and continuous working time of the equipment are first read from each detection device, and then integrated with the current chip under test record in the first multi-dimensional feature vector to form a dynamic resource evaluation basic record. Subsequently, the current dynamic resource evaluation matrix generation unit assigns resource identifiers to each detection device and test channel, and then arranges the equipment status, real-time load, failure rate, detection records, and continuous working time of the equipment as evaluation indicators into the corresponding positions to form the current dynamic resource evaluation matrix. If a test channel has a record of high failure rate or long continuous working time, this state is retained in the current dynamic resource evaluation matrix. The current dynamic resource evaluation matrix is ​​passed to the current detection item sequence generation unit as the current dynamic resource evaluation matrix, while the basic dynamic resource evaluation record is retained for subsequent use when updating and re-fed the detection record.

[0157] The detection item order generation unit 05 is connected to the first multi-dimensional feature vector generation unit and the current dynamic resource evaluation matrix generation unit. It is used to obtain the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, perform detection item dependency matching and reordering processing, and obtain the current detection item order. Specifically, the current detection item order generation unit simultaneously receives the first multi-dimensional feature vector and the current dynamic resource evaluation matrix. The first multi-dimensional feature vector reflects the current state of the chip under test. The current dynamic resource evaluation matrix reflects the resource state of the current chip testing station. During processing, the detection image record, voltage and current record, and sampling record are first read from the first multi-dimensional feature vector. Then, the evaluation indicators of the test machine, test channel, sampling circuit, low-light detection lens, and a set of probes are read from the current dynamic resource evaluation matrix. Subsequently, the communication protocol test, data conversion loop test, normal operation status query, power consumption judgment, and low-light signal detection are matched according to the detection item dependency relationship to form a sequence corresponding to the current state of the chip under test. If the current dynamic resource evaluation matrix shows that a certain test channel is under high real-time load or high failure rate, then the detection items that depend on that test channel will be moved to the back, and other detection items will be moved to the front. After processing, the current detection item order is obtained. The current detection item order is passed to the current working mode test channel record generation unit as the current detection item order, while retaining the correspondence between the matching results and resource identifiers for subsequent updates.

[0158] The working mode test channel record generation unit 06, connected to the current detection item sequence generation unit, is used to perform working mode, test signal, and test channel allocation processing based on the current detection item sequence to obtain the current working mode test channel record. Specifically, the current working mode test channel record generation unit receives the current detection item sequence. During processing, each detection item is read sequentially first, and then the corresponding working mode, test signal, and test channel are allocated to each detection item. For normal operation status query and power consumption judgment, the test channels corresponding to the digital adjustable power supply circuit and voltage and current detection circuit are called. For communication protocol testing, the test channels corresponding to the configuration channel and auxiliary channel are called. For data conversion loop testing, the test channel corresponding to the video interface conversion circuit is called. For low-light signal detection, the test channels corresponding to the transparent stage and low-light detection lens are called, and the operating working mode or pre-charge working mode is given. If adjacent detection items share the same test channel, the current test channel is retained, and only the test signal or working mode is adjusted. If adjacent detection items do not share the same test channel, the current test channel is released and switched to the channel corresponding to the next resource identifier. After processing, the current working mode test channel record is formed. The current working mode test channel record is transmitted to the current dynamic detection record generation unit for use as the current working mode test channel record, and the channel switching record and working mode switching record are registered in this unit.

[0159] The dynamic detection record generation unit 07, connected to the current working mode test channel record generation unit, is used to perform communication protocol testing, data conversion loop testing, normal operation status query, power consumption judgment, or low-light signal detection processing based on the current working mode test channel record to obtain the current dynamic detection record. Specifically, the current dynamic detection record generation unit receives the current working mode test channel record. During processing, the test machine, control circuit, configuration channel control circuit, auxiliary channel control circuit, voltage and current detection circuit, video interface conversion circuit, and low-light detection lens execute the corresponding test items sequentially according to the order of the current working mode test channel record. When performing communication protocol testing, the protocol records of the configuration channel and auxiliary channel are read. When performing data conversion loop testing, the bit error rate record and loop status record are read. When performing normal operation status query, the query result in the current working mode is read. When performing power consumption judgment, the power consumption record is read. When performing low-light signal detection, the record corresponding to the low-light signal position and working mode is read. If a test channel is disconnected during execution, the interruption status is written to the current dynamic detection record, and subsequent unaffected test items continue to be executed. After processing, a current dynamic detection record is generated. This current dynamic detection record is passed to the associated anomaly judgment and updated detection record generation unit for use as the current dynamic detection record, while retaining the execution order, working mode, and test channel records of each detection item for subsequent associated processing.

Claims

1. A method for intelligent detection and adaptive optimization of integrated circuit chips, characterized in that, include: S100: Acquire the chip under test, chip detection card holder and a set of probes, perform rapid positioning, precise holding, detection image acquisition, voltage and current sampling and integration processing to obtain the first detection state; Wherein, the chip under test is a chip object that enters the chip testing station and is ready to be connected to the testing process; the chip testing card holder is a fixed component that carries the chip under test and provides test channels, probe positions and interface access positions; the set of probes is a set of test contacts that make contact with the pins or interfaces of the chip under test. S200. Based on the first detection state, perform matching processing, and integrate device status with resource ID and evaluation index arrangement processing to generate a first multi-dimensional feature vector and the current dynamic resource evaluation matrix. S300. Based on the first multi-dimensional feature vector and the current dynamic resource evaluation matrix, perform detection item dependency matching and reordering processing, and execute working mode allocation, test signal allocation, test channel allocation and detection item execution processing to generate the current dynamic detection record. S400. Based on the current dynamic detection record, perform associated anomaly judgment and anomaly chip marking, send detection results and write back detection results to generate updated detection records.

2. The method according to claim 1, characterized in that, The process of rapid positioning, precise holding, detection image acquisition, and voltage and current sampling processing includes: The rapid positioning and precise holding process includes: placing the chip under test into the placement slot of the chip detection card holder; using a pressure rod, an adjustment plate, and a positioning plate to limit the position and hold the chip under test on the surface; and completing coarse and fine alignment according to the probe distribution position in the chip detection card holder, so that a group of probes enters a pressure contact state with the pins of the chip under test; and writing the position change, pressure state, probe contact state, and whether repositioning has occurred into the chip positioning contact record. The detection image acquisition and voltage and current sampling processing includes: based on the contact state in the chip positioning contact record, the camera acquires the detection image; the control circuit controls the voltage generation circuit to provide a test signal to the IO pin through the sampling circuit and acquire the first voltage sampling value and the first current sampling value; at the same time, the working voltage and working current are recorded; when there is a repositioning record or contact fluctuation record, the detection image acquisition is performed first and then the voltage and current sampling is performed; and the sudden change in the sampling result is compared with the contact state in the chip positioning contact record and then written into the first detection image sampling record.

3. The method according to claim 1, characterized in that, The integration process includes: The integration process includes: matching and merging the detection images, working voltage, working current, first voltage sample value and first current sample value obtained by the same chip under test in the same chip detection card socket, the same pressure state and the same test channel; when there is a repositioning record, the record after the pressure bar is stably pressed down is selected as the valid record to form the first detection state.

4. The method according to claim 1, characterized in that, The matching process includes: The matching process includes: detecting the image, operating voltage, operating current, first voltage sample value, and first current sample value; The matching process includes: the control circuit matching the detection image with the working voltage, working current, first voltage sample value and first current sample value one by one according to the same chip under test, the same chip detection card socket, the same test channel and the same contact state, forming an effective matching record, and arranging it in a fixed order as a first multi-dimensional feature vector.

5. The method according to claim 1, characterized in that, The process of integrating device status and arranging resource IDs and evaluation metrics includes: The equipment status integration and resource ID and evaluation index arrangement processing includes: accessing the detection records of the test machine, voltage and current detection circuit, sampling circuit, PD control circuit, AUX control circuit, low-light detection lens and a set of probes from the detection record positions in the first multi-dimensional feature vector; integrating the equipment status, real-time load, failure rate and continuous working time of each detection device into a dynamic resource evaluation basic record; establishing resource IDs according to the detection resource type; and arranging the contents of the dynamic resource evaluation basic record into the current dynamic resource evaluation matrix according to the resource ID, wherein the equipment status, real-time load, failure rate, detection record and continuous working time of the same resource ID are arranged in the same direction.

6. The method according to claim 1, characterized in that, The process of dependency matching and reordering of detection items includes: The detection item dependency matching and reordering process includes: the control circuit reads the detection image position, working voltage position, working current position, first voltage sample value position, first current sample value position, and detection record position from the first multi-dimensional feature vector, and reads the device status, real-time load, failure rate, detection record, and continuous working duration of each resource ID in the current dynamic resource evaluation matrix. Based on the sequential calling relationship between detection items, the detection order of the current chip under test is generated in real time. Specifically, when the working voltage fluctuates while the working current is stable in the first multi-dimensional feature vector, the normal operation status query is prioritized. When the correspondence between the first voltage sample value and the first current sample value is abnormal, the correspondence between voltage and current is prioritized. When the failure rate of a certain test channel in the current dynamic resource evaluation matrix is ​​higher than that of other resource IDs in the same batch, the test channel is moved to the back, thereby generating the current detection item order.

7. The method according to claim 1, characterized in that, The process of assigning working modes, test signals, test channels, and executing test items includes: The working mode, test signal and test channel allocation process includes: the control circuit determines the working mode, test signal and test channel corresponding to each test item according to the current test item sequence. The working mode includes running working mode, pre-charging working mode and test mode. The test channel includes voltage and current detection channel, communication protocol test channel, data conversion loop test channel and corresponding channel for low light signal detection. The execution process of the detection item includes: the test machine, control circuit, PD control circuit, AUX control circuit, voltage and current detection circuit, video interface conversion circuit and low light detection lens execute the corresponding detection items according to the current working mode test channel record, and merge the communication protocol test record, data conversion loop test record, normal operation status record, power consumption record, low light signal record, and the working mode record and test channel record corresponding to each detection item into the current dynamic detection record according to the execution order.

8. The method according to claim 1, characterized in that, The process of handling correlation anomalies includes: The associated anomaly judgment processing includes: the control circuit and the judgment module read corresponding records from the current dynamic detection record according to the same chip under test, the same working mode, the same test channel and the same execution sequence window, and perform parallel comparison and correspondence. Among them, when the voltage and current correspondence anomaly and the normal operation state anomaly occur simultaneously in the same execution sequence window, they are written into the first associated anomaly item; when the communication protocol test fails and the data conversion loop test fails or the bit error rate is abnormal, they are written into the second associated anomaly item; when the low light signal does not match the current working mode, they are written into the third associated anomaly item, thereby forming an associated anomaly judgment record.

9. The method according to claim 1, characterized in that, The process of anomaly chip marking, detection result transmission, and detection result write-back includes: The abnormal chip marking and detection result sending process includes: when the judgment module marks the chip under test as an abnormal chip in the same working mode of the associated abnormal judgment record, or when the associated abnormal items appear consecutively in the same execution sequence window and are accompanied by the same test channel abnormal record, the judgment module sends the chip number, chip detection card slot position, associated abnormal items, working mode record and test channel record to the host computer through the communication interface; The detection result write-back process includes: the control circuit locates the current dynamic detection record corresponding to the current chip under test based on the abnormal chip marking record, writes back the detection result, detection record, detection duration, working voltage, working current and power consumption to the same batch of detection record set, and synchronously updates the detection record, failure rate and continuous working duration of each resource ID in the current dynamic resource evaluation matrix to obtain the updated detection record.

10. An intelligent detection and adaptive optimization system for integrated circuit chips, characterized in that, include: The chip positioning contact record generation unit, the first detection state generation unit, the first multi-dimensional feature vector generation unit, the dynamic resource evaluation matrix generation unit, the detection item sequence generation unit, the working mode test channel record generation unit, and the dynamic detection record generation unit are connected in sequence to implement the method described in any one of claims 1-9.

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