Display substrate, method for operating the same, and display apparatus

Abstract

A display substrate, a working method thereof and a display device, the display substrate comprising a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least part of the sub-pixels comprising a pixel driving circuit, at least one pixel driving circuit comprising a driving sub-circuit (M01), a blocking sub-circuit (M02), a blocking control end and a data writing node (N5), the driving sub-circuit (M01) comprising a driving control end; in the same pixel driving circuit, the blocking control end is electrically connected with the blocking sub-circuit (M02), and the blocking sub-circuit (M02) is arranged between the data writing node (N5) and the driving control end; the blocking sub-circuit (M02) is arranged to write a signal of the data writing node (N5) to the driving control end under control of the blocking control end.

Description

Display substrate and its working method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its working method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, including a substrate and a plurality of sub-pixels disposed on one side of the substrate. At least some of the sub-pixels include pixel driving circuits. At least one pixel driving circuit includes a driving sub-circuit, an isolation sub-circuit, an isolation control terminal, and a data writing node. The driving sub-circuit includes a driving control terminal. In the same pixel driving circuit, the isolation control terminal is electrically connected to the isolation sub-circuit, and the isolation sub-circuit is disposed between the data writing node and the driving control terminal.

[0006] The isolation sub-circuit is configured to write the signal of the data writing node to the drive control terminal under the control of the isolation control terminal.

[0007] In an exemplary embodiment, the driving sub-circuit includes a third transistor as a driving transistor, and the blocking sub-circuit includes a tenth transistor as a blocking transistor. The control electrode of the third transistor serves as the driving control terminal, and the control electrode of the tenth transistor serves as the blocking control terminal.

[0008] In an exemplary embodiment, the pixel driving circuit further includes at least one capacitor, the at least one capacitor including a first capacitor;

[0009] The first electrode of the tenth transistor is electrically connected to the data writing node, the second electrode of the tenth transistor is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the control electrode of the third transistor.

[0010] In an exemplary embodiment, the at least one capacitor further includes a second capacitor, wherein the second plate of the first capacitor and the first plate of the second capacitor share a common plate;

[0011] The second plate of the first capacitor and the first plate of the second capacitor serve as the control electrode of the third transistor; the orthogonal projections of the first capacitor, the second capacitor, and the third transistor on the substrate at least partially overlap.

[0012] In an exemplary embodiment, the pixel driving circuit includes a plurality of transistors, the plurality of transistors including a first type of transistor and a second type of transistor, the first type of transistor including the third transistor, and the second type of transistor including the tenth transistor;

[0013] In a direction perpendicular to the plane of the substrate, the display substrate includes a shielding layer, an active layer of a first type of transistor, a control electrode of the first type of transistor, a second electrode plate of a second capacitor, an active layer of a second type of transistor, a control electrode of the second type of transistor, and a first electrode and a second electrode of the plurality of transistors, which are sequentially disposed on one side of the substrate.

[0014] The first plate of the first capacitor is located in the shielding layer, and the second plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer as the control electrode of the first type of transistor.

[0015] In an exemplary embodiment, the orthographic projections of the first plate of the first capacitor, the second plate of the first capacitor, and the second plate of the second capacitor onto the substrate at least partially overlap.

[0016] In an exemplary embodiment, the first type of transistor further includes a first transistor as a reset transistor, and the second type of transistor further includes a second transistor as a compensation transistor.

[0017] The second terminals of the first transistor and the second transistor are connected to the second terminal of the third transistor, and the first terminal of the second transistor is electrically connected to the control terminal of the third transistor;

[0018] In the same sub-pixel, the orthogonal projections of the first transistor and the second transistor onto the substrate at least partially overlap.

[0019] In an exemplary embodiment, the first type of transistor further includes a fourth transistor as a data write transistor and a ninth transistor as a reset transistor, the second terminals of the fourth transistor and the ninth transistor being electrically connected to the data write node.

[0020] In an exemplary embodiment, the display substrate further includes a first light-emitting control line, a second light-emitting control line, and a first power line. The first light-emitting control line and the second light-emitting control line are disposed on the same layer as the control electrode of the first type of transistor. The first power line is located on the side of the first electrode and the second electrode of the plurality of transistors away from the substrate.

[0021] The first type of transistor further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a second light-emitting control transistor. The first terminal of the fifth transistor and the second plate of the second capacitor are electrically connected to the first power line. The second terminal of the fifth transistor is connected to the first terminal of the third transistor. The first terminal of the sixth transistor is electrically connected to the second terminal of the third transistor, the second terminal of the first transistor, and the second terminal of the second transistor.

[0022] The region where the first light-emitting control line overlaps with the active layer of the fifth transistor serves as the control electrode of the fifth transistor; the region where the first light-emitting control line overlaps with the active layer of the ninth transistor serves as the control electrode of the ninth transistor; and the region where the second light-emitting control line overlaps with the active layer of the sixth transistor serves as the control electrode of the sixth transistor.

[0023] In a plane parallel to the substrate, the first light-emitting control line and the second light-emitting control line extend along a first direction, and the first power line extends along a second direction, with the first direction intersecting the second direction; in the same sub-pixel, in the second direction, the first light-emitting control line and the second light-emitting control line are located on the same side of the third transistor, and the second light-emitting control line is located on the side of the first light-emitting control line away from the third transistor.

[0024] In an exemplary embodiment, the display substrate further includes a third reset control line, and the first type of transistor further includes a seventh transistor as a reset transistor and an eighth transistor as a reset transistor.

[0025] The third reset control line is disposed on the same layer as the control electrode of the first type of transistor. The third reset control line extends along the first direction. In the same sub-pixel, in the second direction, the third reset control line is located on the side of the second light emission control line away from the third transistor.

[0026] The region where the third reset control line overlaps with the active layer of the seventh transistor serves as the control electrode of the seventh transistor, and the region where the third reset control line overlaps with the active layer of the eighth transistor serves as the control electrode of the eighth transistor.

[0027] In an exemplary embodiment, within the same pixel driving circuit, in the second direction, the tenth transistor and the fourth transistor are located on opposite sides of the third transistor, the fifth transistor and the ninth transistor are located on the side of the fourth transistor away from the third transistor, the sixth transistor is located on the side of the fifth transistor away from the fourth transistor, and the seventh transistor and the eighth transistor are located on the side of the sixth transistor away from the fifth transistor; in the first direction, the fifth transistor, the eighth transistor, and the tenth transistor are located on one side of the third transistor, the first transistor, the second transistor, the sixth transistor, and the seventh transistor are located on the other side of the third transistor, and the third transistor, the fourth transistor, and the ninth transistor are located between the fifth transistor and the sixth transistor.

[0028] In an exemplary embodiment, the first type of transistor further includes a first transistor as a reset transistor, and the second type of transistor further includes a second transistor as a compensation transistor.

[0029] The second terminal of the first transistor and the first terminal of the second transistor are electrically connected to the control terminal of the third transistor and the second plate of the first capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor.

[0030] In an exemplary embodiment, the pixel driving circuit further includes an eleventh transistor, a first transistor serving as a reset transistor, and a second transistor serving as a compensation transistor.

[0031] The first terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second plate of the first capacitor, and the first plate of the second capacitor. The second terminal of the eleventh transistor is electrically connected to the first terminal of the second transistor. The second terminal of the second transistor is electrically connected to the second terminal of the first transistor and the second terminal of the third transistor.

[0032] In an exemplary embodiment, the pixel driving circuit further includes an eleventh transistor, a first transistor serving as a reset transistor, and a second transistor serving as a compensation transistor.

[0033] The first terminal of the eleventh transistor is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor. The second terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second plate of the first capacitor, and the first plate of the second capacitor. The second terminal of the second transistor is electrically connected to the second terminal of the third transistor.

[0034] In an exemplary embodiment, the pixel driving circuit further includes at least one capacitor, the at least one capacitor including a first capacitor;

[0035] The first plate of the first capacitor is electrically connected to the data writing node, the second plate of the first capacitor is electrically connected to the first electrode of the tenth transistor, and the second electrode of the tenth transistor is electrically connected to the control electrode of the third transistor.

[0036] In an exemplary embodiment, the at least one capacitor further includes a second capacitor, the first plate of which is electrically connected to the control electrode of the third transistor and the second electrode of the tenth transistor.

[0037] In an exemplary embodiment, the pixel driving circuit further includes a first transistor as a reset transistor and a second transistor as a compensation transistor.

[0038] The second terminal of the first transistor is electrically connected to the second terminal of the second transistor and the second terminal of the third transistor, and the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor; or, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor.

[0039] In an exemplary embodiment, the pixel driving circuit further includes an eleventh transistor, a first transistor serving as a reset transistor, and a second transistor serving as a compensation transistor.

[0040] The first terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor. The second terminal of the eleventh transistor is electrically connected to the first terminal of the second transistor. The second terminal of the second transistor is electrically connected to the second terminal of the first transistor and the second terminal of the third transistor.

[0041] In an exemplary embodiment, the pixel driving circuit further includes an eleventh transistor, a first transistor serving as a reset transistor, and a second transistor serving as a compensation transistor.

[0042] The first terminal of the eleventh transistor is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor. The second terminal of the eleventh transistor is electrically connected to the first plate of the second capacitor, the control terminal of the third transistor, and the second terminal of the tenth transistor. The second terminal of the second transistor is electrically connected to the second terminal of the third transistor.

[0043] In an exemplary embodiment, the at least one capacitor further includes a second capacitor, and the pixel driving circuit further includes a first transistor as a reset transistor and a second transistor as a compensation transistor.

[0044] The second terminal of the first transistor is electrically connected to the second terminal of the second transistor and the second terminal of the third transistor, and the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor; or, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor.

[0045] In an exemplary embodiment, the at least one capacitor further includes a second capacitor, and the pixel driving circuit further includes an eleventh transistor, a first transistor as a reset transistor, and a second transistor as a compensation transistor.

[0046] The first terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor; the second terminal of the eleventh transistor is electrically connected to the first terminal of the second transistor; and the second terminal of the second transistor is electrically connected to the second terminal of the first transistor and the second terminal of the third transistor. Alternatively, the first terminal of the eleventh transistor is electrically connected to the second terminals of the first transistor and the first terminal of the second transistor; the second terminal of the eleventh transistor is electrically connected to the first plate of the second capacitor, the control terminal of the third transistor, and the second terminal of the tenth transistor; and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor.

[0047] In an exemplary embodiment, the display substrate further includes a fourth reset control line, and the control electrode of the tenth transistor and the control electrode of the eleventh transistor are electrically connected to the fourth reset control line.

[0048] In an exemplary embodiment, the tenth transistor and the eleventh transistor are second-type transistors, the first transistor is a first-type transistor, and the second transistor is either a first-type transistor or a second-type transistor.

[0049] Secondly, embodiments of this disclosure also provide a display device, including the display substrate described in any of the above embodiments.

[0050] Thirdly, embodiments of this disclosure provide a method for operating a display substrate, the display substrate including a plurality of sub-pixels, at least some of the sub-pixels including pixel driving circuits, at least one of the pixel driving circuits including a driving sub-circuit, an isolation sub-circuit, an isolation control terminal, and a data writing node, the driving sub-circuit including a driving control terminal; in the same pixel driving circuit, the isolation control terminal is electrically connected to the isolation sub-circuit, the isolation sub-circuit being disposed between the data writing node and the driving control terminal; the method of operation includes:

[0051] Under the control of the isolation control terminal, the isolation sub-circuit writes the signal of the data writing node to the drive control terminal.

[0052] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0053] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0054] Figure 1 is a schematic diagram of a display device;

[0055] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0056] Figure 3 is a schematic cross-sectional view of a display substrate;

[0057] Figure 4 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0058] Figure 5a shows an equivalent circuit diagram of the pixel driving circuit provided in an exemplary embodiment of the present disclosure;

[0059] Figure 5b shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure;

[0060] Figure 5c shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure;

[0061] Figure 5d shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure;

[0062] Figure 5e shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure;

[0063] Figure 5f shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure;

[0064] Figure 5g shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure;

[0065] Figure 5h shows an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure;

[0066] Figure 6 is a plan view of a display substrate provided in an exemplary embodiment of the present disclosure;

[0067] Figure 7a shows an equivalent circuit diagram of a pixel driving circuit.

[0068] Figure 7b is a timing diagram of one operation of the pixel driving circuit in Figure 7a;

[0069] Figure 8 is a planar schematic diagram of a display substrate after a shielding layer has been formed, according to an exemplary embodiment of the present disclosure.

[0070] Figure 9a is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0071] Figure 9b is a schematic diagram of the first semiconductor layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0072] Figure 10a is a schematic diagram of a display substrate after the formation of a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0073] Figure 10b is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0074] Figure 11a is a schematic diagram of a display substrate after the formation of the second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0075] Figure 11b is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0076] Figure 12a is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0077] Figure 12b is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0078] Figure 13a is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0079] Figure 13b is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0080] Figure 14 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0081] Figure 15a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0082] Figure 15b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0083] Figure 16 is a schematic diagram of a display substrate after a first planarization layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0084] Figure 17a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0085] Figure 17b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0086] Figure 18 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0087] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0088] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0089] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0090] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0091] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0092] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0093] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0094] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0095] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0096] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0097] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0098] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0099] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0100] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a circuit unit and a light-emitting unit. The circuit unit may include a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0101] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular pattern.

[0102] In another exemplary embodiment, the pixel unit P may include four sub-pixels, which may be arranged in a horizontal, vertical, diamond, or square manner, etc., and this disclosure does not limit the arrangement.

[0103] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0104] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 (which can be referred to as the circuit structure layer) for each sub-pixel can include multiple circuit units. Each circuit unit can include a pixel driving circuit composed of multiple transistors and a storage capacitor. Figure 3 illustrates a pixel driving circuit comprising only one driving transistor and one storage capacitor. The light-emitting structure layer 103 for each sub-pixel can include multiple light-emitting units. Each light-emitting unit can include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode of the driving transistor through a via. The organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, while the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer 103.

[0105] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, electron injection layer, hole transport layer, electron transport layer, hole blocking layer, and electron blocking layer of all light-emitting units may be a common layer connected together, and the light-emitting layers of adjacent light-emitting units may have a small amount of overlap, or may be isolated.

[0106] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 4, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to nine signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, light emission signal line E, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS).

[0107] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C. The third node N3 is connected to the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0108] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0109] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the initial signal line Vinit1, and the second terminal of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initial voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0110] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the scan signal line Gate, the second transistor T2 causes the control electrode of the third transistor T3 to connect to its second electrode.

[0111] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0112] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0113] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0114] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device EL. When the on-level scan signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0115] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0116] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0117] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0118] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0119] In an exemplary embodiment, taking an OLED where all seven transistors in the pixel driving circuit of Figure 4 are P-type transistors as an example, the operation of the pixel driving circuit may include:

[0120] The first stage, A1, is called the reset stage. The first reset control line, Reset1, is at a low level, while the scan signal line, Gate, and the light-emitting signal line, E, are at a high level. The low level of Reset1 turns on the first transistor T1, and the initial signal line, INIT, is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage within it. The high level of the scan signal line, Gate, the second reset control line, Reset2, and the light-emitting signal line, E, turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the OLED does not emit light.

[0121] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signals on the scan signal line Gate and the second reset control line Reset2 are low, while the signals on the first reset control line Reset1 and the light emission signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signals on the scan signal line Gate and the second reset control line Reset2 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal on the first reset control line Reset1 is a high-level signal, causing the first transistor T1 to turn off. The signal on the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0122] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the scan signal line Gate, the second reset control line Reset2, and the first reset control line Reset1 are at high levels. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0123] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0124] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0125] With the development of OLED display technology and the increasing demand for high-frequency and high-PPI displays, the pixel driving circuit of 7T1C shown in Figure 4 uses the data voltage output from the data signal line D for compensation. At higher refresh rates, there are insufficient threshold voltage (Vth) compensation and difficulties in writing low grayscale and black state data signals (or abnormal data signal writing).

[0126] An exemplary embodiment of this disclosure provides a display substrate, which may include a substrate and a plurality of sub-pixels disposed on one side of the substrate. At least some of the sub-pixels include pixel driving circuits. At least one pixel driving circuit includes a driving sub-circuit, an isolation sub-circuit, an isolation control terminal, and a data writing node. The driving sub-circuit includes a driving control terminal. In the same pixel driving circuit, the isolation control terminal is electrically connected to the isolation sub-circuit, and the isolation sub-circuit is disposed between the data writing node and the driving control terminal.

[0127] The isolation sub-circuit is configured to write the signal of the data writing node to the drive control terminal under the control of the isolation control terminal.

[0128] The display substrate provided in this embodiment has an isolation sub-circuit configured to write the signal of the data writing node to the driving control terminal under the control of the isolation control terminal, which to a certain extent solves the technical problem of difficulty in writing low grayscale or black state data signals.

[0129] As shown in Figures 5a to 5h, the display substrate may include a substrate and a plurality of sub-pixels disposed on one side of the substrate. At least some of the sub-pixels include pixel driving circuits. At least one pixel driving circuit includes a driving sub-circuit M01, an isolation sub-circuit M02, an isolation control terminal, and a data writing node N5. The driving sub-circuit M01 may include a driving control terminal. In the same pixel driving circuit, the isolation control terminal is electrically connected to the isolation sub-circuit M02. The isolation sub-circuit M02 may be disposed between the data writing node N5 and the driving control terminal.

[0130] The isolation sub-circuit M02 can be configured to write the signal for writing data to node N5 to the drive control terminal under the control of the isolation control terminal.

[0131] The technical solution provided in this disclosure embodiment includes an isolation sub-circuit M02 between the data writing node N5 and the drive control terminal, which can avoid abnormal data signal writing (reduce the problem of difficulty in writing low grayscale or black state data signals).

[0132] In an exemplary embodiment, the driving sub-circuit M01 may include a third transistor T3 as a driving transistor, and the blocking sub-circuit M02 may include a tenth transistor T10 as a blocking transistor. The control electrode of the third transistor T3 may serve as a driving control terminal, and the control electrode of the tenth transistor T10 may serve as a blocking control terminal.

[0133] In an exemplary embodiment, as shown in Figures 5a to 5d and 6, Figure 6 is a schematic diagram of a planar structure of the pixel driving circuit shown in Figure 5a. The pixel driving circuit may also include at least one capacitor, and the at least one capacitor may include a first capacitor C1.

[0134] The first terminal of the tenth transistor T10 can be electrically connected to the data write node N5, the second terminal of the tenth transistor T10 can be electrically connected to the first plate C11 of the first capacitor C1, and the second plate C12 of the first capacitor C1 can be electrically connected to the control terminal of the third transistor T3.

[0135] In an exemplary embodiment, as shown in Figures 5a to 5d and 6, at least one capacitor may further include a second capacitor C2, and the second plate C12 of the first capacitor C1 and the first plate of the second capacitor C2 may share a plate.

[0136] The second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can serve as the control electrode of the third transistor T3; the orthogonal projections of the first capacitor C1, the second capacitor C2 and the third transistor T3 on the substrate at least partially overlap, which can save space on the display substrate and increase the PPI of the display substrate.

[0137] In an exemplary embodiment, the fact that the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 share a single plate can reduce the space occupied by the pixel driving circuit and improve the pixel density (PPI) of the display substrate to a certain extent.

[0138] In an exemplary embodiment, as shown in Figures 5a to 5d and 6, the pixel driving circuit may include a plurality of transistors, which may include a first type of transistor and a second type of transistor. The first type of transistor may include a third transistor T3, and the second type of transistor may include a tenth transistor T10.

[0139] In a direction perpendicular to the plane of the substrate, the display substrate may include a shielding layer, an active layer of a first type of transistor, a control electrode of the first type of transistor, a second electrode plate C22 of a second capacitor C2, an active layer of a second type of transistor, a control electrode of a second type of transistor, and a first electrode and a second electrode of a plurality of transistors, which are sequentially disposed on one side of the substrate.

[0140] The first plate C11 of the first capacitor C1 can be located in the shielding layer, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be arranged in the same layer as the control electrode of the first type of transistor.

[0141] In an exemplary embodiment, the first type of transistor can be a P-type transistor, and the second type of transistor can be an N-type transistor.

[0142] In an exemplary embodiment, the orthographic projections of the first plate C11 of the first capacitor C1, the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 on the substrate at least partially overlap. Without changing the capacitance, the space occupied by the capacitor can be reduced, thereby increasing the pixel density (PPI) of the display substrate to a certain extent.

[0143] In an exemplary embodiment, as shown in FIG5a and FIG6, the first type of transistor may further include a first transistor T1 as a reset transistor, and the second type of transistor may further include a second transistor T2 as a compensation transistor.

[0144] The second terminal of the first transistor T1 and the second terminal of the second transistor T2 can be connected to the second terminal of the third transistor T3, and the first terminal of the second transistor T2 can be electrically connected to the control terminal of the third transistor T3.

[0145] In the same sub-pixel, the orthogonal projections of the first transistor T1 and the second transistor T2 onto the substrate at least partially overlap.

[0146] In an exemplary embodiment, the orthogonal projections of the first transistor T1 and the second transistor T2 on the substrate at least partially overlap. On the one hand, this can reduce the area occupied by the transistors and increase the PPI of the display substrate. On the other hand, the first transistor can shield the channel of the second transistor, thereby improving the stability of the second transistor T2.

[0147] In an exemplary embodiment, as shown in Figures 5a to 5d and Figure 6, the first type of transistor may further include a fourth transistor T4 as a data writing transistor and a ninth transistor T9 as a reset transistor, wherein the second terminal of the fourth transistor T4 and the second terminal of the ninth transistor T9 may be electrically connected to the data writing node N5.

[0148] In an exemplary embodiment, as shown in FIG5a and FIG6, the display substrate may further include a first light-emitting control line EM1, a second light-emitting control line EM2 and a first power line VDD. The first light-emitting control line EM1 and the second light-emitting control line EM2 may be disposed on the same layer as the control electrode of the first type of transistor, and the first power line VDD may be located on the side of the first electrode and the second electrode of the plurality of transistors away from the substrate.

[0149] The first type of transistor may also include a fifth transistor T5 as a first light-emitting control transistor and a sixth transistor T6 as a second light-emitting control transistor. The first terminal of the fifth transistor T5 and the second plate C22 of the second capacitor C2 can be electrically connected to the first power line VDD. The second terminal of the fifth transistor T5 can be connected to the first terminal of the third transistor T3. The first terminal of the sixth transistor T6 can be electrically connected to the second terminal of the third transistor T3, the second terminal of the first transistor T1, and the second terminal of the second transistor T2.

[0150] The region where the first light-emitting control line EM1 overlaps with the active layer of the fifth transistor T5 can be used as the control electrode of the fifth transistor T5; the region where the first light-emitting control line EM1 overlaps with the active layer of the ninth transistor T9 can be used as the control electrode of the ninth transistor T9; and the region where the second light-emitting control line EM2 overlaps with the active layer of the sixth transistor T6 can be used as the control electrode of the sixth transistor T6.

[0151] In a plane parallel to the substrate, the first light-emitting control line EM1 and the second light-emitting control line EM2 can extend along the first direction X, and the first power line VDD can extend along the second direction Y. The first direction X and the second direction Y intersect. In the same sub-pixel, in the second direction Y, the first light-emitting control line EM1 and the second light-emitting control line EM2 can be located on the same side of the third transistor T3, and the second light-emitting control line EM2 can be located on the side of the first light-emitting control line EM1 away from the third transistor T3.

[0152] In an exemplary embodiment, in the same pixel driving circuit, the fifth transistor T5 and the ninth transistor T9 share a first light-emitting control line EM1, which can save space on the display substrate, increase the PPI of the display substrate, and reduce the number of gate driving circuits (GOA circuits), thus benefiting from narrower bezels.

[0153] In an exemplary embodiment, as shown in Figures 5a to 5d and Figure 6, the display substrate may further include a third reset control line Reset3, and the first type of transistor may further include a seventh transistor T7 as a reset transistor and an eighth transistor T8 as a reset transistor.

[0154] The third reset control line Reset3 can be set on the same layer as the control electrode of the first type of transistor. The third reset control line Reset3 can extend along the first direction X. In the same sub-pixel, in the second direction Y, the third reset control line Reset3 can be located on the side of the second light emission control line EM2 away from the third transistor T3.

[0155] The region where the third reset control line Reset3 overlaps with the active layer of the seventh transistor T7 can be used as the control electrode of the seventh transistor T7, and the region where the third reset control line Reset3 overlaps with the active layer of the eighth transistor T8 can be used as the control electrode of the eighth transistor T8.

[0156] In an exemplary embodiment, in the same pixel driving circuit, the seventh transistor T7 and the eighth transistor T8 share a third reset control line Reset3, which can save space on the display substrate, increase the PPI of the display substrate, and reduce the number of gate driving circuits (GOA circuits), thus benefiting from narrower bezels.

[0157] In an exemplary embodiment, as shown in FIG6, in the same pixel driving circuit, in the second direction Y, the tenth transistor T10 and the fourth transistor T4 can be located on opposite sides of the third transistor T3, the fifth transistor T5 and the ninth transistor T9 can be located on the side of the fourth transistor T4 away from the third transistor T3, the sixth transistor T6 can be located on the side of the fifth transistor T5 away from the fourth transistor T4, and the seventh transistor T7 and the eighth transistor can be located on the side of the sixth transistor T6 away from the fifth transistor T5; in the first direction X, the fifth transistor T5, the eighth transistor T8 and the tenth transistor T10 can be located on one side of the third transistor T3, the first transistor T1, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 can be located on the other side of the third transistor T3, and the third transistor T3, the fourth transistor T4 and the ninth transistor T9 are located between the fifth transistor T5 and the sixth transistor T6.

[0158] In an exemplary embodiment, as shown in FIG5b, the first type of transistor may further include a first transistor T1 as a reset transistor, and the second type of transistor may further include a second transistor T2 as a compensation transistor.

[0159] The second terminal of the first transistor T1 and the first terminal of the second transistor T2 can be electrically connected to the control terminal of the third transistor T3 and the second plate C12 of the first capacitor C1. The second terminal of the second transistor T2 can be connected to the second terminal of the third transistor T3.

[0160] In an exemplary embodiment, as shown in FIG5c, the pixel driving circuit may further include an eleventh transistor T11, a first transistor T1 serving as a reset transistor, and a second transistor T2 serving as a compensation transistor.

[0161] The first terminal of the eleventh transistor T11 can be electrically connected to the control terminal of the third transistor T3, the second plate C12 of the first capacitor C1, and the first plate C21 of the second capacitor C2. The second terminal of the eleventh transistor T11 can be electrically connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 can be electrically connected to the second terminal of the first transistor T1 and the second terminal of the third transistor T3.

[0162] In an exemplary embodiment, as shown in FIG5d, the pixel driving circuit may further include an eleventh transistor T11, a first transistor T1 serving as a reset transistor, and a second transistor T2 serving as a compensation transistor.

[0163] The first terminal of the eleventh transistor T11 can be electrically connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2. The second terminal of the eleventh transistor T11 can be electrically connected to the control terminal of the third transistor T3, the second plate C12 of the first capacitor C1, and the first plate C21 of the second capacitor C2. The second terminal of the second transistor T2 can be electrically connected to the second terminal of the third transistor T3.

[0164] In an exemplary embodiment, as shown in Figures 5e to 5h, the pixel driving circuit may further include at least one capacitor, and the at least one capacitor may include a first capacitor C1.

[0165] The first plate C11 of the first capacitor C1 can be electrically connected to the data writing node N5, the second plate C12 of the first capacitor C1 can be electrically connected to the first terminal of the tenth transistor T10, and the second terminal of the tenth transistor T10 can be electrically connected to the control terminal of the third transistor T3.

[0166] In an exemplary embodiment, as shown in Figures 5e to 5h, at least one capacitor may further include a second capacitor C2, the first plate C21 of the second capacitor C2 being electrically connected to the control electrode of the third transistor T3 and the second electrode of the tenth transistor T10.

[0167] In an exemplary embodiment, as shown in Figures 5e and 5f, the pixel driving circuit may further include a first transistor T1 as a reset transistor and a second transistor T2 as a compensation transistor.

[0168] As shown in Figure 5e, the second terminal of the first transistor T1 can be electrically connected to the second terminals of the second transistor T2 and the third transistor T3, and the first terminal of the second transistor T2 can be electrically connected to the control terminal of the third transistor T3, the second terminal of the tenth transistor T10, and the first plate C21 of the second capacitor C2; or, as shown in Figure 5f, the second terminal of the first transistor T1 can be electrically connected to the first terminal of the second transistor T2, the control terminal of the third transistor T3, the second terminal of the tenth transistor T10, and the first plate C21 of the second capacitor C2, and the second terminal of the second transistor T2 can be connected to the second terminal of the third transistor T3.

[0169] In an exemplary embodiment, as shown in FIG5g, the pixel driving circuit may further include an eleventh transistor T11, a first transistor T1 serving as a reset transistor, and a second transistor T2 serving as a compensation transistor.

[0170] The first terminal of the eleventh transistor T11 can be electrically connected to the control terminal of the third transistor T3, the second terminal of the tenth transistor T10, and the first plate C21 of the second capacitor C2. The second terminal of the eleventh transistor T11 can be electrically connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 can be electrically connected to the second terminal of the first transistor T1 and the second terminal of the third transistor T3.

[0171] In an exemplary embodiment, as shown in FIG5h, the pixel driving circuit may further include an eleventh transistor T11, a first transistor T1 serving as a reset transistor, and a second transistor T2 serving as a compensation transistor.

[0172] The first terminal of the eleventh transistor T11 can be electrically connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2. The second terminal of the eleventh transistor T11 can be electrically connected to the first plate C21 of the second capacitor C2, the control terminal of the third transistor T3, and the second terminal of the tenth transistor T10. The second terminal of the second transistor T2 can be electrically connected to the second terminal of the third transistor T3.

[0173] In an exemplary embodiment, as shown in Figures 5c, 5d, 5g, and 5h, the display substrate may further include a fourth reset control line, Reset4, with the control electrodes of the tenth transistor T10 and the eleventh transistor T11 electrically connected to the fourth reset control line, Reset4. In this exemplary embodiment, the tenth transistor T10 and the eleventh transistor T11 share a single fourth reset control line, Reset4, which can save space on the display substrate, increase the PPI of the display substrate, and reduce the number of gate drive circuits (GOA circuits), thus facilitating narrower bezels on the display substrate.

[0174] In an exemplary embodiment, as shown in Figures 5c to 5d and Figures 5g to 5h, the tenth transistor T10 and the eleventh transistor T11 can be second-type transistors, and the first transistor T1 can be a first-type transistor. In an exemplary embodiment, the second transistor T2 can be either a first-type transistor or a second-type transistor.

[0175] In an exemplary embodiment, the first type of transistor can be a P-type transistor, the second type of transistor can be an N-type transistor, and the transistor connected to the control electrode of the third transistor T3 is of the second type, which can reduce the leakage current of the second node N2. The eleventh transistor T11 and the tenth transistor T10 are N-type transistors. With the reduction of leakage current, the tenth transistor T10 and the eleventh transistor T11 can share a fourth reset control line Reset4, which can improve the PPI of the display substrate.

[0176] In an exemplary embodiment, the planar structure of the pixel driving circuit in FIG5a can be as shown in FIG6. In the structures shown in FIG5a and FIG6, the tenth transistor T10 can be located between the data writing node N5 (i.e. the fifth node N5) and the first capacitor C1. The second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can share a plate, which greatly reduces the space occupied by the capacitor on the display substrate. With the capacitance unchanged, the size of the pixel driving circuit of a sub-pixel along the second direction Y is reduced, which can improve the PPI of the display substrate. In a structure where the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 share a single plate (as shown in Figures 5a and 6), the PPI of the display substrate can reach 400 to 500 (e.g., 423), and the size of the pixel driving circuit of a sub-pixel along the second direction Y is approximately 50 to 70 micrometers (e.g., approximately 60 micrometers). In a structure where the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 do not share a single plate (e.g., using the pixel driving circuit shown in Figure 5e), the PPI of the display substrate is typically 380 to 400 (e.g., 391), and the size of the pixel driving circuit of a sub-pixel along the second direction Y is approximately 60 to 80 micrometers (e.g., approximately 65 micrometers).

[0177] In an exemplary embodiment, the pixel driving circuit shown in Figures 5a to 6 can, to a certain extent, avoid the occurrence of writing failures or abnormalities in low grayscale or black state data signals (i.e., data voltage). Using the pixel driving circuit shown in Figure 7a (without the isolation sub-circuit M02), the operating timing of Figure 7a is shown in Figure 7b. The operating timing shown in Figure 7b can include four stages: reset stage S1, compensation stage S2, writing stage S3, and light emission stage S4. In the data writing stage, the signal from the scan signal line Gate controls the fourth transistor T4 to turn on, and the data signal is written to the data writing node N5. The voltage of the data writing node N5 changes from Vref1 to Vdata. After coupling to the second node N2, the voltage of the second node N2 becomes Vdata. Therefore, the voltage change of the second node N2 is Vdata - Vref1. After the data signal is written, the third light emission control line EM3 controls the ninth transistor T9 to turn on, and the voltage of the fifth node N5 changes from Vdata to Vref1. After coupling to the second node N2, the voltage of the second node N2 becomes Vdata - Vref1. If ref1 is written, the voltage change of the second node N2 is Vref1 - Vdata. The sum of the two voltage changes of the second node N2 is (Vdata - Vref1) + (Vref1 - Vdata) = 0, which means that the voltage change of the second node N2 after the data signal is written and before the writing is 0, and the data signal writing fails. In contrast, in the technical solution provided by the embodiments of this disclosure, an isolation sub-circuit M02 is set between the second node N2 and the fifth node N5, which can avoid the occurrence of data signal writing failure. For example, after the data voltage Vdata is written to the second node N2, when the ninth transistor T9 is turned on, the tenth transistor T10 can be turned off by the fourth reset control line Reset4, thereby avoiding data signal writing failure. At high refresh frequency, low grayscale and black state data signals can be successfully written to the second node N2 (i.e., the control electrode of the driving transistor T3).

[0178] The pixel driving circuit provided in this embodiment operates with a compensation phase and a writing phase that are independent of each other. In the writing phase, the data writing transistor T4 writes data voltage, and in the compensation phase, the compensation transistor T2 performs threshold voltage compensation. This makes the threshold voltage compensation no longer limited by the cycle time. The threshold voltage compensation and data writing are separated from each other, which can realize high-frequency driving display and overcome the problem of insufficient threshold voltage compensation at high refresh rates to a certain extent.

[0179] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0180] In an exemplary embodiment, taking four sub-pixels (1 sub-pixel row and 4 sub-pixel columns) in the display area (AA) as an example, the fabrication process of one display substrate may include the following operations.

[0181] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0182] (102) Forming a masking layer pattern. In an exemplary embodiment, forming a masking layer pattern may include: depositing a conductive thin film of the masking layer on a substrate, patterning the conductive thin film of the masking layer by a patterning process, and forming a masking layer pattern on the substrate, as shown in FIG8, FIG8 is a planar structural diagram of the masking layer pattern in four sub-pixels.

[0183] In an exemplary embodiment, the occlusion layer pattern of at least some sub-pixels may include: the first plate C11 of the first capacitor.

[0184] In an exemplary embodiment, the outline of the first plate C11 of the first capacitor can be rectangular, the corners of the rectangle can be chamfered, and the edge of the rectangle can be a broken line or a straight line.

[0185] In an exemplary embodiment, the first plate C11 of the first capacitor C1 is provided with a first connection portion CL1. The first connection portion CL1 is configured to accommodate a subsequently formed nineteenth via. The orthographic projection of the nineteenth via on the substrate is within the range of the orthographic projection of the first connection portion CL1 on the substrate, and exposes the surface of the first connection portion CL1, so that the second electrode of the subsequently formed tenth transistor T10 is connected to the first plate C11 of the first capacitor C1 through the nineteenth via and the first connection portion CL1.

[0186] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the masking layer pattern, and a semiconductor layer pattern disposed on the first insulating layer, as shown in Figures 9a and 9b. Figure 9a shows a planar schematic diagram of four sub-pixels after forming a semiconductor layer, and Figure 9b shows a planar structural schematic diagram of the first semiconductor layer of three sub-pixels.

[0187] In an exemplary embodiment, the first semiconductor layer pattern in at least some of the sub-pixels includes at least: the active layer AT1 of the first transistor T1, the active layer AT3 of the third transistor T3 to the active layer AT9 of the ninth transistor T9.

[0188] In an exemplary embodiment, within the same sub-pixel, the active layer AT3 of the third transistor T3 and the active layer AT1 of the first transistor T1 can be interconnected, the active layer AT4 of the fourth transistor T4 and the active layer AT9 of the ninth transistor T9 can be interconnected, and the active layer AT6 of the sixth transistor T6 and the active layer AT7 of the seventh transistor T7 can be interconnected. For example, the active layer AT3 of the third transistor T3 and the active layer AT1 of the first transistor T1 can be an integral structure interconnected, the active layer AT4 of the fourth transistor T4 and the active layer AT9 of the ninth transistor T9 can be an integral structure interconnected, and the active layer AT6 of the sixth transistor T6 and the active layer AT7 of the seventh transistor T7 can be an integral structure interconnected.

[0189] In an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer AT1 of the first transistor T1, the active layer AT6 of the sixth transistor T6, and the active layer AT7 of the seventh transistor T7 can be located on the same side of the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, and the active layer AT9 of the ninth transistor T9, while the active layer AT5 of the fifth transistor T5 can be located on the other side of the active layers AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, and the active layer AT9 of the ninth transistor T9; in the second direction Y, the active layers AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, the active layer AT6 of the sixth transistor T6, the active layer AT7 of the seventh transistor T7, the active layer AT8 of the eighth transistor T8, and the active layer AT9 of the ninth transistor T9 are located on the same side of the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, the active layer AT6 of the sixth transistor T6, the active layer AT7 of the seventh transistor T7, the active layer AT8 of the eighth transistor T8, and the active layer AT9 of the ninth transistor T9 are located on the same side of the active layer AT4 of the ninth transistor T5. AT9 can be located on the same side of the active layer AT3 of the third transistor T3. The active layer AT1 of the first transistor T1 can be located on the other side of the active layer AT3 of the third transistor T3. The active layer AT9 of the ninth transistor T9 can be located on the side of the active layer AT4 of the fourth transistor T4 away from the active layer AT3 of the third transistor T3. The active layer AT8 of the eighth transistor T8 can be located on the side of the active layer AT5 of the fifth transistor T5 and the active layer AT9 of the ninth transistor T9 away from the active layer AT3 of the third transistor T3. The active layer AT6 of the sixth transistor T6 can be located on the side of the active layer AT4 of the fourth transistor T4 away from the active layer AT3 of the third transistor T3. The active layer AT7 of the seventh transistor T7 can be located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT3 of the third transistor T3.

[0190] In an exemplary embodiment, taking the sub-pixel at the M-th row and the N-th column as an example: in the first direction X, the active layers AT1 of the first transistor T1, the active layers AT6 of the sixth transistor T6, and the active layers AT7 of the seventh transistor T7 can be located on the side of the active layers AT3 of the third transistor T3, the active layers AT4 of the fourth transistor T4, and the active layers AT9 of the ninth transistor T9 closer to the sub-pixel in the (N + 1)-th column, and the active layers AT5 of the fifth transistor T5 can be located on the side of the active layers AT3 of the third transistor T3, the active layers AT4 of the fourth transistor T4, and the active layers AT9 of the ninth transistor T9 farther from the sub-pixel in the (N + 1)-th column; in the second direction Y, the active layers AT4 of the fourth transistor T4, the active layers AT5 of the fifth transistor T5, the active layers AT6 of the sixth transistor T6, the active layers AT7 of the seventh transistor T7, the active layers AT8 of the eighth transistor T8, and the active layers AT9 of the ninth transistor T9 can be located on the side of the active layers AT3 of the third transistor T3 closer to the sub-pixel in the (M + 1)-th row, the active layers AT1 of the first transistor T1 can be located on the side of the active layers AT3 of the third transistor T3 farther from the sub-pixel in the (M + 1)-th row, the active layers AT9 of the ninth transistor T9 can be located on the side of the active layers AT4 of the fourth transistor T4 closer to the sub-pixel in the (M + 1)-th row, the active layers AT8 of the eighth transistor T8 can be located on the side of the active layers AT5 of the fifth transistor T5 and the active layers AT9 of the ninth transistor T9 closer to the sub-pixel in the (M + 1)-th row, the active layers AT6 of the sixth transistor T6 can be located on the side of the active layers AT4 of the fourth transistor T4 closer to the sub-pixel in the (M + 1)-th row, and the active layers AT7 of the seventh transistor T7 can be located on the side of the active layers AT6 of the sixth transistor T6 closer to the sub-pixel in the (M + 1)-th row.

[0191] In an exemplary embodiment, the shape of the active layer AT1 of the first transistor T1 can be in an "I" shape or a bar shape, the shape of the active layer 23 of the third transistor T3 can be in an "Ω" shape or a "ji" shape, the shapes of the active layers AT4 of the fourth transistor T4, the active layers AT5 of the fifth transistor T5, the active layers AT6 of the sixth transistor T6, the active layers AT7 of the seventh transistor T7, the active layers AT8 of the eighth transistor T8, and the active layers AT9 of the ninth transistor T9 can be in an "L" shape, and in the same sub-pixel, the shape of the connection between the active layer AT4 of the fourth transistor T4 and the active layer AT9 of the ninth transistor T9 is approximately in an "F" shape.

[0192] In an exemplary embodiment, the active layer AT7 of the seventh transistor T7 in the Nth column of sub-pixels is interconnected with the active layer AT7 of the seventh transistor T7 in the (N + 1)th column of sub-pixels; the active layer AT5 of the fifth transistor T5 in the (N + 1)th column and the (N + 2)th column of sub-pixels is interconnected, forming a substantially "Ω" shape or a "ji" shape; the active layer AT8 of the eighth transistor T8 in the (N + 1)th column and the (N + 2)th column of sub-pixels is interconnected, forming a substantially "π" shape rotated 180°.

[0193] In an exemplary embodiment, the active layer of at least some of the transistors may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region AT32 of the active layer AT3 of the third transistor T3 may serve as the second region AT12 of the active layer AT1 of the first transistor T1, the second region AT42 of the active layer AT4 of the fourth transistor T4 may serve as the second region AT92 of the active layer AT9 of the ninth transistor T9, the second region AT62 of the active layer AT6 of the sixth transistor T6 may serve as the second region AT72 of the active layer AT7 of the seventh transistor T7, and the first regions AT11 of the active layer AT1 of the first transistor T1, the first region AT31 of the active layer AT3 of the third transistor T3, the first region AT41 of the active layer AT4 of the fourth transistor T4, the first region AT51 of the active layer AT5 of the fifth transistor T5 and the second region AT52, the first region AT61 of the active layer AT6 of the sixth transistor T6, the first region AT71 of the active layer AT7 of the seventh transistor T7, the first region AT81 and the second region AT82 of the active layer AT8 of the eighth transistor T8, and the first region AT91 of the active layer AT9 of the ninth transistor T9 may be provided separately.

[0194] In an exemplary embodiment, within the same sub-pixel, the orthographic projection of the active layer AT3 of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C11 of the first capacitor C1 on the substrate. For example, the orthographic projection of the channel region of the active layer AT3 of the third transistor T3 on the substrate may be located within the range of the orthographic projection of the first electrode plate C11 of the first capacitor C1 on the substrate.

[0195] In an exemplary embodiment, the first semiconductor layer in column N and the first semiconductor layer in column N+1 may be mirror-symmetrical with respect to the first center line, the first semiconductor layer in column N+1 and the first semiconductor layer in column N+2 may be mirror-symmetrical with respect to the second center line, and the first semiconductor layer in column N+2 and the first semiconductor layer in column N+3 may be mirror-symmetrical with respect to the third center line. The first center line, the second center line, and the third center line may each be a straight line extending along the second direction Y between adjacent sub-pixel columns. For example, the first center line may be a straight line extending along the second direction Y between sub-pixels in columns N and N+1, the second center line may be a straight line extending along the second direction Y between sub-pixels in columns N+1 and N+2, and the third center line may be a straight line extending along the second direction Y between sub-pixels in columns N+2 and N+3.

[0196] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning that the first transistor T1 and the third transistors T3 through T9 may be LTPS thin-film transistors. In another exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; then performing a hydrogen removal treatment on the amorphous silicon thin film; and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0197] (104) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 10a and 10b. Figure 10a shows a planar schematic diagram of the first conductive layer formed by four sub-pixels, and Figure 10b is a planar schematic diagram of the first conductive layer in Figure 10a. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0198] In an exemplary embodiment, the first conductive layer pattern may include at least: a first reset control line Reset1, a second electrode C12 of a first capacitor C1, a scan signal line Gate, a first light emission control line EM1, a second light emission control line EM2, and a third reset control line Reset3. The main body portions of the first reset control line Reset1, the scan signal line Gate, the first light emission control line EM1, the second light emission control line EM2, and the third reset control line Reset3 may extend along a first direction X; in the same row of sub-pixels, in the opposite direction of the second direction Y, the first reset control line Reset1, the scan signal line Gate, the first light emission control line EM1, the second light emission control line EM2, and the third reset control line Reset3 are arranged sequentially, and in the same sub-pixel, the second electrode C12 of the first capacitor C1 is located between the first reset control line Reset1 and the scan signal line Gate.

[0199] In an exemplary embodiment, the outline of the second plate C12 of the first capacitor C1 can be rectangular, with chamfered corners and the edges of the rectangle can be either broken lines or straight lines. The orthographic projection of the second plate C12 onto the substrate overlaps with the orthographic projection of the first plate C11 onto the substrate. The first plate C11 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1 of the pixel driving circuit. In an exemplary embodiment, the first plate C11 can serve as the control electrode of the third transistor T3 and the first plate C21 of the second capacitor. The second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 share a single plate.

[0200] In an exemplary embodiment, the region where the first reset control line Reset1 overlaps with the active layer AT1 of the first transistor T1 can serve as the control electrode of the first transistor T1; the region where the scan signal line Gate overlaps with the active layer AT4 of the fourth transistor T4 can serve as the control electrode of the fourth transistor T4; the region where the first light emission control line EM1 overlaps with the active layer of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5; the region where the first light emission control line EM1 overlaps with the active layer of the ninth transistor T9 can serve as the control electrode of the ninth transistor T9; the region where the second light emission control line EM2 overlaps with the active layer of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6; the region where the third reset control line Reset3 overlaps with the active layer of the seventh transistor T7 can serve as the control electrode of the seventh transistor T7; and the region where the third reset control line Reset3 overlaps with the active layer of the eighth transistor T8 can serve as the control electrode of the eighth transistor T8.

[0201] In an exemplary embodiment, the first conductive layer in column N and the first conductive layer in column N+1 may be mirror-symmetrical with respect to the first center line, the first conductive layer in column N+1 and the first conductive layer in column N+2 may be mirror-symmetrical with respect to the second center line, and the first conductive layer in column N+2 and the first conductive layer in column N+3 may be mirror-symmetrical with respect to the third center line.

[0202] In an exemplary embodiment, the first light-emitting control line EM1 and the second light-emitting control line EM2 can be designed with equal width or with non-equal width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines.

[0203] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3 to the ninth transistor T9. The first semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first region and the second region of the active layer AT1 of the first transistor T1, the active layer AT3 of the third transistor T3 to the active layer AT9 of the ninth transistor T9 are all conducted.

[0204] (105) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 11a and 11b. Figure 11a is a planar structural diagram of four columns of sub-pixels (i.e., four sub-pixels) in a row of sub-pixels, and Figure 11b is a planar schematic diagram of the second conductive layer in Figure 11a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0205] In an exemplary embodiment, the second conductive layer pattern includes at least: the second electrode C22 of the second capacitor C2 and the connection structure Vref2M of the second reference signal line. In the second direction Y, within the same sub-pixel, the connection structure Vref2M of the second reference signal line is located on one side of the second electrode C22 of the second capacitor C2. Taking the Mth row sub-pixel as an example: the connection structure Vref2M of the second reference signal line is located on the side of the second electrode C22 of the second capacitor C2 near the (M+1)th row sub-pixel.

[0206] In an exemplary embodiment, in the same sub-pixel row, the second plates C22 of two adjacent second capacitors C2 are connected to each other, so that the second plates C22 of multiple second capacitors C2 located in the same sub-pixel row have approximately the same potential. This can ensure that the second plates of the storage capacitors of adjacent sub-pixels have the same potential, which is beneficial to improve the uniformity of the panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0207] In an exemplary embodiment, the outline of the second electrode C22 of the second capacitor C2 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode C22 on the substrate overlaps with the orthographic projection of the first electrode C21 on the substrate. The first electrode C21 and the second electrode C22 constitute the second capacitor C2 of the pixel driving circuit. An opening K0 is provided on the second electrode C22, which can be located in the middle of the second electrode C22. The opening K0 can be rectangular, so that the second electrode C22 forms a ring structure. The opening K0 exposes the third insulating layer covering the first electrode C21, and the orthographic projection of the first electrode C21 on the substrate includes the orthographic projection of the opening K0 on the substrate. In an exemplary embodiment, the opening K0 is configured to accommodate a subsequently formed twentieth via. The twentieth via is located in the opening K0 and exposes the first electrode C21, so that the first electrode of the subsequently formed second transistor T2 is connected to the first electrode C21 of the second capacitor C2.

[0208] In an exemplary embodiment, within the same row of sub-pixels, the connection structure Vref2M of the second reference signal line is configured as the first region of the active layer connecting two adjacent eighth transistors T8.

[0209] In an exemplary embodiment, the second conductive layer in the Nth column and the second conductive layer in the N+1th column can be mirror-symmetrical with respect to the second center line, the second conductive layer in the N+1th column and the second conductive layer in the N+2th column can be mirror-symmetrical with respect to the second center line, and the second conductive layer in the N+2th column and the second conductive layer in the N+3th column can be mirror-symmetrical with respect to the third center line.

[0210] (106) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on a substrate on which the aforementioned pattern is formed, patterning the second semiconductor film by a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in Figures 12a and 12b. Figure 12a is a planar structural diagram of four sub-pixels after the formation of the second semiconductor layer, and Figure 12b is a planar schematic diagram of the second semiconductor layer in Figure 12a.

[0211] In an exemplary embodiment, the second semiconductor layer pattern in at least some of the sub-pixels includes at least: the active layer AT2 of the second transistor T2 and the active layer AT10 of the tenth transistor T10.

[0212] In an exemplary embodiment, the active layer AT2 of the second transistor T2 can be I-shaped, or it can be a strip extending along the second direction Y. The first region AT21 and the second region AT22 of the active layer AT2 of the second transistor T2 can be set separately. In the same sub-pixel, the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate can at least partially overlap with the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The active layer AT2 of the second transistor T2 and the active layer AT1 of the first transistor T1 are located on the same side of the active layer AT3 of the third transistor T3.

[0213] In an exemplary embodiment, the active layer AT10 of the tenth transistor T10 can be shaped like an "n" or a "7", and the first region AT101 and the second region AT102 of the active layer AT10 of the tenth transistor T10 can be set separately.

[0214] In an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer AT10 of the tenth transistor T10 may be located on one side of the active layer AT2 of the second transistor T2; for example, within the same sub-pixel, the active layer AT10 of the tenth transistor T10 and the active layer AT2 of the second transistor T2 may be arranged at intervals along the first direction X. Within the same sub-pixel, in the second direction Y, the active layer AT10 of the tenth transistor T10 may be located on the same side as the active layer AT2 of the second transistor T2, which is located on the same side as the active layer AT3 of the third transistor T3. The active layer AT2 of the second transistor T2 is located on the side of the active layer AT3 of the third transistor T3 that is away from the active layer AT6 of the sixth transistor T6, and the active layer AT10 of the tenth transistor T10 may be located on the side of the active layer AT3 of the third transistor T3 that is away from the active layer AT5 of the fifth transistor T5.

[0215] In an exemplary embodiment, the second semiconductor layer in column N and the second semiconductor layer in column N+1 may be mirror-symmetric with respect to the first center line, the second semiconductor layer in column N+1 and the second semiconductor layer in column N+2 may be mirror-symmetric with respect to the second center line, and the second semiconductor layer in column N+2 and the second semiconductor layer in column N+3 may be mirror-symmetric with respect to the third center line.

[0216] In an exemplary embodiment, the second semiconductor layer may be an oxide, i.e., the second transistor T2 and the tenth transistor T10 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of IGZO TFT is relatively small, the second transistor T2 is an N-type transistor, which can avoid leakage of the second node N2 during the light-emitting stage.

[0217] (107) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the fifth insulating layer, as shown in Figures 13a and 13b. Figure 13a is a planar structural diagram of four sub-pixels after the formation of the third conductive layer, and Figure 13b is a planar schematic diagram of the third conductive layer in Figure 13a. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0218] In an exemplary embodiment, the third conductive layer pattern includes at least: a second initial signal line Vinit2, a first reference signal line Vref1, a fourth reset control line Reset4, and a second reset control line Reset2.

[0219] In an exemplary embodiment, the main body of the second initial signal line Vinit2, the first reference signal line Vref1, the fourth reset control line Reset4, and the second reset control line Reset2 can be a strip-shaped structure or a broken line structure extending along the first direction X; in the same row of sub-pixels, the second initial signal line Vinit2, the first reference signal line Vref1, the fourth reset control line Reset4, and the second reset control line Reset2 can be arranged sequentially at intervals along the second direction Y.

[0220] In an exemplary embodiment, within the same row of sub-pixels, in the second direction Y, the second initial signal line Vinit2 and the first reference signal line Vref1 can be located on one side of the first capacitor C1 and the second capacitor C2, while the fourth reset control line Reset4 and the second reset control line Reset2 can be located on the other side of the first capacitor C1 and the second capacitor C2. The second initial signal line Vinit2, the first reference signal line Vref1, and the sixth transistor T5 are located on the same side of the third transistor T3, and the second reset control line Reset2 and the tenth transistor T10 are located on the same side of the third transistor T3. The orthographic projection of the second initial signal line Vinit2 on the substrate at least partially overlaps with the orthographic projection of the third reset control line Reset3 on the substrate, which can save space and improve the PPI of the display substrate. The orthographic projections of the second initial signal line Vinit2, the first reference signal line Vref1, the fourth reset control line Reset4, and the second reset control line Reset2 on the substrate do not overlap with the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate.

[0221] In an exemplary embodiment, within the same row of sub-pixels, a first bending structure ZL1 and a second bending structure ZL2 can be provided on the fourth reset control line Reset4. The first bending structure ZL1 can be bent towards the second reset control line Reset2, bypassing the first capacitor C1 and the second capacitor C2, and at least partially overlapping with the active layer of the tenth transistor T10. The second bending structure ZL2 can be bent away from the second transistor T2, bypassing the second transistor T2, thereby preventing the fourth reset control line Reset4 from causing signal interference to the second transistor T2, the first capacitor C1, and the second capacitor C2.

[0222] In an exemplary embodiment, within the same row of sub-pixels, a third bending structure ZL3 and a fourth bending structure ZL4 can be provided on the second reset control line Reset2. The third bending structure ZL3 can be bent away from the fourth reset control line Reset4, bypassing the first bending structure ZL1, the tenth transistor T10, the first capacitor C1, and the second capacitor C2 in the fourth reset control line Reset4, thereby preventing the second reset control line Reset2 from causing signal interference to the tenth transistor T10, the first capacitor C1, and the second capacitor C2. The fourth bending structure ZL4 can be bent towards the second transistor T2 and at least partially overlap with the active layer of the second transistor T2.

[0223] In an exemplary embodiment, the region where the second reset control line Reset2 (such as the fourth bent structure ZL4) overlaps with the active layer AT2 of the second transistor T2 can be used as the control electrode of the second transistor T2, and the region where the fourth reset control line Reset4 (such as the first bent structure ZL1) overlaps with the active layer AT10 of the tenth transistor T10 can be used as the control electrode of the tenth transistor T10.

[0224] In an exemplary embodiment, the orthographic projection of the second initial signal line Vinit2 on the substrate at least partially overlaps with the orthographic projection of the third reset control line Reset3 on the substrate, and the orthographic projection of the first reference signal line Vref1 on the substrate at least partially overlaps with the orthographic projection of the first light emission control line on the substrate, which can save space occupied by pixel driving and provide pixel density (PPI) of the display substrate.

[0225] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer. The sixth insulating layer has a plurality of vias, as shown in FIG14, FIG14 being a planar structural diagram of four sub-pixels after the formation of the sixth insulating layer.

[0226] In an exemplary embodiment, at least some of the vias in the sub-pixels include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, and a twenty-fourth via V24.

[0227] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0228] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the second region AT2 of the active layer AT1 of the first transistor T1 (which is also the second region AT32 of the active layer AT3 of the third transistor T3). The second via V2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer AT1 of the first transistor T1 through the via, and to connect the second electrode of the subsequently formed third transistor T3 to the active layer AT3 of the third transistor T3 through the via.

[0229] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the third via V3 are etched away, exposing the surface of the second region AT2 of the active layer AT1 of the first transistor T1 (which is also the second region AT12 of the active layer AT1 of the first transistor T1). The third via V3 is configured to allow a subsequently formed second connection electrode to be connected to the active layers AT1 of the first transistor T1 and AT3 of the third transistor T3 through this via.

[0230] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the fourth via V4 are etched away, exposing the surface of the first region AT21 of the active layer AT2 of the second transistor T2. The fourth via V4 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the active layer AT2 of the second transistor T2 through the via.

[0231] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the fifth via V5 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2. The fifth via V5 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected to the active layer AT2 of the second transistor T2 through this via.

[0232] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the substrate lies within the orthogonal projection of the active layer AT3 of the third transistor T3 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3. The sixth via V6 is configured to allow the first electrode of the subsequently formed third transistor T3 to be connected to the active layer AT3 of the third transistor T3 through this via.

[0233] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate lies within the orthogonal projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the first region AT41 of the active layer AT4 of the fourth transistor T4. The seventh via V7 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0234] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT92 of the active layer AT9 of the ninth transistor T9). The eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor T4 to the active layer AT4 of the fourth transistor T4 through the via, and to connect the second electrode of the subsequently formed ninth transistor T9 to the active layer AT9 of the ninth transistor T9 through the via.

[0235] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the orthogonal projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The ninth via V9 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0236] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the substrate lies within the orthogonal projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the second region AT52 of the active layer AT5 of the fifth transistor T5. The tenth via V10 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0237] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first region AT61 of the active layer AT6 of the sixth transistor T6. The eleventh via V11 is configured to allow the first electrode of the subsequently formed sixth transistor T6 to be connected to the active layer AT6 of the sixth transistor T6 through this via.

[0238] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the orthographic projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7). The twelfth via V12 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via.

[0239] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the orthographic projection of the active layer AT7 of the seventh transistor T7 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first region AT71 of the active layer AT7 of the seventh transistor T7. The thirteenth via V13 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the active layer AT7 of the seventh transistor T7 through this via.

[0240] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the orthographic projection of the active layer AT8 of the eighth transistor T8 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first region AT81 of the active layer AT8 of the eighth transistor T8. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed eighth transistor T8 to be connected to the active layer AT8 of the eighth transistor T8 through this via.

[0241] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the active layer AT8 of the eighth transistor T8 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second region AT82 of the active layer AT8 of the eighth transistor T8. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed eighth transistor T8 to be connected to the active layer AT8 of the eighth transistor T8 through this via.

[0242] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the orthographic projection of the active layer AT9 of the ninth transistor T9 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the sixteenth via V16 are etched away, exposing the surface of the first region AT91 of the active layer AT9 of the ninth transistor T9. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed ninth transistor T9 to be connected to the active layer AT9 of the ninth transistor T9 through this via.

[0243] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate lies within the orthographic projection of the active layer AT10 of the tenth transistor T10 onto the substrate. The sixth and fifth insulating layers within the seventeenth via V17 are etched away, exposing the surface of the first region AT101 of the active layer AT10 of the tenth transistor T10. The seventeenth via V17 is configured to allow the first electrode of the subsequently formed tenth transistor T10 to be connected to the active layer AT10 of the tenth transistor T10 through this via.

[0244] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate lies within the orthographic projection of the active layer AT10 of the tenth transistor T10 onto the substrate. The sixth and fifth insulating layers within the eighteenth via V18 are etched away, exposing the surface of the second region AT102 of the active layer AT10 of the tenth transistor T10. The eighteenth via V18 is configured to allow the second electrode of the subsequently formed tenth transistor T10 to be connected to the active layer AT10 of the tenth transistor T10 through this via.

[0245] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate lies within the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate. The sixth, fifth, fourth, third, second, and first insulating layers within the nineteenth via V19 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1 (i.e., exposing the surface of the first connection portion CL1). The nineteenth via V19 is configured to allow the second electrode of the subsequently formed tenth transistor T10 to be connected to the first electrode C11 of the first capacitor C1 through this via.

[0246] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate lies within the range of the orthographic projection of the opening K0 onto the substrate. The sixth, fifth, fourth, and third insulating layers within the twentieth via V20 are etched away, exposing the surface of the second electrode C12 of the first capacitor C1. The twentieth via V20 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the second electrode C12 of the first capacitor C1 (which is also the first electrode C11 of the second capacitor C2) through the via.

[0247] In an exemplary embodiment, the twenty-first via V21 is located within the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate. The sixth, fifth, and fourth insulating layers within the twenty-first via V21 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The twenty-first via V21 is configured to allow a subsequently formed twelfth connection electrode to be connected to the second electrode C22 of the second capacitor C2 through this via.

[0248] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the substrate lies within the orthogonal projection of the connection structure Vref2M of the second reference signal line onto the substrate. The sixth, fifth, and fourth insulating layers within the 22nd via V22 are etched away, exposing the surface of the connection structure Vref2M of the second reference signal line. The 22nd via V22 is configured to allow the first electrode of the subsequently formed eighth transistor T8 to be connected to the connection structure Vref2M of the second reference signal line through this via.

[0249] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 onto the substrate lies within the range of the orthographic projection of the first reference signal line Vref1 onto the substrate. The sixth insulating layer within the twenty-third via V23 is etched away, exposing the surface of the first reference signal line Vref1. The twenty-third via V23 is configured to allow the first electrode of the subsequently formed ninth transistor T9 to be connected to the first reference signal line Vref1 through this via.

[0250] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate lies within the range of the orthographic projection of the second initial signal line Vinit2 onto the substrate. The sixth insulating layer within the 24th via V24 is etched away, exposing the surface of the second initial signal line Vinit2. The 24th via V24 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the second initial signal line Vinit2 through the via.

[0251] (109) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in Figures 15a and 15b. Figure 15a is a planar structural diagram of four sub-pixels after the formation of the fourth conductive layer, and Figure 15b is a planar schematic diagram of the fourth conductive layer in Figure 15a. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0252] In an exemplary embodiment, the fourth conductive layer includes at least: a first initial signal line Vinit1 and first connection electrodes L1 to thirteenth connection electrodes L13.

[0253] In an exemplary embodiment, the first initial signal line Vinit1 can be a zigzag or strip shape whose main body extends along the first direction X. Vinit1 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 in that row of sub-pixels via a first via V1 in that row, thus providing a first initial signal to the first transistor T1 in that row of sub-pixels. In an exemplary embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1. Within the same sub-pixel, in the second direction Y, the first initial signal line Vinit1 can be located on the side of the second transistor T2 away from the third transistor T3.

[0254] In an exemplary embodiment, the first connecting electrode L1 can be a strip shape or a broken line extending along the second direction Y of the main body, or the first connecting electrode L1 can be generally rectangular in shape. The first connecting electrode L1 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT32 of the active layer AT3 of the third transistor T3) through the second via V2. The first connecting electrode L1 can also be connected to the second region AT22 of the active layer AT2 of the second transistor T2 through the fifth via V5. In an exemplary embodiment, the first connecting electrode L1 can serve as the second electrode of the first transistor T1 and the second electrode of the second transistor T2.

[0255] In an exemplary embodiment, the second connection electrode L2 can be a strip shape or a broken line extending along the second direction Y of the main body. The second connection electrode L2 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT32 of the active layer AT3 of the third transistor T3) through the third via V3. The second connection electrode L2 can also be connected to the first region AT61 of the active layer AT6 of the sixth transistor T6 through the eleventh via V11. In an exemplary embodiment, the second connection electrode L2 can serve as the second electrode of the first transistor T1 and as the first electrode of the sixth transistor T6. Both the first connection electrode L1 and the second connection electrode L2 are connected to the second region AT12 of the active layer AT1 of the first transistor T1, can have substantially the same potential, and can both serve as the second electrode of the first transistor T1.

[0256] In an exemplary embodiment, the third connection electrode L3 can be a strip shape or a broken line extending from the main body along a direction forming an angle with the second direction Y. The third connection electrode L3 can be connected to the first region AT21 of the active layer AT2 of the second transistor T2 through the fourth via V4. The third connection electrode L3 can also be connected to the second electrode C12 of the first capacitor C1 (which is also the first electrode C11 of the second capacitor C2) through the twentieth via V20. In an exemplary embodiment, the third connection electrode L3 can serve as the first electrode of the second transistor T2.

[0257] In an exemplary embodiment, the fourth connection electrode L4 can be a strip shape or a broken line extending along the second direction Y of the main body. The fourth connection electrode L4 can be connected to the first region AT31 of the active layer AT3 of the third transistor T3 through the sixth via V6, and the fourth connection electrode L4 can also be connected to the second region AT82 of the active layer AT8 of the eighth transistor T8 through the fifteenth via V15. In an exemplary embodiment, the fourth connection electrode L4 can serve as the first electrode of the third transistor T3 and as the second electrode of the eighth transistor T8.

[0258] In an exemplary embodiment, the fifth connection electrode L5 can be generally a rectangular structure or a block structure. The fifth connection electrode L5 can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 through the ninth via V9. The fifth connection electrode L5 can serve as the first electrode of the fifth transistor T5.

[0259] In an exemplary embodiment, the sixth connection electrode L6 can be a strip shape or a broken line extending along the second direction Y or at an angle to the second direction Y. The sixth connection electrode L6 can be connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT92 of the active layer AT9 of the ninth transistor T9) through the eighth via V8. The sixth connection electrode L6 can also be connected to the first region AT101 of the active layer AT10 of the tenth transistor T10 through the seventeenth via V17. In an exemplary embodiment, the sixth connection electrode L6 can serve as the first electrode of the tenth transistor T10 and as the second electrode of the fourth transistor T4 and the ninth transistor T9.

[0260] In an exemplary embodiment, the seventh connection electrode L7 may be a strip structure or a broken line structure extending along the first direction X. The seventh connection electrode L7 may be connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the twelfth via V12. The seventh connection electrode L7 may serve as the second electrode of the sixth transistor T6 and as the second electrode of the seventh transistor T7.

[0261] In an exemplary embodiment, the eighth connection electrode L8 can be a strip shape or a broken line extending along the second direction Y of the main body portion. The eighth connection electrode L8 can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 through the thirteenth via V13, and the eighth connection electrode L8 can also be connected to the second initial signal line Vinit2 through the twenty-fourth via V24. In an exemplary embodiment, the eighth connection electrode L8 can serve as the first electrode of the seventh transistor T7.

[0262] In an exemplary embodiment, the ninth connection electrode L9 can be generally a strip structure or a broken line structure extending along the first direction X. The ninth connection electrode L9 can be connected to the first region AT81 of the active layer AT8 of the eighth transistor T8 through the fourteenth via V14. The ninth connection electrode L9 can also be connected to the connection structure Vref2M of the second reference signal line through the twenty-second via V22. The ninth connection electrode L9 can serve as the first electrode of the eighth transistor T8.

[0263] In an exemplary embodiment, the tenth connection electrode L10 may be a strip structure or a broken line structure extending along the second direction Y. The tenth connection electrode L10 may be connected to the first region AT91 of the active layer AT9 of the ninth transistor T9 through the sixteenth via V16. The tenth connection electrode L10 may also be connected to the first reference signal line Vref1 through the twenty-third via V23. The tenth connection electrode L10 may serve as the first electrode of the ninth transistor T9.

[0264] In an exemplary embodiment, the eleventh connection electrode L11 can be generally a strip structure or a broken line structure extending along the first direction X. The tenth connection electrode L10 can be connected to the second region AT102 of the active layer AT10 of the tenth transistor T10 through the eighteenth via V18. The tenth connection electrode L10 can also be connected to the first plate C11 of the first capacitor C1 through the nineteenth via V19. The tenth connection electrode L10 can serve as the second electrode of the tenth connection electrode L10.

[0265] In an exemplary embodiment, the twelfth connecting electrode L12 may be generally rectangular or block-shaped, and the twelfth connecting electrode L12 may be connected to the second plate C22 of the second capacitor C2 through the twenty-first through hole V21.

[0266] In an exemplary embodiment, the thirteenth connection electrode L13 can be generally a rectangular structure or a block structure. The thirteenth connection electrode L13 can be connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the seventh via V7. The thirteenth connection electrode L13 can serve as the first electrode of the fourth transistor T4.

[0267] (110) Forming a pattern for a seventh insulating layer and a first planarization layer. In an exemplary embodiment, forming a pattern for a seventh insulating layer and a first planarization layer may include: depositing a seventh insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the pattern of a fourth conductive layer and a first planarization layer disposed on the seventh insulating layer. A plurality of vias are provided on the seventh insulating layer and the first planarization layer, as shown in FIG16. FIG16 is a planar structural diagram of four sub-pixels after the formation of the first planarization layer.

[0268] In an exemplary embodiment, at least the plurality of vias in a sub-pixel may include at least: a 25th via V25, a 26th via V26, a 27th via V27, and a 28th via V28.

[0269] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate lies within the range of the orthographic projection of the 13th connecting electrode L13 onto the substrate. The first planarization layer and the seventh insulating layer within the 25th via V25 are etched away, exposing the surface of the 13th connecting electrode L13. The 25th via V25 is configured to allow subsequently formed data signal lines to be connected to the 13th connecting electrode L13 through this via.

[0270] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate lies within the orthographic projection of the fifth connecting electrode L5 onto the substrate. The first planarization layer and the seventh insulating layer within the 26th via V26 are etched away, exposing the surface of the fifth connecting electrode L5. The 26th via V260 is configured to allow a subsequently formed first power line to be connected to the fifth connecting electrode L5 through this via.

[0271] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate lies within the range of the orthographic projection of the 7th connecting electrode L7 onto the substrate. The first planarization layer and the 7th insulating layer within the 27th via V27 are etched away, exposing the surface of the 7th connecting electrode L7'. The 27th via V27 is configured to allow a subsequently formed first power line to be connected to the 7th connecting electrode L7 through the via.

[0272] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 onto the substrate lies within the range of the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate. The first planarization layer and the seventh insulating layer within the twenty-eighth via V28 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The twenty-eighth via V28 is configured to allow a subsequently formed first power line to be connected to the second electrode C22 of the second capacitor C2 through the via.

[0273] (111) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a first planarization layer, as shown in Figures 17a and 17b. Figure 17a is a planar structural diagram of four sub-pixels after the formation of the fifth conductive layer, and Figure 17b is a planar schematic diagram of the fifth conductive layer in Figure 17a. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0274] In an exemplary embodiment, the fifth conductive layer includes at least: a data signal line D, a first power supply line VDD, and an anode connection electrode ANL.

[0275] In an exemplary embodiment, the data signal line D is a zigzag or strip shape whose main body extends along the second direction Y. The data signal line D is connected to the thirteenth connection electrode L13 through the twenty-fifth via V25. Since the thirteenth connection electrode L13 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line D and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4.

[0276] In an exemplary embodiment, the first power line VDD is a zigzag or strip-shaped portion extending along the second direction Y. The first power line VDD is connected to the fifth connection electrode L5 through the twenty-sixth via V26. Since the fifth connection electrode L5 is connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 through the via, the connection between the first power line VDD and the first electrode of the fifth transistor T5 is realized, and the power signal is written to the fifth transistor T5. The first power line VDD can also be connected to the second plate C22 of the second capacitor C2 through the twenty-eighth via V28, and a power signal can be provided to the second plate C22 of the second capacitor C2.

[0277] In an exemplary embodiment, the anode connection electrode ANL can be a strip structure or a broken line structure extending along the first direction X, or the anode connection electrode ANL can be a block structure. The anode connection electrode ANL is connected to the seventh connection electrode L7 through the twenty-seventh via V27. Since the seventh connection electrode L7 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 and the second region AT72 of the active layer AT7 of the seventh transistor T7 through the via, the connection between the anode connection electrode ANL and the first electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0278] Thus, the driving circuit layer is fabricated on the substrate. The driving circuit layer can have pixel driving circuits for multiple sub-pixels. Figures 8 to 17d show schematic diagrams of the planar structure of the pixel driving circuits for sub-pixels in the display substrate. In an exemplary embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer may include a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate.

[0279] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, and a first planarization layer. The first insulating layer is disposed between the shielding layer and the first semiconductor layer, the second insulating layer is disposed between the first semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the second semiconductor layer, the fifth insulating layer is disposed between the second semiconductor layer and the third conductive layer, the sixth insulating layer is disposed between the third conductive layer and the fourth conductive layer, and the seventh insulating layer and the first planarization layer are disposed between the fourth conductive layer and the fifth conductive layer.

[0280] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations: forming a second planarization layer pattern, wherein at least an anode via is provided on the second planarization layer; forming an anode pattern (i.e., an anode conductive layer), wherein the anode is connected to the anode connecting electrode through the anode via; forming a pixel definition layer, wherein a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode; forming an organic light-emitting layer using a vapor deposition or inkjet printing process, wherein a cathode is formed on the organic light-emitting layer; forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials, wherein the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0281] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0282] This disclosure also provides a display device, as shown in FIG18, which may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator, or vehicle display.

[0283] This disclosure provides a method for operating a display substrate, as shown in Figures 5a to 6. The display substrate may include multiple sub-pixels, and at least some of the sub-pixels may include pixel driving circuits. At least one pixel driving circuit may include a driving sub-circuit M01, an isolation sub-circuit M02, an isolation control terminal, and a data writing node N5. The driving sub-circuit M01 may include a driving control terminal. In the same pixel driving circuit, the isolation control terminal may be electrically connected to the isolation sub-circuit M02, and the isolation sub-circuit M02 may be disposed between the data writing node N5 and the driving control terminal. The operating method may include:

[0284] Under the control of the isolation control terminal, the isolation sub-circuit M02 writes the signal for writing data to node N5 to the drive control terminal.

[0285] The display substrate and its working method and display device provided in the embodiments of this disclosure are configured such that the isolation sub-circuit in the display substrate is configured to write the signal of the data writing node to the driving control terminal under the control of the isolation control terminal, which to a certain extent solves the technical problem of difficulty in writing low grayscale or black state data signals.

[0286] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0287] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0288] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate and a plurality of sub-pixels disposed on one side of the substrate, wherein at least some of the sub-pixels include a pixel driving circuit, and at least one of the pixel driving circuits includes a driving sub-circuit, an isolation sub-circuit, an isolation control terminal, and a data writing node, wherein the driving sub-circuit includes a driving control terminal; in the same pixel driving circuit, the isolation control terminal is electrically connected to the isolation sub-circuit, and the isolation sub-circuit is disposed between the data writing node and the driving control terminal; The isolation sub-circuit is configured to write the signal of the data writing node to the drive control terminal under the control of the isolation control terminal.

2. The display substrate according to claim 1, wherein, The driving sub-circuit includes a third transistor as a driving transistor, and the blocking sub-circuit includes a tenth transistor as a blocking transistor. The control electrode of the third transistor serves as the driving control terminal, and the control electrode of the tenth transistor serves as the blocking control terminal.

3. The display substrate according to claim 2, wherein, The pixel driving circuit further includes at least one capacitor, and the at least one capacitor includes a first capacitor; The first electrode of the tenth transistor is electrically connected to the data writing node, the second electrode of the tenth transistor is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the control electrode of the third transistor.

4. The display substrate according to claim 3, wherein, The at least one capacitor further includes a second capacitor, wherein the second plate of the first capacitor and the first plate of the second capacitor share a common plate. The second plate of the first capacitor and the first plate of the second capacitor serve as the control electrode of the third transistor; the orthogonal projections of the first capacitor, the second capacitor, and the third transistor on the substrate at least partially overlap.

5. The display substrate according to claim 4, wherein, The pixel driving circuit includes a plurality of transistors, the plurality of transistors including a first type of transistor and a second type of transistor, the first type of transistor including the third transistor, and the second type of transistor including the tenth transistor; In a direction perpendicular to the plane of the substrate, the display substrate includes a shielding layer, an active layer of a first type of transistor, a control electrode of the first type of transistor, a second electrode plate of a second capacitor, an active layer of a second type of transistor, a control electrode of the second type of transistor, and a first electrode and a second electrode of the plurality of transistors, which are sequentially disposed on one side of the substrate. The first plate of the first capacitor is located in the shielding layer, and the second plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer as the control electrode of the first type of transistor.

6. The display substrate according to claim 5, wherein, The first plate of the first capacitor, the second plate of the first capacitor, and the second plate of the second capacitor have at least partially overlapping orthogonal projections onto the substrate.

7. The display substrate according to claim 5, wherein, The first type of transistor further includes a first transistor as a reset transistor, and the second type of transistor further includes a second transistor as a compensation transistor; The second terminals of the first transistor and the second transistor are connected to the second terminal of the third transistor, and the first terminal of the second transistor is electrically connected to the control terminal of the third transistor; In the same sub-pixel, the orthogonal projections of the first transistor and the second transistor onto the substrate at least partially overlap.

8. The display substrate according to claim 7, wherein, The first type of transistor also includes a fourth transistor as a data write transistor and a ninth transistor as a reset transistor, the second terminals of the fourth transistor and the ninth transistor being electrically connected to the data write node.

9. The display substrate according to claim 8 further includes a first light-emitting control line, a second light-emitting control line, and a first power line, wherein the first light-emitting control line and the second light-emitting control line are disposed on the same layer as the control electrode of the first type of transistor, and the first power line is located on the side of the first electrode and the second electrode of the plurality of transistors away from the substrate; The first type of transistor further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a second light-emitting control transistor. The first terminal of the fifth transistor and the second plate of the second capacitor are electrically connected to the first power line. The second terminal of the fifth transistor is connected to the first terminal of the third transistor. The first terminal of the sixth transistor is electrically connected to the second terminal of the third transistor, the second terminal of the first transistor, and the second terminal of the second transistor. The region where the first light-emitting control line overlaps with the active layer of the fifth transistor serves as the control electrode of the fifth transistor; the region where the first light-emitting control line overlaps with the active layer of the ninth transistor serves as the control electrode of the ninth transistor; and the region where the second light-emitting control line overlaps with the active layer of the sixth transistor serves as the control electrode of the sixth transistor. In a plane parallel to the substrate, the first light-emitting control line and the second light-emitting control line extend along a first direction, the first power line extends along a second direction, and the first direction intersects the second direction; Within the same sub-pixel, in the second direction, the first light-emitting control line and the second light-emitting control line are located on the same side of the third transistor, with the second light-emitting control line located away from the first light-emitting control line from the third transistor. One side.

10. The display substrate according to claim 9, further comprising a third reset control line, wherein the first type of transistor further comprises a seventh transistor as a reset transistor and an eighth transistor as a reset transistor; The third reset control line is disposed on the same layer as the control electrode of the first type of transistor. The third reset control line extends along the first direction. In the same sub-pixel, in the second direction, the third reset control line is located on the side of the second light emission control line away from the third transistor. The region where the third reset control line overlaps with the active layer of the seventh transistor serves as the control electrode of the seventh transistor, and the region where the third reset control line overlaps with the active layer of the eighth transistor serves as the control electrode of the eighth transistor.

11. The display substrate according to claim 10, wherein, In the same pixel driving circuit, in the second direction, the tenth transistor and the fourth transistor are located on opposite sides of the third transistor, the fifth transistor and the ninth transistor are located on the side of the fourth transistor away from the third transistor, the sixth transistor is located on the side of the fifth transistor away from the fourth transistor, and the seventh transistor and the eighth transistor are located on the side of the sixth transistor away from the fifth transistor; in the first direction, the fifth transistor, the eighth transistor, and the tenth transistor are located on one side of the third transistor, the first transistor, the second transistor, the sixth transistor, and the seventh transistor are located on the other side of the third transistor, and the third transistor, the fourth transistor, and the ninth transistor are located between the fifth transistor and the sixth transistor.

12. The display substrate according to claim 5, wherein, The first type of transistor further includes a first transistor as a reset transistor, and the second type of transistor further includes a second transistor as a compensation transistor; The second terminal of the first transistor and the first terminal of the second transistor are electrically connected to the control terminal of the third transistor and the second plate of the first capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor.

13. The display substrate according to claim 4, wherein, The pixel driving circuit also includes an eleventh transistor, a first transistor as a reset transistor, and a second transistor as a compensation transistor. The first terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second plate of the first capacitor, and the first plate of the second capacitor. The second terminal of the eleventh transistor is electrically connected to the first terminal of the second transistor. The second terminal of the second transistor is electrically connected to the second terminal of the first transistor and the second terminal of the third transistor.

14. The display substrate according to claim 4, wherein, The pixel driving circuit also includes an eleventh transistor, a first transistor as a reset transistor, and a second transistor as a compensation transistor. The first terminal of the eleventh transistor is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor. The second terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second plate of the first capacitor, and the first plate of the second capacitor. The second terminal of the second transistor is electrically connected to the second terminal of the third transistor.

15. The display substrate according to claim 2, wherein, The pixel driving circuit further includes at least one capacitor, and the at least one capacitor includes a first capacitor; The first plate of the first capacitor is electrically connected to the data writing node, the second plate of the first capacitor is electrically connected to the first electrode of the tenth transistor, and the second electrode of the tenth transistor is electrically connected to the control electrode of the third transistor.

16. The display substrate according to claim 15, wherein, The at least one capacitor further includes a second capacitor, and the pixel driving circuit further includes a first transistor as a reset transistor and a second transistor as a compensation transistor. The second terminal of the first transistor is electrically connected to the second terminal of the second transistor and the second terminal of the third transistor, and the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor; or, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor.

17. The display substrate according to claim 15, wherein, The at least one capacitor further includes a second capacitor, and the pixel driving circuit further includes an eleventh transistor, a first transistor as a reset transistor, and a second transistor as a compensation transistor. The first terminal of the eleventh transistor is electrically connected to the control terminal of the third transistor, the second terminal of the tenth transistor, and the first plate of the second capacitor; the second terminal of the eleventh transistor is electrically connected to the first terminal of the second transistor; and the second terminal of the second transistor is electrically connected to the second terminal of the first transistor and the second terminal of the third transistor. Alternatively, the first terminal of the eleventh transistor is electrically connected to the second terminals of the first transistor and the first terminal of the second transistor; the second terminal of the eleventh transistor is electrically connected to the first plate of the second capacitor, the control terminal of the third transistor, and the second terminal of the tenth transistor; and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor.

18. The display substrate according to any one of claims 13, 14, and 17 further includes a fourth reset control line, wherein the control electrode of the tenth transistor and the control electrode of the eleventh transistor are electrically connected to the fourth reset control line.

19. A display device comprising a display substrate as described in any one of claims 1 to 18.

20. A method of operating a display substrate, the display substrate comprising a plurality of sub-pixels, at least some of the sub-pixels comprising pixel driving circuits, at least one of the pixel driving circuits comprising a driving sub-circuit, an isolation sub-circuit, an isolation control terminal, and a data writing node, the driving sub-circuit comprising a driving control terminal; in the same pixel driving circuit, the isolation control terminal is electrically connected to the isolation sub-circuit, the isolation sub-circuit being disposed between the data writing node and the driving control terminal; the method of operating includes: Under the control of the isolation control terminal, the isolation sub-circuit writes the signal of the data writing node to the drive control terminal.

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