Simultaneous clock domain data processing simulation processing system
By introducing a delay simulation module into the front-end simulation of chip design, the problem of failure to effectively consider delay information in existing technologies is solved, enabling the discovery of potential problems at the front end and improving chip development efficiency.
CN122414079APending Publication Date: 2026-07-17METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In chip design, existing technologies fail to effectively consider latency information during front-end simulation, which can have a significant impact when problems are detected in the back-end, thus affecting chip development efficiency.
Method used
A delay simulation module is introduced into the front-end simulation. By setting a random range and delay value, the data is delayed to simulate delay information and discover potential problems.
Benefits of technology
By introducing delay information during front-end simulation, chip design problems can be detected as early as possible, thereby improving chip development efficiency.
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Figure CN122414079A_ABST
Abstract
本发明涉及芯片技术领域，尤其涉及一种同时钟域数据处理仿真处理系统，包括设置在第一寄存器和第二寄存器之间的同时钟域数据处理路径，以及设置在同时钟域数据处理路径中的延迟仿真模块；延迟仿真模块用于基于最大延迟值设置第一随机范围，若当前传输的数据为第一笔传输数据，则直接将第一随机范围确定为当前随机范围，否则，基于上一笔传输数据对应的随机延迟值生成第二随机范围，并将第一随机范围和第二随机范围的交集确定为当前随机范围，基于当前随机范围生成同时钟域数据处理路径对应的随机延迟值；同时钟域数据处理路径基于随机延迟值对数据进行延迟处理后传输给第二寄存器。本发明提高了芯片开发效率。
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