Display driving method, display driving chip and display device

Abstract

This invention provides a display driving method, a display driving chip, and a display device, belonging to the field of display technology. In this display driving method, the display driving chip can generate a pixel flip flag indicating whether continuously transmitted pixel data has changed. This allows for the determination of whether continuously transmitted pixel data has changed, and based on the pixel flip flag, selective data processing can be performed on the received pixel data, such as selecting to process only the changed pixel data. Therefore, power consumption can be adaptively adjusted based on image data, thereby effectively reducing the power consumption of the display driving chip.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driving method, a display driving chip, and a display device. Background Technology

[0002] The display driver IC (DDIC) is the core control circuit in a display device. It is primarily responsible for processing the received continuous image data stream to drive the pixels in the display panel to emit light, ultimately achieving image display. Consequently, the DDIC inevitably generates operating power consumption, including dynamic power consumption and static power consumption.

[0003] Currently, to reduce the power consumption of DDICs, a pixel enable signal is typically used as the clock gate for the flip-flop level within the DDIC, i.e., as the enable signal for the Integrated Clock Gating (ICG) unit. The pixel enable signal is the data enable signal controlled by the horizontal and vertical sync signals. It is generally active during the horizontal scanning phase and inactive during the blanking phase between adjacent lines, instructing the DDIC to process valid image data only during the horizontal scanning phase. The ICG is usually placed on the path from the clock signal to the flip-flop (FF), allowing the clock signal to be transmitted to the FF or cutting off clock signal transmission under the control of the enable signal. This allows the clock signal to be cut off during the blanking phase, preventing unnecessary clock signal toggling and thus reducing the DDIC's power consumption. However, the current DDIC power consumption remains relatively high. Summary of the Invention

[0004] A display driving method, a display driving chip, and a display device are provided, which can solve the problem of high power consumption in DDIC (Display Driver Integrated Circuit) technologies. The technical solution is as follows: On the one hand, a display driving method is provided, the method comprising: Receives raw image data stream, field synchronization signal, and pixel enable signal; Based on multiple pixel data in the original image data stream, the field synchronization signal, and the pixel enable signal, a pixel flip flag is generated. The pixel flip flag is used to indicate whether the real-time pixel data of the current time period has changed relative to the historical pixel data of the previous time period. Based on the pixel flip flag, the real-time pixel data is selectively processed.

[0005] Optionally, generating a pixel flip flag based on pixel data in the original image data stream, the field synchronization signal, and the pixel enable signal includes: A first pixel flag is generated based on the field synchronization signal and the pixel enable signal. The first pixel flag is used to indicate whether the first pixel data in a frame has been received. Detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate an initial flip flag bit; The pixel flip flag is generated based on the first pixel flag and the initial flip flag.

[0006] Optionally, generating the first pixel flag bit based on the field synchronization signal and the pixel enable signal includes: The pixel enable signal is delayed by one clock cycle to generate a pixel delay enable signal; The counting result is obtained by counting based on the pixel delay enable signal, the field synchronization signal, and the pixel enable signal; The counting result, the pixel enable signal, and the pixel delay enable signal are logically processed to generate the first pixel flag bit.

[0007] Optionally, the real-time pixel data and the historical pixel data are pixel data received in two adjacent clock cycles; the step of detecting whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generating an initial flip flag, includes: In the first clock cycle, the received real-time pixel data is delayed by one clock cycle to generate delayed pixel data; In the second clock cycle following the first clock cycle, the pixel value of the received real-time pixel data is compared with the pixel value of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and the initial flip flag is generated; and if the comparison result is that the pixel values ​​are different, an initial flip flag of the first level is generated, otherwise, an initial flip flag of the second level is generated.

[0008] Optionally, generating the pixel flip flag based on the first pixel flag and the initial flip flag includes: Based on the first pixel flag, the initial flip flag is selected as the pixel flip flag or the flip flag that outputs a first level is selected as the pixel flip flag; and if the first pixel flag indicates that the first pixel data in a frame has been received, the flip flag that outputs a first level is selected as the pixel flip flag, otherwise, the initial flip flag is selected as the pixel flip flag.

[0009] Optionally, the step of selectively processing the real-time pixel data based on the pixel flip flag bit includes: Based on the pixel flip flag, select the real-time pixel data that has changed to perform data processing.

[0010] Optionally, the step of selectively processing the real-time pixel data based on the pixel flip flag bit includes: Based on the pixel flip flag, select to perform read and write operations on the real-time pixel data that has changed. Based on the pixel flip flag, select the real-time pixel data that has undergone read and write operations for data processing.

[0011] Optionally, the method further includes: The pixel flip flag is delayed to generate a gating enable signal; Furthermore, the step of selectively processing the real-time pixel data based on the pixel flip flag bit includes: selectively processing the real-time pixel data based on the pixel flip flag bit and the gating enable signal.

[0012] Optionally, the method further includes: Receive an enable control signal and select whether to enable the pixel flip detection function based on the enable control signal.

[0013] Optionally, the enable control signal is related to whether the image corresponding to the original image data stream is a complex image; Furthermore, if the image corresponding to the original image data stream is a complex image, the pixel flip detection function is disabled by the enable control signal; if the image corresponding to the original image data stream is not a complex image, the pixel flip detection function is enabled by the enable control signal.

[0014] Optionally, the raw image data stream includes: multiple pixel data transmitted in parallel; the method further includes: Simultaneously, a pixel flip detection function is performed on multiple pixel data transmitted in parallel to generate a pixel flip flag bit that includes multiple detection results corresponding one-to-one with the multiple pixel data.

[0015] On the other hand, a display driver chip is provided for performing the display driving method as described in the above aspect.

[0016] In another aspect, a display driver chip is provided, the display driver chip comprising: The pixel flip detection module is used to: receive the original image data stream, the field synchronization signal and the pixel enable signal, and generate a pixel flip flag bit based on the multiple pixel data included in the original image data stream, the field synchronization signal and the pixel enable signal, so as to indicate whether the real-time pixel data of the current period has changed relative to the historical pixel data of the previous period. The data processing module is configured to: receive the pixel flip flag and the original image data stream, and selectively process the real-time pixel data based on the pixel flip flag.

[0017] Optionally, the pixel flip detection module is used for: The first pixel flag is generated based on the field synchronization signal and the pixel enable signal to indicate whether the first pixel data in a frame has been received. Detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate an initial flip flag bit; The pixel flip flag is generated based on the first pixel flag and the initial flip flag.

[0018] Optionally, the pixel flip detection module is used for: The pixel enable signal is delayed by one clock cycle to generate a pixel delay enable signal; The counting result is obtained by counting based on the pixel delay enable signal, the field synchronization signal, and the pixel enable signal; The counting result, the pixel enable signal, and the pixel delay enable signal are logically processed to generate the first pixel flag bit.

[0019] Optionally, the real-time pixel data and the historical pixel data are pixel data received in two adjacent clock cycles; the pixel flip detection module is used for: In the first clock cycle, the received real-time pixel data is delayed by one clock cycle to generate delayed pixel data; In the second clock cycle following the first clock cycle, the pixel value of the received real-time pixel data is compared with the pixel value of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and the initial flip flag is generated; and if the comparison result is that the pixel values ​​are different, an initial flip flag of the first level is generated, otherwise, an initial flip flag of the second level is generated.

[0020] Optionally, the pixel flip detection module is used for: Based on the first pixel flag, the initial flip flag is selected as the pixel flip flag or the flip flag that outputs a first level is selected as the pixel flip flag; and if the first pixel flag indicates that the first pixel data in a frame has been received, the flip flag that outputs a first level is selected as the pixel flip flag, otherwise, the initial flip flag is selected as the pixel flip flag.

[0021] Optionally, the data processing module is used to: select real-time pixel data that has changed based on the pixel flip flag bit for data processing.

[0022] Optionally, the data processing module includes: The data gating module is used to: receive the pixel flip flag and the original image data stream, and select to perform read and write operations on the real-time pixel data that has changed based on the pixel flip flag; The image processing module is configured to: receive the pixel flip flag and real-time pixel data after read / write operations, and select the real-time pixel data after read / write operations for data processing based on the pixel flip flag.

[0023] Optionally, the image processing module includes: An integrated clock gating unit is configured to: receive the pixel flip flag and a clock signal, and control the output of the clock signal in response to the pixel flip flag; and, if the pixel flip flag indicates a change in real-time pixel data, allow the clock signal to be output, otherwise, cut off the output of the clock signal. A trigger is used to: receive real-time pixel data that has undergone read / write operations, and to process the received real-time pixel data upon receiving the clock signal output by the integrated clock gating unit.

[0024] Optionally, the display driver chip further includes: The delay module is used to: receive the pixel flip flag bit, perform delay processing on the pixel flip flag bit, and generate a gating enable signal; The data processing module is further configured to: receive the gating enable signal, and selectively process the real-time pixel data based on the pixel flip flag and the gating enable signal.

[0025] Optionally, the pixel flip detection module is further configured to: receive an enable control signal, and select whether to enable the pixel flip detection function based on the enable control signal.

[0026] Optionally, the enable control signal is related to whether the image corresponding to the original image data stream is a complex image; Furthermore, if the image corresponding to the original image data stream is a complex image, the pixel flip detection function is disabled by the enable control signal; if the image corresponding to the original image data stream is not a complex image, the pixel flip detection function is enabled by the enable control signal.

[0027] Optionally, the raw image data stream includes: multiple pixel data transmitted in parallel; The pixel flip detection module is further configured to: simultaneously perform pixel flip detection on multiple pixel data transmitted in parallel, so as to generate a pixel flip flag bit including multiple detection results corresponding one-to-one with the multiple pixel data.

[0028] In another aspect, a display device is provided, the display device comprising: a display panel, and a display driver chip as described in the other and yet another aspects above.

[0029] In summary, the technical solution provided in this application can bring at least the following beneficial effects: A display driving method, a display driving chip, and a display device are provided. In this display driving method, the display driving chip can generate a pixel flip flag indicating whether continuously transmitted pixel data has changed. This allows for the determination of whether continuously transmitted pixel data has changed, and based on the pixel flip flag, selective data processing can be performed on the received pixel data, such as processing only the changed pixel data. Therefore, power consumption can be adaptively adjusted based on image data, thereby effectively reducing the power consumption of the display driving chip. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a display driver chip provided in an embodiment of this application; Figure 2 This is a schematic diagram of another display driver chip provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of another display driver chip provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of a pixel flip detection module provided in an embodiment of this application; Figure 5This is a schematic diagram of another pixel flip detection module provided in an embodiment of this application; Figure 6 This is a schematic diagram of the circuit structure of a pixel flip detection module provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a data gating module provided in an embodiment of this application; Figure 8 This is a schematic diagram of the circuit structure of a data gating module provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an image processing module provided in an embodiment of this application; Figure 10 This is a schematic diagram of the circuit structure of an image processing module provided in an embodiment of this application; Figure 11 This is a flowchart illustrating a display driving method provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0033] As mentioned in the background, the power consumption of a DDIC (also known as a display driver chip) is mainly divided into two parts: dynamic power consumption and static power consumption. Dynamic power consumption accounts for the majority of the overall power consumption when the chip is working normally.

[0034] Furthermore, it is understandable that a DDIC typically processes continuous image data streams based on the field synchronization control signal VSYNC, the line synchronization control signal HSYNC, and the pixel enable signal DE. The field synchronization signal VSYNC marks the start of a frame of image data; the line synchronization control signal HSYNC marks the start of a line of image data within a frame; and the pixel enable signal DE distinguishes between the line scanning phase and the blanking phase. The line scanning phase is the effective scanning phase of a line, while the blanking phase is, for example, the interval phase between adjacent line scans. Based on this, a DDIC can typically begin acquiring and processing a frame of image data upon receiving a valid field synchronization control signal VSYNC, achieving frame synchronization. Multiple line synchronization control signals HSYNC can be included within one field synchronization control signal cycle. Subsequently, the DDIC can begin acquiring and processing a line of image data upon receiving a valid line synchronization control signal HSYNC, achieving line synchronization. Furthermore, during the line scanning phase, the pixel enable signal DE can remain at an active level to instruct the DDIC to acquire and process one line of image data based on the line synchronization control signal HSYNC. During the blanking phase, the pixel enable signal DE can remain at an inactive level. At this time, even if the line synchronization control signal HSYNC is active, the DDIC stops acquiring and processing one line of image data. Thus, it can be seen that the power consumption caused by the DDIC's internal digital image processing logic circuit is mainly concentrated within the enable range when the pixel enable signal DE is active. Optionally, in this embodiment, the active level can be high relative to the inactive level; for example, the active level can be represented by 1, and the inactive level by 0, but this is not limited to these. Also, the active level is equivalent to enabling, and the inactive level is equivalent to de-enabling.

[0035] It's also understandable that a typical image processing module in a DDIC generally includes a clock module providing the clock signal, multiple flip-flops (FFs), multiple integrated clock gating units (ICGs) connected between the clock module and the FFs, each corresponding to one of the FFs, and combinational logic circuitry connected between every two FFs. The ICGs are responsible for connecting or disconnecting the transmission path from the clock module to the FFs under the control of a received enable signal, allowing the clock signal provided by the clock module to be transmitted to the FFs, or disabling the transmission path. Generally, when the enable signal is active, the transmission path from the clock module to the FFs is connected; when the enable signal is inactive, the transmission path is disconnected.

[0036] Based on this, we are currently considering using the pixel enable signal DE directly as the enable signal transmitted to the integrated clock gating unit ICG. This allows the transmission path from the clock module to the flip-flop FF to be connected only during the row scanning phase, controlling the flip-flop FF to work and controlling the combinational logic circuit to perform logic operations. During the blanking phase, the transmission path from the clock module to the flip-flop FF can be cut off, controlling the flip-flop FF to stop working and controlling the combinational logic circuit to stop logic operations, thereby reducing power consumption.

[0037] However, the continuous image data stream actually input to the DDIC often contains many consecutive identical pixel data, such as the background of a static image. Furthermore, the pixel enable signal DE typically remains active throughout the entire line scan, lacking the ability to determine whether pixel data within a line has changed. Consequently, when faced with multiple consecutive identical pixel data in the same color channel, the DDIC's internal clock network and logic processing circuits are still activated, performing repetitive sampling, charging, and discharging operations. This results in a large amount of redundant clock switching and logic operations, keeping the DDIC's dynamic power consumption at a high level, preventing adaptive power adjustment based on image data. In other words, currently, due to the presence of consecutive, repetitive, and redundant pixel data in the image data stream, the DDIC's internal digital image processing logic circuits maintain a high dynamic power consumption state for extended periods.

[0038] To address this issue, considering the characteristic of continuous, repetitive, and redundant pixel data in image data streams, and in conjunction with the architecture of most image processing circuits, this application introduces a finer-grained clock gating method. It provides a dynamic power consumption optimization method and a general digital circuit architecture based on pixel flip detection to better reduce the dynamic power consumption of the DDIC during normal operation. Pixel flip detection involves detecting whether the pixel values ​​of pixel data received from the same color channel at consecutive different time periods have changed; a change is equivalent to a flip, and no change is equivalent to no flip.

[0039] Figure 1 This is a schematic diagram of the structure of a display driver chip (i.e., DDIC) provided in an embodiment of this application. Figure 1 As shown, the display driver chip includes: a pixel flip detection module 01 and a data processing module 02. Combined with... Figure 1 It can also be seen that the pixel flip detection module 01 and the data processing module 02 can establish a connection.

[0040] The pixel flip detection module 01 is used to: receive the original image data stream, the field synchronization signal i_vs (i.e., VSYNC as described above), and the pixel enable signal i_de (i.e., DE as described above), and generate a pixel flip flag o_tgg_de based on the multiple pixel data included in the original image data stream, the field synchronization signal i_vs, and the pixel enable signal i_de, to indicate whether the real-time pixel data of the current period has changed relative to the historical pixel data of the previous period.

[0041] The raw image data stream can be an upstream input image data stream, such as an application processor (AP) or system-on-chip (SOC) connected to the DDIC. The raw image data stream typically includes multiple consecutively transmitted pixel data, and as described above, the pixel values ​​of these consecutive pixel data can be the same or different. The field synchronization signal i_vs and the pixel enable signal i_de can come from the timing control module. As described above, the field synchronization signal i_vs can mark the frame start position, and i_de can distinguish between the line scan phase and the blanking phase. During the line scan phase, the pixel enable signal i_de can remain at an active level to instruct the DDIC to acquire and process one line of image data; during the blanking phase, the pixel enable signal i_de can remain at an inactive level to instruct the DDIC to stop acquiring and processing one line of image data.

[0042] In this embodiment, the pixel flip detection module 01 can acquire the original input pixel data (i.e., the original image data stream) and perform changes such as adjacent pixel data to determine whether the real-time pixel data received in the current time period has changed compared with the historical pixel data received in the previous time period, and whether the pixel value has changed. Based on the detection result (or pixel change result), the field synchronization signal i_vs, and the pixel enable signal i_de, a pixel flip flag bit o_tgg_de is generated to indicate the change. The whole process can also be called performing the pixel flip detection function.

[0043] For example, if a change is detected, the pixel flip detection module 01 can generate a pixel flip flag bit o_tgg_de with a valid level "1", that is, control the pixel flip flag bit o_tgg_de to be valid, thereby indicating that the pixels of subsequent modules (e.g., data processing module 02) have been flipped, corresponding to the pixel values ​​of real-time pixel data and historical pixel data being different, and the real-time pixel data having changed relative to the historical pixel data. If no change is detected, the pixel flip detection module 01 can generate a pixel flip flag bit o_tgg_de with an invalid level "0", that is, control the pixel flip flag bit o_tgg_de to be invalid, thereby indicating that the pixels of subsequent modules have not been flipped, corresponding to the pixel values ​​of real-time pixel data and historical pixel data being the same, and the real-time pixel data having not changed relative to the historical pixel data. Thus, it has the ability to determine whether the pixel data within a row has changed. Optionally, in the embodiments of this application, the pixel data that has changed can also be called valid pixel data; the pixel data that has not changed can also be called invalid pixel data.

[0044] Here, the current time period and the previous time period can refer to two adjacent clock cycles. In this way, pixel flip detection can be achieved for continuous and adjacent pixel data, determining whether the pixel values ​​of every two consecutive and adjacent pixel data are the same, whether the pixel data has changed, and generating a pixel flip flag bit o_tgg_de indicating the change.

[0045] The data processing module 02 is used to: receive the pixel flip flag o_tgg_de and the raw image data stream, and selectively process the real-time pixel data based on the pixel flip flag o_tgg_de.

[0046] In this embodiment, after receiving parameters such as the pixel flip flag o_tgg_de and the original image data stream, the data processing module 02 can selectively process the received real-time pixel data based on the pixel flip situation, i.e., the pixel value change of the pixel data, to adaptively adjust power consumption based on the image data. Optionally, the data processing performed by the data processing module 02 includes various processing methods such as sampling and logical operations, and outputs the processed results. The data processing module 02 includes the general image processing module described above. It is also understood that performing data processing can make the output data inconsistent with the input data, while not performing data processing can make the output data consistent with the input data.

[0047] For example, as described above, when the pixel flip flag o_tgg_de is invalid, indicating that in two adjacent clock cycles, the real-time pixel data of the current clock cycle has the same pixel value as the historical pixel data of the previous clock cycle, and the real-time pixel data has not changed relative to the historical pixel data, that is, when the pixel flip detection module 01 detects that the pixel has not flipped, the data processing module 02 does not need to perform repeated data processing on the unchanged real-time pixel data. However, when the pixel flip flag o_tgg_de is valid, indicating that in two adjacent clock cycles, the real-time pixel data of the current clock cycle has a different pixel value than the historical pixel data of the previous clock cycle, and the real-time pixel data has changed relative to the historical pixel data, that is, when the pixel flip detection module 01 detects that the pixel has flipped, then the data processing is performed on the changed real-time pixel data.

[0048] Therefore, not only can the pixel enable signal DE be used as the enable signal transmitted to the integrated clock gating unit ICG, so that the data processing module 02 only works in the row scanning stage and not in the blanking stage, thereby reducing dynamic power consumption, but also the data processing module 02 can be prevented from repeatedly processing unchanged pixel data by judging whether the continuously transmitted pixel data has changed, thereby further reducing dynamic power consumption and not affecting the normal processing of changed pixel data.

[0049] In summary, this application provides a display driver chip. Because the pixel flip detection module in this display driver chip can generate a pixel flip flag indicating whether continuously transmitted pixel data has changed, it can determine whether continuously transmitted pixel data has changed. This allows the data processing module to selectively process the received pixel data based on the pixel flip flag, such as selecting to process only the changed pixel data. Therefore, power consumption can be adaptively adjusted based on image data, thereby effectively reducing the power consumption of the display driver chip.

[0050] Optionally, in Figure 1 Based on this, further reference Figure 2 As can be seen, the display driver chip provided in this embodiment may further include a delay module 03. Furthermore, the delay module 03 may be connected between the pixel flip detection module 01 and the data processing module 02.

[0051] The delay module 03 can be used to: receive the pixel flip flag bit o_tgg_de, perform delay processing on the pixel flip flag bit o_tgg_de, and generate the gate enable signal tgg_de_dly.

[0052] Correspondingly, the data processing module 02 can also be used to: receive the gating enable signal tgg_de_dly, and selectively process the real-time pixel data based on the pixel flip flag o_tgg_de and the gating enable signal tgg_de_dly.

[0053] Understandably, considering that the pixel flip detection module 01 performs the flip detection function in real time, it compares real-time pixel data with historical pixel data and immediately outputs a pixel flip flag bit o_tgg_de. However, the pixel data indicated by this pixel flip flag bit o_tgg_de usually takes one or even more clock cycles to reliably transmit to subsequent modules (e.g., data processing module 02). Thus, without delay processing, subsequent modules are likely to obtain incorrect pixel data. Therefore, the delay module 03 can be set to delay the pixel flip flag bit o_tgg_de based on the delay requirements of subsequent modules, so as to ensure data alignment, and the delay time can be exactly equal to the pixel data transmission time. In this way, when the delayed gating enable signal tgg_de_dly is valid, it can be ensured that the pixel data indicated by the pixel flip flag bit o_tgg_de arrives at the subsequent module, thereby ensuring that the subsequent module reliably obtains accurate pixel data.

[0054] Optionally, in some embodiments, the pixel flip detection module 01 can also be used to: receive an enable control signal and select whether to enable the pixel flip detection function based on the enable control signal.

[0055] In other words, in some embodiments, an enable control signal can also be provided to select whether to enable or disable the pixel flip detection function. This can improve detection flexibility, better adapt to application scenarios, and better manage and optimize power consumption.

[0056] Optionally, in some embodiments, the enable control signal may be related to whether the image corresponding to the original image data stream is a complex image. Furthermore, if the image corresponding to the original image data stream is a complex image, the pixel flip detection function is disabled by the enable control signal; if the image corresponding to the original image data stream is not a complex image, the pixel flip detection function is enabled by the enable control signal. Here, a complex image can refer to an image whose pixel value change frequency is greater than a frequency threshold. The frequency threshold can be a preset value.

[0057] Building on this, for example, we will continue to combine Figure 2As can be seen, the enable control signal can include a complex image detection signal i_complex_flag. The complex image detection signal i_complex_flag can be used to indicate whether the image corresponding to the original image data stream is a complex image. Furthermore, a low level "0" for the complex image detection signal i_complex_flag can indicate that the image is not a complex image; a high level "1" for the complex image detection signal i_complex_flag can indicate that the image is a complex image. Thus, the pixel flip detection module 01 can be used to: if the complex image detection signal i_complex_flag reflects that the image corresponding to the original image data stream is not a complex image (i.e., the complex image detection signal i_complex_flag is low level "0"), then select to enable the pixel flip detection function; if the complex image detection signal i_complex_flag reflects that the image corresponding to the original image data stream is a complex image (i.e., the complex image detection signal i_complex_flag is high level "1"), then select to disable the pixel flip detection function.

[0058] Alternatively, in some other embodiments, the combination continues. Figure 2 It can be seen that the enable control signal may also include: the register status signal REG_TOGGLE_EN. Furthermore, if the level of the register status signal REG_TOGGLE_EN is the first level (e.g., high level "1"), then the pixel flip detection function is enabled; if the level of the register status signal REG_TOGGLE_EN is the second level (e.g., low level "0"), then the pixel flip detection function is disabled.

[0059] Optionally, continue to combine Figure 2 It can also be seen that the display driver chip may include a user module 04, which can be used to configure the register status signal REG_TOGGLE_EN. That is, the user module 04 can be used to store user parameter settings, which may include, for example, the enable configuration of pixel flip detection related triggers.

[0060] That is, in this embodiment, the decision to enable the pixel flip detection function and whether to adaptively adjust power consumption based on image data can be made based on the user-configured pixel flip detection trigger state (i.e., the register state signal REG_TOGGLE_EN) and / or, such as the upstream input complex image detection signal i_complex_flag. Furthermore, the enabling conditions for enabling the pixel flip detection function may include, for example: When the pixel flip detection trigger is valid, i.e. the register status signal REG_TOGGLE_EN is valid, if the level of the register status signal REG_TOGGLE_EN is the first level "1", and the upstream input complex image detection signal i_complex_flag reflects that the image corresponding to the original image data stream is a non-complex image, if the complex image detection signal i_complex_flag is a low level "0", i.e. the current image is a non-complex image, then the pixel flip detection function is enabled.

[0061] When the pixel flip detection trigger is invalid, i.e. the register status signal REG_TOGGLE_EN is invalid, such as the level of the register status signal REG_TOGGLE_EN being the second level "0", or the upstream input complex image detection signal i_complex_flag reflecting that the image corresponding to the original image data stream is a complex image, such as the complex image detection signal i_complex_flag being a high level "1", i.e., the current image is a complex image, then the pixel flip detection function is turned off.

[0062] In this way, on the one hand, we can improve work flexibility and adapt to more application scenarios, and on the other hand, we can ensure reliable processing of complex images.

[0063] Optionally, the data processing module 02 provided in this embodiment can be used to: select and process real-time pixel data (also known as valid pixel data) that has changed based on the pixel flip flag bit o_tgg_de. Of course, if a delay module 03 is also included, the data processing module 02 can be used to: select and process valid pixel data based on the pixel flip flag bit o_tgg_de and the gate enable signal tgg_de_dly.

[0064] In other words, in this embodiment of the application, as described above, the data processing module 02 can employ a selective processing mechanism based on the pixel data changes indicated by the pixel flip flag o_tgg_de. It only performs data processing such as sampling and logical operations on the valid parts of the pixel data that have changed when the pixel flip flag o_tgg_de is valid, while not processing the invalid parts of the pixel data that have not changed when the pixel flip flag o_tgg_de is invalid. In this way, by dynamically processing the valid pixel data that has changed according to the pixel data content in the image data stream, while ignoring the unchanged, repetitive invalid pixel data, redundant calculations of pixel data in static or repetitive image areas can be fundamentally avoided, thus saving power consumption without affecting the normal processing of the valid pixel data that has changed. Alternatively, power consumption can be saved by reducing the processing frequency of invalid pixel data.

[0065] Optionally, in Figure 2 On this basis, continue to combine Figure 3 As can be seen, the data processing module 02 provided in this application embodiment may include: a data gating module 021 and an image processing module 022.

[0066] The data gating module 021 can be used to: receive the pixel flip flag bit o_tgg_de and the original image data stream, and select the real-time pixel data that has changed (i.e., the valid pixel data) for read / write operations based on the pixel flip flag bit o_tgg_de. Of course, if the delay module 03 is also included, the data gating module 021 can also receive the gating enable signal tgg_de_dly, and select the valid pixel data for read / write operations based on the pixel flip flag bit o_tgg_de, the gating enable signal tgg_de_dly, and the original image data stream.

[0067] That is, in this embodiment, after the data gating module 021 obtains the pixel flip flag o_tgg_de generated by the pixel flip detection module 01, it can, in conjunction with the real-time input image data stream, select only the pixel data that has changed for delayed snapshot processing. For example, it can use a First In First Out (FIFO) mechanism to select only the pixel data that has changed for sequential write and read operations, thereby outputting the selected image data stream of changed pixel data to the subsequent image processing module 022. In other words, the image data stream received by the image processing module 022 can include only the changed pixel data.

[0068] It is understandable that, compared to directly using the pixel enable signal i_de as the read / write control signal for a FIFO, the data gating module 021 provided in this application embodiment can perform read / write operations even when the pixel value changes or the pixel flips. This can significantly reduce the amount of data written and read, thereby reducing storage requirements. Simultaneously, it can effectively reduce the frequent flipping of the internal address signal during read operations in a FIFO, further reducing dynamic power consumption. Furthermore, the pixel flip flag o_tgg_de and the gate enable signal tgg_de_dly can optimize the operating power consumption of the sampling circuit of the FIFO's internal trigger and the dynamic power consumption caused by frequent charging and discharging of the clock pin capacitor.

[0069] Image processing module 022 can be used to: receive the pixel flip flag o_tgg_de and real-time pixel data after read / write operations, and select the real-time pixel data after read / write operations for data processing based on the pixel flip flag o_tgg_de. Alternatively, if a delay module 03 is also included, image processing module 022 can receive a delayed pixel flip flag o_tgg_de, i.e., a gate enable signal tgg_de_dly, and select the real-time pixel data after read / write operations for data processing based on the gate enable signal tgg_de_dly.

[0070] In other words, in this embodiment, the image processing module 022 can obtain the pixel flip flag o_tgg_de generated by the pixel flip detection module 01, and can obtain the image data stream output by the data gating module 021, including real-time pixel data that has undergone read / write operations. Furthermore, based on the validity of the pixel flip flag o_tgg_de, the image processing module 022 can selectively perform reliable data processing on the pixel data after read / write operations by the data gating module 021, i.e., the changed pixel data. That is, by employing a selective processing mechanism, digital logic operations are performed on the pixel data that has been marked as valid, and finally, the optimized image processing result is output. In this way, the purpose of identifying pixel data content and dynamically optimizing power consumption can be achieved.

[0071] Optionally, digital logic operations may include processing such as color space conversion and gamma correction. The image processing module 022 is the general-purpose image processing module described above. It can serve as the core processing unit of the display driver chip DDIC, and is mainly responsible for performing real-time algorithmic logic operations on the input image data stream to optimize pixel data and ensure a better final display effect.

[0072] Next, based on the above embodiments, the pixel flip detection module 01, data processing module 02, and delay module 03 will be described in detail below: First, in this embodiment of the application, the pixel flip detection module 01 can be used for: The first pixel flag bit first_p is generated based on the field synchronization signal i_vs and the pixel enable signal i_de to indicate whether the first pixel data in a frame has been received.

[0073] Detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate the initial flip flag toggle_all_flag.

[0074] The pixel flip flag o_tgg_de is generated based on the first pixel flag first_p and the initial flip flag toggle_all_flag.

[0075] Based on this, Figure 4 A schematic diagram of the structure of a pixel flip detection module 01 is shown. (Combined with...) Figure 4 As can be seen, the pixel flip detection module 01 may include, for example, a first detection module 011, a second detection module 012, and a third detection module 013.

[0076] The first detection module 011 can be used to: receive the field synchronization signal i_vs and the pixel enable signal i_de, and generate a first pixel flag bit first_p based on the field synchronization signal i_vs and the pixel enable signal i_de to indicate whether the first pixel data in a frame has been received. That is, in this embodiment, an independent detection module can be set to detect whether the acquired pixel data in each frame is the first pixel data, and generate a first pixel flag bit to indicate whether the first pixel data has been acquired.

[0077] For example, assuming the first pixel data is acquired, a first pixel flag bit `first_p` of a first-level voltage is generated to indicate that the first pixel data has been received; assuming the first pixel data is not acquired or a non-first pixel data is acquired, a second pixel flag bit `first_p` of a second-level voltage is generated to indicate that the first pixel data has not been received. Optionally, the first level is, for example, the valid voltage level "1" described above, and the second level is, for example, the invalid voltage level "0" described above. Accordingly, generating the first pixel flag bit `first_p` of the first-level voltage can also be considered as controlling the first pixel flag bit `first_p` to be valid, and generating the first pixel flag bit `first_p` of the second-level voltage can also be considered as controlling the first pixel flag bit `first_p` to be invalid.

[0078] Understandably, generating the first pixel flag `first_p` to indicate whether the first pixel data in a frame has been received is primarily to provide an accurate frame start reference point for pixel flip detection and subsequent data processing. For example, it can precisely pinpoint the start time of the first valid pixel in each frame, ensuring that subsequent modules can accurately determine delay requirements. This allows the generated gating enable signal `tgg_de_dly` to be synchronized with the original image data stream, achieving precise control over the first pixel and all subsequent pixels.

[0079] The second detection module 012 can be used to: receive the original image data stream, detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate an initial flip flag toggle_all_flag. That is, in this embodiment, a separate detection module can be set up to acquire the original input pixel data and, for the same color channel, perform change detection on real-time pixel data and historical pixel data received in adjacent clock cycles, such as detecting whether the pixel value has changed, and also generate an initial flip flag toggle_all_flag. This initial flip flag toggle_all_flag can be used to indicate whether the real-time pixel data detected by the second detection module 012 has changed relative to the historical pixel data.

[0080] For example, as described above, if a change is detected, the second detection module 012 can generate an initial flip flag bit toggle_all_flag with a valid level "1", thus making the initial flip flag bit toggle_all_flag valid. If no change is detected, it can generate an initial flip flag bit toggle_all_flag with an invalid level "0", thus making the pixel flip flag bit o_tgg_de invalid. Therefore, it has the ability to determine whether the pixel data within a row has changed.

[0081] The third detection module 013 can be used to: receive the first pixel flag bit first_p and the initial flip flag bit toggle_all_flag, and generate the pixel flip flag bit o_tgg_de based on the first pixel flag bit first_p and the initial flip flag bit toggle_all_flag. That is, as shown in the figure. Figure 4 As shown, the third detection module 013 can be connected to the first detection module 011 and the second detection module 012 respectively, and can obtain the first pixel flag bit first_p generated by the first detection module 011 and the initial flip flag bit toggle_all_flag generated by the second detection module 012. Furthermore, it can combine the first pixel flag bit first_p and the initial flip flag bit toggle_all_flag to finally generate the pixel flip flag bit o_tgg_de mentioned above.

[0082] For example, if the first pixel flag bit first_p is valid, indicating that the first pixel data has been received, the third detection module 013 can force the pixel flip flag bit o_tgg_de to be valid, that is, generate a pixel flip flag bit o_tgg_de with a valid level of "1". If the first pixel flag bit first_p is invalid, indicating that data other than the first pixel has been received, the third detection module 013 can select the second detection module 012, that is, select the initial flip flag bit toggle_all_flag generated by the second detection module 012 as the pixel flip flag bit o_tgg_de output.

[0083] Understandably, through Figure 4 The architecture and control method shown can not only reliably judge the changes of all adjacent pixel data and perform reliable pixel flip detection, but also ensure that the first pixel data corresponding to the first pixel clock of each frame input can be calculated. This ensures that the first pixel data of each frame image can be forcibly marked as valid flip, thus establishing a reliable starting benchmark for pixel flip detection of all pixel data in the whole frame. It can avoid misjudgment or no response caused by the lack of pixel data from the previous frame, such as avoiding meaningless cross-frame comparisons between the first pixel data of the current frame and the last pixel data of the adjacent previous frame, thereby preventing misjudgment and miscontrol.

[0084] Optionally, in some embodiments, for generating the first pixel flag bit first_p, the pixel flip detection module 01 can be used to: The pixel enable signal is delayed by one clock cycle to generate a pixel delay enable signal.

[0085] The counting result is obtained by counting based on the pixel delay enable signal, field synchronization signal, and pixel enable signal.

[0086] The counting result, pixel enable signal, and pixel delay enable signal are logically processed to generate the first pixel flag bit.

[0087] Based on this, combined Figure 4 , Figure 5 A schematic diagram of another pixel flip detection module 01 is shown. (Combined with...) Figure 5 It can be seen that the first detection module 011 may include: a first delay unit 0111, a counting unit 0112, and a first logic unit 0113.

[0088] The first delay unit 0111 can be used to: delay the pixel enable signal i_de by one clock cycle to generate the pixel delay enable signal i_de_dly.

[0089] For example, in Figure 5 Based on this, further reference Figure 6 As can be seen, the first delay unit 0111 may include a flip-flop FF (identified as FF1). It can be understood that a flip-flop FF is an edge-triggered memory device that samples and latches the signal received from the input at each valid edge of the clock signal received at the clock input, and then holds the latched signal at the output until the next valid edge arrives. Thus, through this flip-flop FF1, the pixel enable signal i_de can be reliably delayed by a complete clock signal. The pixel enable signal i_de can be transmitted to the input of flip-flop FF1, and the pixel delay enable signal i_de_dly can be output through the output of flip-flop FF1. Of course, this delay structure is not limited to this specific delay configuration.

[0090] Based on this, refer to Figure 6 It can also be seen that the pixel flip detection module 01 can be equipped with an integrated clock gating unit (ICG) to provide a clock signal clk to the clock input of each flip-flop FF in the pixel flip detection module 01. Furthermore, the pixel enable signal i_de can also be transmitted to the integrated clock gating unit (ICG) to achieve signal synchronization.

[0091] Optionally, in the embodiments of this application, a valid edge can refer to a rising edge, such as a transition from a low level to a high level, and correspondingly, an invalid edge can refer to a falling edge, such as a transition from a high level to a low level. Of course, it is not limited to this.

[0092] Understandably, by setting the first delay unit 0111 to delay the pixel enable signal i_de, it can lay the foundation for detecting the arrival of the first pixel data and synchronize it to the clock domain of the current module, avoiding the risks brought by cross-clock domains, and thus ensuring that all subsequent processing can be carried out under a unified clock tick.

[0093] The counting unit 0112 can be used to: count based on the pixel delay enable signal i_de_dly, the field synchronization signal i_vs, and the pixel enable signal i_de to obtain the counting result.

[0094] For example, in Figure 5 Based on this, further reference Figure 6 As can be seen, the counting unit 0112 may include a counter, and the pixel delay enable signal i_de_dly, the field synchronization signal i_vs, and the pixel enable signal i_de can all be input to the counter so that the counter can count them. Correspondingly, it can also be seen that the counting unit 0112 can be connected to the first delay unit 0111.

[0095] For example, when the on-site synchronization signal i_vs is valid, marking the start of a new frame, the counter can begin counting. Subsequently, on the valid edge of the pixel enable signal i_de, the counter can be incremented by 1. In this way, the counting result can reflect which row of pixel data in the current frame the currently transmitted real-time pixel data corresponds to.

[0096] Optionally, combined Figure 6 It can also be seen that, in this embodiment of the application, an AND gate with an inverted input (labeled N-AND1) can be set between the flip-flop FF1 and the counter. That is, the gate circuit N-AND1 can be a combinational logic circuit including a NOT gate and an AND gate. The gate circuit N-AND1 can first invert the received input signal "pixel enable signal i_de", and then perform AND logic processing on the inverted pixel enable signal i_de and another received input signal "pixel delay enable signal i_de_dly", thereby more accurately detecting the effective edge of the pixel enable signal i_de.

[0097] As can be understood, inversion processing means that the signal received at the input terminal is inverted from a high level "1" to a low level "0" through a NOT gate, or from a low level "0" to a high level "1". AND logic processing means that if all input signals received at the input terminal of the AND gate are high level "1", then the signal output by the AND gate is high level "1"; conversely, if at least one input signal received at the input terminal of the AND gate is low level "0", then the signal output by the AND gate is low level "0".

[0098] The first logic unit 0113 can be used to: perform logical processing on the counting result, the pixel enable signal i_de, and the pixel delay enable signal i_de_dly to generate the first pixel flag bit first_p.

[0099] In this embodiment of the application, the following continues to be combined Figure 5 and Figure 6As can be seen, the first logic unit 0113 can be connected to the counting unit 0112. The first logic unit 0113 can perform various logical processing on parameters such as the received counting result, the pixel enable signal i_de, and the pixel delay enable signal i_de_dly. Furthermore, when the counting result output by the counter indicates the first row and the first valid edge (i.e., rising edge) of that first row arrives, it can determine the first pixel received in each frame's image data stream and generate a first pixel flag bit first_p with a first level "1", i.e., control the first pixel flag bit first_p to be valid to indicate that the first pixel data has been received. Additionally, when the counting result output by the counter indicates a row other than the first row, it can generate a first pixel flag bit first_p with a second level "0", i.e., control the first pixel flag bit first_p to be invalid to indicate that the first pixel data has not been received.

[0100] For example, in Figure 5 Based on this, further reference Figure 6 As can be seen, the first logic unit 0113 may include: an equality comparator EC, two AND gates (identified as AND1 and AND2 respectively), and an AND gate N-AND2 with an inverted input.

[0101] Among them, the AND gate can be used to perform AND logic processing on the signals received at the input terminal. The AND logic processing is described above and will not be repeated here. The AND gate with input inverting can be used to first invert an input signal received at the input terminal, and then perform AND logic processing on the inverted input signal and another input signal received at the input terminal. The equality comparator EC can be used to compare whether two signals received at the input terminal are equal. If they are equal, a high level "1" is usually output; if they are not equal, a low level "0" is usually output.

[0102] Therefore, combined Figure 6 In the first logic unit 0113, the comparison result is first output by the comparison result of the comparison counter (EC) and the fixed low-level "0" signal. Then, the comparison result and the pixel enable signal (i_de) are ANDed by AND gate 1 to obtain the first logic result. The pixel delay enable signal (i_de_dly) is first inverted by gate N-AND2, and then the pixel enable signal (i_de) and the inverted pixel delay enable signal (i_de_dly) are ANDed to obtain the second logic result. Finally, the first logic result and the second logic result are ANDed by AND gate 2 to generate the first pixel flag bit (first_p). Of course, the logic processing is not limited to the above.

[0103] Optionally, as described above, in the embodiments of this application, the real-time pixel data and the historical pixel data can be pixel data received in two adjacent clock cycles. That is, the pixel flip detection function can be performed on adjacent pixel data.

[0104] Optionally, in some embodiments, the pixel flip detection module 01 can be used to generate the initial flip flag toggle_all_flag for: In the first clock cycle, the received real-time pixel data is delayed by one clock cycle to generate delayed pixel data.

[0105] In the second clock cycle following the first clock cycle, the pixel values ​​of the received real-time pixel data are compared with the pixel values ​​of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and an initial flip flag is generated; and if the comparison result is that the pixel values ​​are different, an initial flip flag of the first level is generated, otherwise, an initial flip flag of the second level is generated.

[0106] Based on this, continue to refer to Figure 5 It can be seen that the second detection module 012 may include: a second delay unit 0121 and a second logic unit 0122.

[0107] The second delay unit 0121 can be used to: delay the received pixel data by one clock cycle in the first clock cycle to generate delayed pixel data.

[0108] For example, such as the first delay unit 0111, in Figure 5 Based on this, further reference Figure 6 It can also be seen that the second delay unit 0121 may include a flip-flop FF (identified as FF2). Correspondingly, the received pixel data can be reliably delayed by one clock cycle through this flip-flop FF2 to generate delayed pixel data. And, refer to... Figure 6 It can also be seen that the integrated clock gating unit (ICG) can be connected to the clock input of the flip-flop FF2 to provide the required clock signal.

[0109] As can be understood, as mentioned earlier, pixel flip detection essentially compares the pixel values ​​of real-time pixel data in the current time period with the pixel values ​​of historical pixel data in the previous time period (e.g., an adjacent previous time period). Therefore, in scenarios where pixel flip detection is performed on adjacent pixel data, by setting the second delay unit 0121 to delay the pixel data by one clock cycle, the current pixel data can be latched and held for one clock cycle at the effective edge of each clock cycle. Thus, in the next clock cycle, the delayed pixel data output by the second delay unit 0121 is exactly the pixel data of the previous clock cycle. This ensures that the second detection module 012 can reliably compare the latest pixel data with this delayed pixel data, reliably determining whether the pixel values ​​of adjacent pixel data have changed. Of course, if the two pixel data being compared are not adjacent, the delay can be the same, corresponding to the difference in clock cycles.

[0110] Optionally, in this embodiment, the original image data stream may include multiple pixel data transmitted in parallel. Based on this, the pixel flip detection module 01 can be used to simultaneously perform pixel flip detection on the multiple parallel pixel data to generate pixel flip flag bits o_tgg_de[n:0] that correspond one-to-one with multiple detection results of the multiple pixel data. [n:0] can represent the number of parallel operations, and n can be an integer greater than 1, such as n = 7, where o_tgg_de[7:0] represents 8 detection results. That is, the original image data stream can be input in the form of a multi-channel pixel data (e.g., RGB pixel data) stream, so that the pixel flip detection module 01 can simultaneously distinguish pixel data from multiple channels within one clock cycle and generate corresponding multiple pixel flip flag bits o_tgg_de. This improves detection efficiency, increases the real-time data processing rate, and achieves more efficient power consumption management.

[0111] For example, refer to Figure 6It can also be seen that the second delay unit 0121 (i.e., trigger FF2) can receive eight parallel pixel data: i_dat_r1, i_dat_g1, i_dat_b2, i_dat_g2, i_dat_r3, i_dat_g3, i_dat_b4, i_dat_g4. Here, r can refer to red pixel data, g can refer to green pixel data, and b can refer to blue pixel data. The second delay unit 0121 can simultaneously delay these eight parallel pixel data, resulting in eight parallel delayed pixel data: o_dat_r1, o_dat_g1, o_dat_b2, o_dat_g2, o_dat_r3, o_dat_g3, o_dat_b4, o_dat_g4. i_dat_r1 and o_dat_r1 form a group of pixel data; the others are similar and will not be repeated. Of course, it's not limited to eight.

[0112] The second logic unit 0122 can be used to: in the second clock cycle after the first clock cycle, compare the pixel value of the received real-time pixel data with the pixel value of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate the initial flip flag bit toggle_all_flag.

[0113] For example, in Figure 5 Based on this, further reference Figure 6 It can be seen that the second logic unit 0122 may include an inequality comparator NQ. The inequality comparator NQ can be used to compare whether two signals received at the input are equal. If they are not equal, a high level "1" is usually output at the output terminal; if they are equal, a low level "0" is usually output at the output terminal. Thus, the second logic unit 0122 can compare the pixel value of the real-time pixel data with the pixel value of the delayed pixel data through the inequality comparator NQ and generate the initial toggle_all_flag.

[0114] Furthermore, it is understandable that, in combination Figure 6 For each pixel data and its corresponding delayed pixel data, i.e., for a set of pixel data, an inequality comparator NQ can be set accordingly. Accordingly, the number of inequality comparators NQ included in the second logic unit 0122 can be the same as the number of parallel input pixel data sets, or the same as the number of pixel data sets, and they correspond one-to-one. For example, combined with... Figure 6In a scenario where the second delay unit 0121 can receive 8 parallel pixel data, the second logic unit 0122 may include 8 unequal comparators NQ (identified as NQ1 to NQ8 respectively). Furthermore, the generated initial flip flag toggle_all_flag may also include initial flip flags toggle_all_flag[n:0] corresponding one-to-one with multiple detection results of the multiple pixel data.

[0115] For example, consider a set of pixel data i_dat_r1 and o_dat_r1, which corresponds to an inequality comparator NQ1. This inequality comparator NQ1 can receive i_dat_r1 and o_dat_r1 and compare their pixel values. If the pixel values ​​of i_dat_r1 and o_dat_r1 are not equal, the inequality comparator NQ1 outputs a high-level "1" initial toggle_all_flag, making toggle_all_flag valid; if the pixel values ​​of i_dat_r1 and o_dat_r1 are equal, the inequality comparator NQ1 outputs a low-level "0" initial toggle_all_flag, making toggle_all_flag invalid. This achieves reliable detection of whether adjacent pixel data has changed.

[0116] Optionally, in some embodiments, the pixel flip detection module 01 can be used to generate the pixel flip flag o_tgg_de for: Based on the first pixel flag, either the initial flip flag is selected as the pixel flip flag or the flip flag that outputs the first level is selected as the pixel flip flag; and if the first pixel flag indicates that the first pixel data in a frame has been received, the flip flag that outputs the first level is selected as the pixel flip flag, otherwise, the initial flip flag is selected as the pixel flip flag.

[0117] On this basis, continue to combine Figure 5 and Figure 6 It can be seen that the third detection module 013 may include: the first gating unit 0131.

[0118] The first gating unit 0131 can be used to: select the initial flip flag bit toggle_all_flag as the pixel flip flag bit o_tgg_de based on the first pixel flag bit first_p, or select the flip flag that outputs the first level (e.g., high level "1") as the pixel flip flag bit.

[0119] For example, the first gating unit 0131 can be a multiplexer MUX (identified as MUX1). The first pixel flag bit first_p can be used as the selection control signal for multiplexer MUX1, and the initial toggle flag bit toggle_all_flag can be used as the input signal for one path 0 of multiplexer MUX1. It can also set the input signal for the other path 1 to a fixed high level "1". Figure 6 The 8'hff shown corresponds to the detection results of 8 parallel pixel data. Based on this, and combined with the previous description, the selection logic of the multiplexer MUX1 can satisfy the following: When the first pixel flag bit first_p is valid, indicating that the first pixel data has been received, path 1 can be selected to force the initial flip flag toggle_all_flag to be output as a high level "1", thus ensuring that each byte in the final output pixel flip flag bit o_tgg_de[7:0] is a high level "1". When the first pixel flag bit first_p is invalid, indicating that non-first pixel data has been received, path 0 can be selected, controlling the initial flip flag bit toggle_all_flag generated by the second detection module 012 as the pixel flip flag bit o_tgg_de output. This initial flip flag bit toggle_all_flag can be synchronized with the pixel enable signal i_de of each row for subsequent module logic processing.

[0120] Optionally, in Figure 3 Based on this, continue to refer to Figure 5 It can also be seen that the pixel flip detection module 01 may include: a fourth detection module 014 and a fifth detection module 015.

[0121] The fourth detection module 014 can be used to: receive the complex image detection signal i_complex_flag and the register status signal REG_TOGGLE_EN, and generate a total control signal K based on the complex image detection signal i_complex_flag and the register status signal REG_TOGGLE_EN; and if the complex image detection signal i_complex_flag reflects that the image corresponding to the original image data stream is not a complex image, and the level of the register status signal REG_TOGGLE_EN is a first level, then generate a total control signal K with a first level (e.g., high level "1"); otherwise, generate a total control signal K with a second level (e.g., low level "0").

[0122] For example, in Figure 5 On this basis, continue to combine Figure 6As can be seen, the fourth detection module 014 may include an AND gate N-AND3 with an inverting input. The input of the N-AND3 gate can receive the complex image detection signal i_complex_flag and the register status signal REG_TOGGLE_EN. Furthermore, the N-AND3 gate can first invert the complex image detection signal i_complex_flag, and then perform AND logic processing on the register status signal REG_TOGGLE_EN and the inverted complex image detection signal i_complex_flag, thereby outputting the overall control signal K.

[0123] The fifth detection module 015 can be used to: receive the total control signal K and the pixel enable signal i_de, and based on the first level (e.g., high level "1") of the total control signal K, select to output the pixel flip flag bit o_tgg_de synchronized with the pixel enable signal i_de to enable the pixel flip detection function, and based on the second level (e.g., low level "0") of the total control signal K, select to stop outputting the pixel flip flag bit o_tgg_de to disable the pixel flip detection function.

[0124] For example, in Figure 5 On this basis, continue to combine Figure 6 It can be seen that the fifth detection module 015 may include a multiplexer MUX (identified as MUX2). The total control signal K can be used as the selection control signal for multiplexer MUX2, and the initial toggle_all_flag can be used as the input signal for one path 0 of multiplexer MUX2, and the input signal for the other path 1 can also be set to a fixed low level "0". Based on this, and combined with the previous description, the selection logic of multiplexer MUX2 can satisfy: when the level of the total control signal K is high level "1", path 0 can be selected, that is, the initial toggle_all_flag is selected as the pixel toggle_tgg_de output to enable the pixel toggle detection function. When the level of the total control signal K is low level "0", path 1 can be selected, that is, the low level "0" output is selected to disable the pixel toggle detection function. Furthermore, combined with... Figure 6 It can also be seen that the multiplexer MUX2 can also receive the pixel enable signal i_de, so that the output pixel flip flag o_tgg_de can be synchronized with the pixel enable signal i_de.

[0125] In addition, refer to Figure 6It can also be seen that another flip-flop FF3 can be connected after the multiplexer MUX2. This flip-flop FF34 can be used to acquire, latch, and output the pixel toggle flag o_tgg_de under the control of the clock signal clk and the pixel enable signal i_de. That is, the pixel toggle flag o_tgg_de can be reliably output through the flip-flop FF3.

[0126] Understandable, Figure 6 The structure shown is also the structure of the pixel flip detection module 01 described in the embodiments of this application. Combined with... Figure 6 As previously described, the clock signal clk can be accessed via the integrated clock gating unit (ICG) and provided to each flip-flop (FF). The pixel enable signal i_de can be transmitted to each flip-flop (FF), the counter, the multiplexer MUX2, gates N-AND1 and N-AND2, and AND gate AND1. The field synchronization signal i_vs can be transmitted to the counter. The complex image detection signal i_complex_flag and the register status signal REG_TOGGLE_EN can both be transmitted to gate N-AND3. Parallel pixel data (e.g., 8 pixels) can be transmitted to flip-flop FF2. Furthermore, a reset signal rst_n can be provided to each flip-flop (FF) to reset it, ensuring that each flip-flop (FF) is always in the same state. Additionally, it can be seen that flip-flop FF1 can be connected to the counter via gate N-AND1, and flip-flop FF1 can also be connected to gate N-AND2. The counter can be connected to the equality comparator EC. The equality comparator EC can also be connected to AND gate AND1. AND gate AND1 and AND gate N-AND2 can both be connected to AND gate AND2. AND gate AND2 can then be connected to multiplexer MUX1. Flip-flop FF2 can be connected to multiple (e.g., 8) inequality comparators NQ. Multiple inequality comparators NQ can all be connected to multiplexer MUX1. Multiplexer MUX1 can then be connected to multiplexer MUX2. Multiplexer MUX2 can then be connected to flip-flop FF3. Finally, flip-flop FF3 can be connected to subsequent modules (e.g., delay module 03, data processing module 02). Other signal inputs and outputs, and the connection methods of each device, can be found in [reference needed]. Figure 6 The details will not be repeated here.

[0127] Optionally, in Figure 3 On this basis, continue to combine Figure 7 It can be seen that the data gating module 021 may include: a second gating unit 0211 and a first-in-first-out storage unit (i.e., FIFO) 0212.

[0128] The second gating unit 0211 can be used to: receive the pixel flip flag o_tgg_de and the original image data stream, and select whether to gating pixel data in the image data stream based on the pixel flip flag o_tgg_de. Furthermore, if the pixel flip flag o_tgg_de indicates that the pixel data has changed, then multiple pixel data in the image data stream are gated. Otherwise, pixel data in the image data stream are not gated.

[0129] For example, in Figure 7 On this basis, further integration Figure 8 It can be seen that for each pixel data, the second gating unit 0211 can include a corresponding multiplexer MUX (identified as MUX3). Accordingly, the number of multiplexers MUX3 included in the second gating unit 0211 is the same as the number of parallel input pixel data, and they correspond one-to-one. Furthermore, for each multiplexer MUX3, the pixel flip flag o_tgg_de can be used as the selection control signal for the multiplexer MUX3. A corresponding pixel data can be used as the input signal for one path 0 of the multiplexer MUX3, and the input signal for the other path 1 can be set to a fixed low level "0". The pixel data received by the multiplexer MUX3 can be the pixel data delayed by the pixel flip detection module 01. For example, for pixel data i_dat_r1 in the original image data stream, the multiplexer MUX3 can receive pixel data o_dat_r1 after a one-clock-cycle delay. Based on this, and combined with the previous description, the gating logic of the multiplexer MUX3 can satisfy the following: When the pixel flip flag o_tgg_de is high ("1"), i.e., o_tgg_de is valid, then path 0 can be selected, i.e., pixel data (e.g., o_dat_r1) is selected and output. When the pixel flip flag o_tgg_de is low ("0"), i.e., o_tgg_de is invalid, then path 1 can be selected, i.e., low ("0") is selected for output, also known as not selecting pixel data in the image data stream.

[0130] The first-in-first-out (FIFO) memory unit 0212 can be used to: receive the pixel flip flag o_tgg_de, the data output from the second gating unit, and the gating enable signal tgg_de_dly; and in response to the pixel flip flag o_tgg_de, select whether to write the data output from the second gating unit 0211, and in response to tgg_de_dly, select whether to read the stored data. Furthermore, if the level of the pixel flip flag o_tgg_de is a first level (e.g., high level "1"), then data is written; otherwise, no data is written. If the level of the gating enable signal tgg_de_dly is a first level (e.g., high level "1"), then data is read; otherwise, no data is read.

[0131] That is, the pixel flip flag bit o_tgg_de can be selected as the read enable signal wen for the first-in-first-out (FIFO) memory cell 0212, and the gate enable signal tgg_de_dly can be selected as the write enable signal ren for the FIFO memory cell 0212. Furthermore, combined with... Figure 8 When the pixel flip flag o_tgg_de is high ("1"), meaning o_tgg_de is active, the read enable signal wen is also active. At this time, the FIFO can store the received data w_dat into it. Simultaneously, based on the required delay, taking n clock cycles as an example, a gate enable signal tgg_de_dly with a delay of n-1 clock cycles can be selected as the write enable signal ren for the FIFO memory unit 0212. Furthermore, combined with... Figure 8 When the gating enable signal tgg_de_dly is high ("1"), meaning it is active, the write enable signal ren is also active. At this time, the FIFO can read and output the stored pixel data. Furthermore, for each pixel data, the second gating unit 0211 can include a corresponding FIFO. Accordingly, the number of FIFOs included in the second gating unit 0211 is the same as the number of parallel input pixel data, and they correspond one-to-one. For example, taking pixel data i_dat_r1 as an example, the data finally read and output by the FIFO can be identified as o_dat_r1_ndly. Thus, in multiple parallel channels, the pixel data of each channel can use the corresponding pixel flip flag o_tgg_de and its delayed gating enable signal tgg_de_dly as the FIFO read / write enable signal, thereby reliably achieving output with different delay requirements. Additionally, combined with... Figure 8 It can also be seen that the clock input of the FIFO can receive the clock signal clk, so that it can work reliably based on the clock signal clk.

[0132] It is understood that, based on the foregoing description, when there are a large number of consecutive identical pixels in the original image data stream, the read / write frequency of the FIFO can be significantly reduced, allowing the entire module to enter a low-power state. That is, the pixel flip flag o_tgg_de can reliably identify whether the pixel value of adjacent pixel data has changed. The multiplexer MUX3 reliably selects the pixel data whose pixel value has changed when the pixel flip flag o_tgg_de is valid, thereby significantly reducing the read / write frequency of the FIFO and optimizing overall power consumption.

[0133] Optionally, in Figure 3 On this basis, continue to combine Figure 9 As can be seen, the image processing module 022 may include: an integrated clock gating unit (i.e., ICG) 0221 and a flip-flop (i.e., FF) 0222.

[0134] The integrated clock gating unit 0221 can be used to: receive the pixel flip flag o_tgg_de and the clock signal clk, and control the output of the clock signal clk in response to the pixel flip flag o_tgg_de. Furthermore, if the pixel flip flag o_tgg_de indicates a change in pixel data, the clock signal clk is allowed to be output; otherwise, the clock signal clk is disabled. Of course, when a delay module 03 is also included, combined with... Figure 9 It can be seen that the integrated clock gating unit 0221 here can receive the delayed pixel flip flag bit o_tgg_de, that is, the gating enable signal tgg_de_dly, and can be the output of the control clock signal clk in response to the gating enable signal tgg_de_dly.

[0135] The trigger 0222 can be used to: receive real-time pixel data that has undergone read / write operations (i.e., valid pixel data that has changed), and process the received real-time pixel data when the clock signal clk output by the integrated clock gating unit 0221 is received, and stop processing the received real-time pixel data when the clock signal clk output by the integrated clock gating unit 0221 is not received.

[0136] That is, as described above, an integrated clock gating unit (ICG) can be set on the transmission path from the clock signal clk to the flip-flop FF. Furthermore, in this embodiment, the clock signal clk can originate from... Figure 9The clock module shown, namely the integrated clock gating unit (ICG), can receive the clock signal clk provided by this clock module. The clock signal clk described above can also all originate from this clock module. The integrated clock gating unit (ICG) can receive the pixel flip flag o_tgg_de, or the gating enable signal tgg_de_dly after delaying the pixel flip flag o_tgg_de output by the delay module 03 to the pixel flip detection module 01, to reliably determine whether adjacent pixel data has changed. Furthermore, when no change is detected in consecutive pixel data, the transmission of the clock signal clk can be cut off, also known as cutting off the clock signal clk downstream of the corresponding register clock tree. For example, controlling the level of the clock signal gate_clk transmitted to the flip-flop FF to an invalid level can cause the flip-flop 0222 to stop subsequent processing. Conversely, when a change is detected in consecutive pixel data, the transmission of the clock signal clk can be allowed again, such as controlling the level of the clock signal gate_clk transmitted to the flip-flop FF to an active level, thereby causing the flip-flop 0222 to start subsequent processing.

[0137] Furthermore, combined Figure 10 It can also be seen that the image processing module 022 (i.e., the general image processing module) can include multiple integrated clock gating units (ICGs) and multiple flip-flops (FFs) in a one-to-one correspondence, respectively identified as FF01, FF02...FF0N, where N is an integer greater than 1. Furthermore, a combinational logic circuit (0223) can be connected between two adjacent flip-flops (FFs). Flip-flops are also called registers. Correspondingly, the stopping of subsequent processing by flip-flop 0222 corresponds to: the register array in the image processing module 022 maintaining the data state after processing the valid pixel data, and the combinational logic circuit between the registers maintaining the current calculation result unchanged. The starting of subsequent processing by flip-flop 0222 corresponds to: the register array in the image processing module 022 starting to work, and the combinational logic circuit between the registers starting to perform logical operations. In this way, the dynamic power consumption of the clock network of the entire architecture only occurs when the pixel data changes and an update is actually needed. This ensures reliable processing of changing pixel data while avoiding redundant processing of duplicate pixel data, effectively reducing power consumption.

[0138] Thus, it can also be considered that the image processing module 022 in this application embodiment can adopt a dynamic power management scheme based on pixel flip detection. By accurately matching the pixel flip flag bit o_tgg_de after different delay processing with the corresponding pixel data, it provides fine register-level gating enable signals for each of the triggers FF01, FF02...FF0N.

[0139] Optionally, combined Figures 1 to 3 The delay module 03 described in this application embodiment can also be used to: obtain different delay requirements of the data processing module 02, and perform corresponding delay processing on the pixel flip flag o_tgg_de based on each delay requirement to generate a corresponding gate enable signal tgg_de_dly.

[0140] That is, in this embodiment of the application, the delay module 03 can also be set to delay the pixel flip flag bit o_tgg_de generated by the pixel flip detection module 01, and generate the corresponding pixel flip flag under the delay (here called the gate enable signal tgg_de_dly) according to different delay requirements and transmit them to the subsequent data processing module 02 respectively.

[0141] Furthermore, in the case of multiple pixel data in parallel, the delay module 03 can delay and beat the pixel flip flag o_tgg_de corresponding to each pixel data in the multi-channel obtained above, providing the data processing module 02 with a trigger-level gating enable signal tgg_de_dly under different delay requirements. Thus, when the pixel flip flag o_tgg_de is o_tgg_de[n:0], the gating enable signal tgg_de_dly generated by the delay module 03 is also a gating enable signal [n:0].

[0142] Thus, combined with the above description, reliable data alignment can be ensured, and the gate switch action can be accurately activated when the required pixel data arrives. This allows for better optimization of dynamic power consumption without affecting the reliable sampling and processing of the data processing module 02 and avoiding processing logic errors caused by signal misalignment.

[0143] Optionally, combined Figure 6 As can be seen, the delay module 03 here can also include a trigger FF. This will not be elaborated upon further here.

[0144] As described above, this application's embodiments achieve precise control of dynamic power consumption through an innovative clock gating mechanism and general digital image logic circuit architecture-level optimization. This ensures that the corresponding clock network switching operation is activated only when pixel data actually changes, thereby fundamentally eliminating the ineffective dynamic power consumption present in traditional global clock schemes. Compared to traditional architectures, this design achieves the following effects at the digital circuit level: Firstly, it enables finer-grained clock gating. For example, by combining... Figure 10Each flip-flop (FF) in the image processing module 022 has an independent clock enable control. The clock signal clk is only allowed to be transmitted to the corresponding flip-flop FF when a change in pixel data is detected. This reliably cuts off the propagation of the clock signal to the downstream clock network, eliminates unnecessary consumption caused by redundant clock tree switching, and avoids dynamic power consumption loss caused by continuous clock flipping, thus effectively reducing power consumption. Secondly, it can automatically adjust dynamic power consumption. For example, by monitoring changes in pixel data in real time, the operational scale of the combinational logic circuit can be dynamically adjusted, also known as dynamically adjusting the scale of active computing units, thereby achieving a precise match between power consumption and computing requirements and effectively reducing power consumption. Thirdly, it can achieve lossless state preservation. For example, during the static pixel data cycle, that is, under the premise that continuous pixel data has not changed, the key processing state of the digital circuit can be preserved, ensuring that the operation can be resumed at any time without generating additional power consumption. This embodiment is applicable to most image processing scenarios, allowing the display driver chip DDIC to automatically switch to a lower power consumption operating state based on pixel data.

[0145] In summary, this application provides a display driver chip. Because the pixel flip detection module in this display driver chip can generate a pixel flip flag indicating whether continuously transmitted pixel data has changed, it can determine whether continuously transmitted pixel data has changed. This allows the data processing module to selectively process the received pixel data based on the pixel flip flag, such as selecting to process only the changed pixel data. Therefore, power consumption can be adaptively adjusted based on image data, thereby effectively reducing the power consumption of the display driver chip.

[0146] This application also provides a display driving method. This method can be applied to the display driver chip described above. For example... Figure 11 As shown, the display driving method includes: Step 1101: Receive the raw image data stream, field synchronization signal, and pixel enable signal.

[0147] Step 1102: Generate a pixel flip flag bit based on multiple pixel data, field synchronization signal and pixel enable signal in the original image data stream.

[0148] The pixel flip flag is used to indicate whether the real-time pixel data of the current period has changed relative to the historical pixel data of the previous period.

[0149] Step 1103: Based on the pixel flip flag, selectively process the real-time pixel data.

[0150] Optionally, generating a pixel flip flag bit (i.e., step 1102 above) based on pixel data, field synchronization signal, and pixel enable signal in the original image data stream may include: The first pixel flag is generated based on the field synchronization signal and the pixel enable signal. The first pixel flag is used to indicate whether the first pixel data in a frame has been received.

[0151] Detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate an initial flip flag.

[0152] Generate a pixel flip flag based on the first pixel flag and the initial flip flag.

[0153] Optionally, the above-mentioned generation of the first pixel flag bit based on the field synchronization signal and the pixel enable signal may include: The pixel enable signal is delayed by one clock cycle to generate a pixel delay enable signal.

[0154] The counting result is obtained by counting based on the pixel delay enable signal, field synchronization signal, and pixel enable signal.

[0155] The counting result, pixel enable signal, and pixel delay enable signal are logically processed to generate the first pixel flag bit.

[0156] Optionally, the real-time pixel data and the historical pixel data are pixel data received in two adjacent clock cycles. Furthermore, the process of detecting whether real-time pixel data in the same color channel of the original image data stream has changed relative to historical pixel data, and generating an initial flip flag, may include: In the first clock cycle, the received real-time pixel data is delayed by one clock cycle to generate delayed pixel data.

[0157] In the second clock cycle following the first clock cycle, the pixel values ​​of the received real-time pixel data are compared with the pixel values ​​of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and an initial flip flag is generated. Furthermore, if the comparison result indicates that the pixel values ​​are different, a first-level initial flip flag is generated; otherwise, a second-level initial flip flag is generated.

[0158] Optionally, the generation of the pixel flip flag bit based on the first pixel flag bit and the initial flip flag bit may include: Based on the first pixel flag, either the initial flip flag or the flip flag that outputs the first level is selected as the pixel flip flag. Furthermore, if the first pixel flag indicates that the first pixel data in a frame has been received, the flip flag that outputs the first level is selected as the pixel flip flag; otherwise, the initial flip flag is selected as the pixel flip flag.

[0159] Optionally, selectively processing real-time pixel data based on the pixel flip flag (i.e., step 1103 above) may include: Based on the pixel flip flag, select the real-time pixel data that has changed for data processing.

[0160] Optionally, the above-mentioned selective data processing of real-time pixel data based on the pixel flip flag bit may include: Based on the pixel flip flag, select the real-time pixel data that has changed to perform read and write operations.

[0161] Based on the pixel flip flag, select the real-time pixel data that has undergone read and write operations for data processing.

[0162] Optionally, in some embodiments, the display driving method may further include: The pixel flip flag is delayed to generate a gating enable signal.

[0163] In addition, based on the pixel flip flag, selective data processing is performed on the real-time pixel data, including: selective data processing of the real-time pixel data based on the pixel flip flag and the gating enable signal.

[0164] Optionally, in some embodiments, the display driving method may further include: Receive the enable control signal and select whether to enable the pixel flip detection function based on the enable control signal.

[0165] Optionally, the enable control signal may be related to whether the image corresponding to the original image data stream is a complex image. Furthermore, if the image corresponding to the original image data stream is a complex image, the pixel flip detection function can be disabled via the enable control signal. If the image corresponding to the original image data stream is not a complex image, the pixel flip detection function can be enabled via the enable control signal.

[0166] Optionally, the raw image data stream may include: multiple pixel data transmitted in parallel. And, in some embodiments, the display driving method may further include: Simultaneously, a pixel flip detection function is performed on multiple pixel data transmitted in parallel to generate pixel flip flag bits that include multiple detection results corresponding one-to-one with the multiple pixel data.

[0167] It is understandable that, since the display driving method has essentially the same implementation and technical effect as the aforementioned display driving chip, for the sake of brevity, the implementation and technical effect of the display driving method will not be described again here.

[0168] This application also provides a display driver chip (i.e., DDIC). This display driver chip can be used to execute the display driving method as described above.

[0169] It is understandable that, since the display driver chip and the aforementioned display driving method have essentially the same technical effects, for the sake of brevity, the technical effects of the display driver chip will not be described again here.

[0170] This application also provides a display device. For example... Figure 12 As shown, the display device includes a display panel and a display driver chip as described above.

[0171] Optionally, the display device described in the embodiments of this application may include, but is not limited to, organic light-emitting diode (OLED) display devices and liquid crystal displays (LCDs). Furthermore, the display device may be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, and any other products or components with display functions.

[0172] It is understandable that, since the display device and the aforementioned display driver chip have essentially the same technical effects, for the sake of brevity, the technical effects of the display device will not be described again here.

[0173] It is understood that the terminology used in the embodiments section of this application is for explaining the embodiments of this application only, and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0174] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection or a communication connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0175] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display driving method, characterized in that, The method includes: Receives raw image data stream, field synchronization signal, and pixel enable signal; Based on multiple pixel data in the original image data stream, the field synchronization signal, and the pixel enable signal, a pixel flip flag is generated. The pixel flip flag is used to indicate whether the real-time pixel data of the current time period has changed relative to the historical pixel data of the previous time period. Based on the pixel flip flag, the real-time pixel data is selectively processed.

2. The method according to claim 1, characterized in that, The step of generating a pixel flip flag based on pixel data in the original image data stream, the field synchronization signal, and the pixel enable signal includes: A first pixel flag is generated based on the field synchronization signal and the pixel enable signal. The first pixel flag is used to indicate whether the first pixel data in a frame has been received. Detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate an initial flip flag bit; The pixel flip flag is generated based on the first pixel flag and the initial flip flag.

3. The method according to claim 2, characterized in that, The generation of the first pixel flag bit based on the field synchronization signal and the pixel enable signal includes: The pixel enable signal is delayed by one clock cycle to generate a pixel delay enable signal; The counting result is obtained by counting based on the pixel delay enable signal, the field synchronization signal, and the pixel enable signal; The counting result, the pixel enable signal, and the pixel delay enable signal are logically processed to generate the first pixel flag bit.

4. The method according to claim 2, characterized in that, The real-time pixel data and the historical pixel data are pixel data received in two adjacent clock cycles; The step of detecting whether real-time pixel data in the same color channel of the original image data stream has changed relative to historical pixel data, and generating an initial flip flag, includes: In the first clock cycle, the received real-time pixel data is delayed by one clock cycle to generate delayed pixel data; In the second clock cycle following the first clock cycle, the pixel value of the received real-time pixel data is compared with the pixel value of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and the initial flip flag is generated; and if the comparison result is that the pixel values ​​are different, an initial flip flag of the first level is generated, otherwise, an initial flip flag of the second level is generated.

5. The method according to claim 2, characterized in that, The step of generating the pixel flip flag bit based on the first pixel flag bit and the initial flip flag bit includes: Based on the first pixel flag, the initial flip flag is selected as the pixel flip flag or the flip flag that outputs a first level is selected as the pixel flip flag; and if the first pixel flag indicates that the first pixel data in a frame has been received, the flip flag that outputs a first level is selected as the pixel flip flag, otherwise, the initial flip flag is selected as the pixel flip flag.

6. The method according to any one of claims 1 to 5, characterized in that, The selective data processing of the real-time pixel data based on the pixel flip flag bit includes: Based on the pixel flip flag, select the real-time pixel data that has changed to perform data processing.

7. The method according to claim 6, characterized in that, The selective data processing of the real-time pixel data based on the pixel flip flag bit includes: Based on the pixel flip flag, select to perform read and write operations on the real-time pixel data that has changed. Based on the pixel flip flag, select the real-time pixel data that has undergone read and write operations for data processing.

8. The method according to any one of claims 1 to 5, characterized in that, The method further includes: The pixel flip flag is delayed to generate a gating enable signal; Furthermore, the step of selectively processing the real-time pixel data based on the pixel flip flag bit includes: selectively processing the real-time pixel data based on the pixel flip flag bit and the gating enable signal.

9. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Receive an enable control signal and select whether to enable the pixel flip detection function based on the enable control signal.

10. The method according to claim 9, characterized in that, The enable control signal is related to whether the image corresponding to the original image data stream is a complex image; Furthermore, if the image corresponding to the original image data stream is a complex image, the pixel flip detection function is disabled by the enable control signal; if the image corresponding to the original image data stream is not a complex image, the pixel flip detection function is enabled by the enable control signal.

11. The method according to any one of claims 1 to 5, characterized in that, The raw image data stream includes: multiple pixel data transmitted in parallel; the method further includes: Simultaneously, a pixel flip detection function is performed on multiple pixel data transmitted in parallel to generate a pixel flip flag bit that includes multiple detection results corresponding one-to-one with the multiple pixel data.

12. A display driver chip, characterized in that, The display driver chip is used to execute the display driving method as described in any one of claims 1 to 11.

13. A display driver chip, characterized in that, The display driver chip includes: The pixel flip detection module is used to: receive the original image data stream, the field synchronization signal and the pixel enable signal, and generate a pixel flip flag bit based on the multiple pixel data included in the original image data stream, the field synchronization signal and the pixel enable signal, so as to indicate whether the real-time pixel data of the current period has changed relative to the historical pixel data of the previous period. The data processing module is configured to: receive the pixel flip flag and the original image data stream, and selectively process the real-time pixel data based on the pixel flip flag.

14. The display driver chip according to claim 13, characterized in that, The pixel flip detection module is used for: The first pixel flag is generated based on the field synchronization signal and the pixel enable signal to indicate whether the first pixel data in a frame has been received. Detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and generate an initial flip flag bit; The pixel flip flag is generated based on the first pixel flag and the initial flip flag.

15. The display driver chip according to claim 14, characterized in that, The pixel flip detection module is used for: The pixel enable signal is delayed by one clock cycle to generate a pixel delay enable signal; The counting result is obtained by counting based on the pixel delay enable signal, the field synchronization signal, and the pixel enable signal; The counting result, the pixel enable signal, and the pixel delay enable signal are logically processed to generate the first pixel flag bit.

16. The display driver chip according to claim 14, characterized in that, The real-time pixel data and the historical pixel data are pixel data received in two adjacent clock cycles; The pixel flip detection module is used for: In the first clock cycle, the received real-time pixel data is delayed by one clock cycle to generate delayed pixel data; In the second clock cycle following the first clock cycle, the pixel value of the received real-time pixel data is compared with the pixel value of the delayed pixel data to detect whether the real-time pixel data in the same color channel in the original image data stream has changed relative to the historical pixel data, and the initial flip flag is generated. Additionally, if the comparison result shows that the pixel values ​​are different, an initial flip flag of the first level is generated; otherwise, an initial flip flag of the second level is generated.

17. The display driver chip according to claim 14, characterized in that, The pixel flip detection module is used for: Based on the first pixel flag bit, the initial flip flag bit is selected as the pixel flip flag bit or the flip flag bit that outputs the first level is selected as the pixel flip flag bit; Furthermore, if the first pixel flag indicates that the first pixel data in a frame has been received, then the flip flag that outputs the first level is selected as the pixel flip flag; otherwise, the initial flip flag is selected as the pixel flip flag.

18. The display driver chip according to any one of claims 13 to 17, characterized in that, The data processing module is used to: select and process real-time pixel data that has changed based on the pixel flip flag.

19. The display driver chip according to claim 18, characterized in that, The data processing module includes: The data gating module is used to: receive the pixel flip flag and the original image data stream, and select to perform read and write operations on the real-time pixel data that has changed based on the pixel flip flag; The image processing module is configured to: receive the pixel flip flag and real-time pixel data after read / write operations, and select the real-time pixel data after read / write operations for data processing based on the pixel flip flag.

20. The display driver chip according to claim 19, characterized in that, The image processing module includes: An integrated clock gating unit is configured to: receive the pixel flip flag and a clock signal, and control the output of the clock signal in response to the pixel flip flag; and, if the pixel flip flag indicates a change in real-time pixel data, allow the clock signal to be output, otherwise, cut off the output of the clock signal. A trigger is used to: receive real-time pixel data that has undergone read / write operations, and to process the received real-time pixel data upon receiving the clock signal output by the integrated clock gating unit.

21. The display driver chip according to any one of claims 13 to 17, characterized in that, The display driver chip also includes: The delay module is used to: receive the pixel flip flag bit, perform delay processing on the pixel flip flag bit, and generate a gating enable signal; The data processing module is further configured to: receive the gating enable signal, and selectively process the real-time pixel data based on the pixel flip flag and the gating enable signal.

22. The display driver chip according to any one of claims 13 to 17, characterized in that, The pixel flip detection module is also used to: receive an enable control signal, and select whether to enable the pixel flip detection function based on the enable control signal.

23. The display driver chip according to claim 22, characterized in that, The enable control signal is related to whether the image corresponding to the original image data stream is a complex image; Furthermore, if the image corresponding to the original image data stream is a complex image, the pixel flip detection function is disabled by the enable control signal; if the image corresponding to the original image data stream is not a complex image, the pixel flip detection function is enabled by the enable control signal.

24. The display driver chip according to any one of claims 13 to 17, characterized in that, The raw image data stream includes: multiple pixel data transmitted in parallel; The pixel flip detection module is further configured to: simultaneously perform pixel flip detection on multiple pixel data transmitted in parallel, so as to generate a pixel flip flag bit including multiple detection results corresponding one-to-one with the multiple pixel data.

25. A display device, characterized in that, The display device includes: a display panel, and a display driver chip as described in any one of claims 12 to 24.

Images