Data processing method and device of SRAM controller, equipment and medium

Abstract

The present disclosure relates to a data processing method, device, equipment and medium of an SRAM controller, the method comprising: receiving an access request of an AXI bus; in the case that the access request is burst transmission, performing address splitting according to the size of the transmission data in the access request to obtain a plurality of access addresses; calculating an error correction code for the access addresses and sequentially storing the access addresses carrying the error correction code into a cache queue; taking out a first access address from the cache queue, determining an address range accessed by the SRAM controller according to the first access address and the bit width of the SRAM device; merging the access addresses within the address range from the remaining access addresses in the cache queue into one access operation; and accessing the SRAM device based on the access operation. The present disclosure can improve the data transmission efficiency between the AXI bus and the SRAM, effectively improve the system bandwidth utilization, and reduce the access delay.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method, apparatus, device and medium for an SRAM controller. Background Technology

[0002] In high-performance system-on-a-chip (SoC) design, the AXI (Advanced Extensible Interface) bus serves as a complex, high-performance interface, supporting features such as outstanding transmissions and out-of-order access. SRAM (Static Random Access Memory), on the other hand, typically employs an address-mapped interface. Currently, when converting between the two protocols, only transmission requests with the same operation type and contiguous addresses are usually merged. This simplistic protocol conversion can lead to low bandwidth utilization and high latency, failing to fully leverage the performance of both AXI and SRAM. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a data processing method, apparatus, device, and medium for an SRAM controller.

[0004] According to one aspect of this disclosure, a data processing method for an SRAM controller is provided, the method comprising: Receive access requests from the AXI bus; In the case where the access request is a burst transmission, the address is split according to the size of the data transmitted in the access request to obtain multiple access addresses; Calculate the error correction code for the access address, and store the access addresses carrying the error correction code into the cache queue in sequence; The first access address is retrieved from the cache queue, and the address range accessed by the SRAM controller is determined based on the first access address and the bit width of the SRAM device. Among the remaining access addresses in the cache queue, the access addresses within the address range are merged into a single access operation; The SRAM device is accessed based on the access operation.

[0005] According to another aspect of this disclosure, a data processing apparatus for an SRAM controller is also provided, the apparatus comprising: The request receiving module is used to receive access requests from the AXI bus. The address splitting module is used to split the address according to the size of the data transmitted in the access request when the access request is a burst transmission, so as to obtain multiple access addresses. The address caching module is used to calculate the error correction code for the access address and store the access address carrying the error correction code into the cache queue in sequence. The address range determination module is used to retrieve the first access address from the cache queue and determine the address range accessed by the SRAM controller based on the first access address and the bit width of the SRAM device. The address merging module is used to merge the access addresses within the address range into a single access operation from the remaining access addresses in the cache queue. An access module is used to access the SRAM device based on the access operation.

[0006] According to another aspect of this disclosure, an electronic device is also provided, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the above method.

[0007] According to another aspect of this disclosure, a computer-readable storage medium is also provided, the storage medium storing a computer program for performing the above-described method.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art: The technical solution provided in this disclosure includes: receiving an access request from the AXI bus; in the case of a burst transmission in the access request, splitting the address according to the size of the data transmitted in the access request to obtain multiple access addresses; calculating an error correction code for the access address and storing the access addresses carrying the error correction code into a cache queue in sequence; retrieving the first access address from the cache queue and determining the address range to be accessed by the SRAM controller according to the first access address and the bit width of the SRAM device; merging the access addresses within the address range into a single access operation from the remaining access addresses in the cache queue; and accessing the SRAM device based on the access operation.

[0009] This solution receives access requests from the AXI bus and, in burst transmission scenarios, splits the address based on the size of the transmitted data to obtain multiple access addresses. An error correction code is then calculated for each access address and stored in a cache queue, ensuring that the access addresses are protected throughout the caching and subsequent processing, preventing data errors caused by address faults. Based on this, the access address range is determined using the first access address as a baseline and considering the bit width of the SRAM device. Then, from the remaining access addresses in the cache queue, access addresses within this range are merged into a single access operation, which then accesses the SRAM device. This process does not require strictly consecutive access addresses; instead, merging is based on the bit width of the SRAM device. Even in automotive-grade peripheral access scenarios with discrete addresses and mismatched bit widths, multiple accesses that would otherwise require multiple operations can be merged into a single SRAM access, significantly reducing the number of SRAM read / write operations, improving data transfer efficiency between the AXI bus and SRAM, effectively increasing system bandwidth utilization, and reducing access latency. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of the data processing method for the SRAM controller described in the embodiments of this disclosure; Figure 2 This is a block diagram of the SRAM controller write transfer data according to an embodiment of this disclosure; Figure 3 This is a schematic diagram of the address merging process described in an embodiment of this disclosure; Figure 4 This is a block diagram of the SRAM controller read transfer data according to an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of the data processing device of the SRAM controller described in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the structure of the electronic device described in the embodiments of this disclosure. Detailed Implementation

[0013] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0014] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0015] AXI is a complex, high-performance on-chip bus whose protocol supports outstanding transmissions and out-of-order access. SRAM interfaces, on the other hand, are typically address-mapped. Simple protocol conversion can lead to low bandwidth utilization and high latency, failing to fully leverage the performance of both AXI and SRAM.

[0016] Automotive-grade chips must meet the ISO 26262 standard, which has strict requirements for diagnostic coverage (DC) and fault mode coverage. For example, for ASIL B requirements, the diagnostic coverage must be higher than 95%; for ASIL D requirements, the single-point fault diagnostic coverage must reach 99%. This requires the controller to have strong error detection and handling capabilities.

[0017] As a critical data storage unit, SRAM needs to be protected against transient faults (such as those caused by radiation) and permanent hardware failures. During protocol conversion, a fault in the address decoding circuit may cause data to be read using an incorrect address, even though the data itself has a correct ECC (Error Correction Code) and cannot pass the regular ECC check, ultimately leading to the system receiving erroneous data.

[0018] To improve bus transmission bandwidth utilization, related technologies typically employ request merging strategies, which identify and consolidate transmission requests with the same operation type and contiguous physical addresses. Specifically, this includes merging consecutive read requests into a single merged read request, or consecutive write requests into a single merged write request, aiming to improve efficiency by reducing the number of transaction interactions. However, this address contiguity-based merging mechanism has significant limitations in automotive-grade MCU applications. Since automotive peripherals are typically slow devices, and the effective bit width of the AXI bus is often smaller than the storage bit width of SRAM, address discontinuities (i.e., discrete addresses) are highly likely to occur during actual transmission. Related technologies can only handle ideal contiguous address streams and cannot effectively cope with the complex discontinuous address transmission scenarios described above. This results in a large number of transmission requests not being merged, severely restricting the overall system bandwidth utilization.

[0019] Regarding data integrity and correctness assurance, related technologies typically perform ECC verification on data and addresses only before AXI data enters the controller. This protection is then removed during the intermediate processing of protocol conversion, and ECC verification codes are only re-added when the data is finally written to SRAM. This mechanism of initial and final verification with no protection in the middle results in a lack of effective data protection in the core AXI-to-SRAM protocol conversion stage, failing to meet the stringent end-to-end security requirements of automotive-grade MCUs. Especially in complex scenarios involving the aforementioned transmission merging, the related technologies fail to provide corresponding ECC protection and error correction mechanisms. Once the address decoding circuit fails or the data is flipped during the conversion path, the system is highly susceptible to acquiring logically erroneous data, making it difficult to achieve the diagnostic coverage required by high-level functional safety standards.

[0020] Based on this, the present disclosure provides a data processing method, apparatus, device and medium for an SRAM controller. This solution is applied to an SRAM controller with high utilization and end-to-end ECC protection and error correction functions. The external access interface of the SRAM controller is an AXI bus interface. The SRAM controller can merge transmissions with discontinuous transmission addresses and different burst lengths and send them to the SRAM device. ECC protection is provided throughout the protocol conversion process of the SRAM controller, realizing end-to-end ECC protection and error correction functions, and meeting the safety requirements of automotive-grade ASIL D level.

[0021] Figure 1 This disclosure provides a flowchart of a data processing method for an SRAM controller, applicable to vehicle-mounted applications. The data processing method for the SRAM controller may include the following steps.

[0022] Step S102: Receive an access request from the AXI bus. The access request can be either a write request or a read request.

[0023] Step S104: In the case of a burst transmission in the access request, the address is split according to the size of the data transmitted in the access request to obtain multiple access addresses.

[0024] Step S106: Calculate the error correction code for the access address and store the access addresses carrying the error correction code into the cache queue in sequence.

[0025] Step S108: Retrieve the first access address from the cache queue, and determine the address range accessed by the SRAM controller based on the first access address and the bit width of the SRAM device.

[0026] Step S110: Among the remaining access addresses in the cache queue, access addresses within the address range are merged into a single access operation.

[0027] Step S112: Access the SRAM device based on the access operation.

[0028] To better understand the solution, the following describes access requests as either write requests or read requests, and provides different implementation examples for each.

[0029] Reference Figure 2 In this embodiment, the access request includes a write request, and the corresponding data processing method of the SRAM controller can be referred to the following.

[0030] Step (1): The SRAM controller receives a write request from the AXI bus. This write request carries ECC.

[0031] Step (2): In the case of a burst transmission for the write request, the address is split according to the size of the data transmitted in the access request to obtain multiple access addresses; where each access address corresponds to one piece of data.

[0032] Specifically, the AXI bus supports burst transfers, meaning that multiple data items can be transferred at once, with each data item corresponding to an access address. The burst length indicates the number of data items in a single burst transfer. For example, a burst length of 0 indicates the transfer of 1 data item, and a burst length of 3 indicates the transfer of 4 data items.

[0033] When a write request arrives on the AXI bus, in order to adapt to the physical characteristics of SRAM, the SRAM controller will first parse the address, burst length, data size, and other information of the write request.

[0034] If the burst length of the write request transmission is 0, it indicates that it is a single transmission and there is no need to split the address.

[0035] If the burst length of the write request transfer is greater than 0, it indicates that it is a burst transfer. In this case, the SRAM controller splits the address according to the information carried by the write request, specifically, splitting the address according to the effective transfer data size, and the number of access addresses obtained by splitting is equal to the burst transfer length plus 1.

[0036] In this embodiment, for continuous burst transmissions, the SRAM controller splits them into multiple independent access addresses for more flexible optimization and merging, thereby improving bandwidth utilization.

[0037] Step (3) recalculates the ECC of the access address and stores the access address carrying the ECC into the cache queue (FIFO, First In First Out) in sequence. This ensures that the access address itself is protected during subsequent caching and merging processes, meets ASIL D security requirements, and prevents address decoding errors.

[0038] Step (4): Take the first access address from the cache queue, and determine the address range accessed by the SRAM controller based on the first access address and the bit width of the SRAM device.

[0039] Specific reference Figure 3 For the merging operation of access addresses, as long as the cache queue is not empty, the first access address is taken out and used as a reference. Based on the bit width of the SRAM device, the address range of the SRAM controller for this access is determined.

[0040] For example, suppose the SRAM device is 64 bits (8 bytes) wide. If the first access address is 0x00, then the address range for this access by the SRAM controller is 0x00 to 0x07.

[0041] Step (5): Among the remaining access addresses in the cache queue, access addresses within the address range will be merged into a single access operation.

[0042] This embodiment may include: Read the current access address from the cache queue; where the current access address can be the access address currently being read in the cache queue in the first-in-first-out order, for example, it can be the next access address after the first access address, or it can be the i-th access address in this address merging process.

[0043] If the current access address falls within the address range, then a merge operation is performed on the current access address.

[0044] Then, it is determined whether the cache queue is empty; if the cache queue is not empty, the next access address is used as the new current access address; if the cache queue is empty, multiple access addresses falling within the address range are merged into one SRAM access operation.

[0045] Referring to the above embodiments, the remaining access addresses in the cache queue are gradually retrieved. If the split access addresses fall within the address range of the SRAM controller's current access, regardless of whether these access addresses are consecutive, they can be merged into a single access operation of the SRAM device. If the access addresses exceed the address range of the current access, the current address merging operation ends, and the next address merging operation is performed.

[0046] As an example, access address 1 is 0x00, which is within the address range of this access, so a merge operation is performed on it; access address 2 is 0x02, although address 0x01 is skipped, access address 2 is still within the address range of this access, so a merge operation is performed on it; access address 3 is 0x06, which is within the address range of this access, so a merge operation is performed on it; access address 4 is 0x09, which exceeds the address range of this access, so the merge operation stops. Therefore, access addresses 1, 2, and 3 are merged into a single SRAM access operation. Furthermore, for access address 4, which exceeds the address range of this access, a new packing process can be initiated and repeated. Figure 3 The process is shown.

[0047] In this embodiment, when merging the split access addresses, the access addresses are not required to be continuous. Instead, the address range is determined by the bit width of the SRAM device. As long as the access addresses are within the same address range, regardless of whether there are gaps in between, i.e., they are not continuous, they are captured and merged. This method can greatly reduce the number of SRAM read and write operations. What might have required 3 writes can now be merged into 1, thereby significantly improving bandwidth utilization. It is particularly suitable for peripheral access scenarios in automotive-grade MCUs where bit widths are mismatched and addresses jump around randomly.

[0048] In this embodiment, after performing a merging operation on the current access addresses, the number of addresses merged is recorded.

[0049] Specifically, during the address merging process, a counter can be used to record how many access addresses were merged. If no merging operation was performed, the counter value is 0. The recorded number of addresses indicates the number of data items that need to be processed in this SRAM access operation. For example, if 3 access addresses were merged, 3 sets of data need to be processed.

[0050] Step (6), the access request includes a write request, and the corresponding access operation includes a write transfer operation; then, the SRAM device is accessed based on the write transfer operation.

[0051] This embodiment may include: merging the data and the effective number of bits in the cache queue according to the write transfer operation and the number of addresses to be merged, to obtain the data to be written and the target effective number of bits. Based on the target effective number of bits, reading the first data from the SRAM device and updating the first data with the data to be written, to obtain the second data. Calculating the error correction code on the second data and writing the second data carrying the error correction code into the SRAM device.

[0052] Specifically, for write transfer operations, a data merging operation is required. Based on the number of addresses to be merged, the data in the cache queue is retrieved through the merging control logic and merged sequentially according to their positions in the SRAM bit width to obtain the data to be written.

[0053] At the same time, the significant digits (WSTRB) corresponding to each data point are also merged to obtain the target significant digits.

[0054] If not all of the target valid bits are 1, read the first data from the SRAM device; update the data at the corresponding position in the first data using the data to be written, while keeping the data at other positions in the first data unchanged, to obtain the second data.

[0055] Specifically, if the target valid bits are not all 1, it means that this operation is not a full write transfer operation of the SRAM device, but only modifies a part of the data in the SRAM device, such as writing only 2 bytes out of 8 bytes, instead of overwriting the entire 64 bits.

[0056] Therefore, the first data originally stored in the SRAM device is read according to the write transfer operation; then, according to the target number of valid bits, the data at the corresponding position in the first data is rewritten into valid data to be written, while keeping the data at other positions in the first data unchanged.

[0057] Since the data stored in the SRAM device has changed, the original ECC checksum is no longer valid. Therefore, the ECC is recalculated for the second data, and the second data carrying the new ECC is written into the SRAM device.

[0058] After calculating the ECC on the second data, or before writing the second data carrying the new ECC into the SRAM device, this embodiment can verify the second data carrying the error correction code; if the verification fails, the second data carrying the error correction code is corrected; if the error correction fails, an error report is generated and a write response error message is returned to the AXI bus.

[0059] Specifically, this embodiment performs ECC verification on the address and data of the second data carrying the error correction code. If an error is detected, such as a bit flip in the cached data, an attempt is made to correct it. If the error is too severe to be corrected, the data cannot be written to prevent memory contamination. In this case, the error can be reported to the system, and an error message can be sent back to the AXI bus write response.

[0060] Reference Figure 4 In this embodiment, the access request includes a read request, and correspondingly, the access operation includes a read transfer operation. In this read scenario, the data processing method of the SRAM controller can be referred to the following.

[0061] Receive a read request from the AXI bus. This read request carries ECC. In the case of a burst transfer, the address is split according to the size of the data to be transferred in the access request, resulting in multiple access addresses. An error correction code is calculated for each access address, and the access addresses carrying the error correction codes are sequentially stored in a buffer queue. The first access address is retrieved from the buffer queue, and the address range to be accessed by the SRAM controller is determined based on the first access address and the bit width of the SRAM device. Among the remaining access addresses in the buffer queue, those within the address range are merged into a single read transfer operation. The SRAM device is accessed based on this read transfer operation.

[0062] In this embodiment, the address merging operation for read requests is the same as in the aforementioned write request embodiment. The main difference lies in the implementation process of accessing the SRAM device based on read transfer operations. Therefore, this embodiment focuses on describing accessing the SRAM device based on read transfer operations.

[0063] In this embodiment, accessing the SRAM device based on a read transfer operation may include: The third data is read from the SRAM device according to the read transfer operation; an error correction code is calculated on the third data, and the third data carrying the error correction code is returned to the AXI bus.

[0064] Specifically, when third-party data is read from the SRAM device, it needs to undergo ECC verification and error correction. If error correction is not possible, the data needs to be reported to the system.

[0065] After ECC verification and error correction, the third data needs to be returned. Since there is no control over the valid bits when reading data, more data can be returned. Therefore, even if the third data is read after address merging, it does not need to be split and can be directly returned to the AXI bus.

[0066] In this embodiment, when reading third data from the SRAM device according to a read transfer operation, since sending additional data does not disrupt the system state (unlike a write operation which overwrites data), the SRAM controller does not need to painstakingly split the third data after merging the read data. Instead, it directly returns the entire third data block to the AXI bus, which then automatically extracts the required portion. This design simplifies the hardware logic and improves the transmission efficiency of the read path.

[0067] The data processing method for the SRAM controller provided in the above embodiments can be applied to a certain automotive-grade microprocessor chip development project and can meet the requirements of automotive-grade ASIL D level.

[0068] Specifically, when applied to automotive-grade MCUs, it significantly improves bandwidth utilization for scenarios where low-speed peripheral interfaces need to access SRAM. The data bit width of the low-speed interface is much smaller than that of the SRAM device, and it can provide end-to-end ECC protection throughout the process.

[0069] In summary, the data processing method for an SRAM controller provided in this disclosure includes: receiving an access request from an AXI bus; in the case of a burst transmission in the access request, splitting the address according to the size of the data transmitted in the access request to obtain multiple access addresses; calculating an error correction code for the access address and storing the access addresses carrying the error correction code into a cache queue in sequence; retrieving the first access address from the cache queue and determining the address range to be accessed by the SRAM controller based on the first access address and the bit width of the SRAM device; merging the access addresses within the address range into a single access operation from the remaining access addresses in the cache queue; and accessing the SRAM device based on the access operation.

[0070] This solution receives access requests from the AXI bus and, in burst transmission scenarios, splits the address based on the size of the transmitted data to obtain multiple access addresses. An error correction code is then calculated for each access address and stored in a cache queue, ensuring that the access addresses are protected throughout the caching and subsequent processing, preventing data errors caused by address faults. Based on this, the access address range is determined using the first access address as a baseline and considering the bit width of the SRAM device. Then, from the remaining access addresses in the cache queue, access addresses within this range are merged into a single access operation, which then accesses the SRAM device. This process does not require strictly consecutive access addresses; instead, merging is based on the bit width of the SRAM device. Even in automotive-grade peripheral access scenarios with discrete addresses and mismatched bit widths, multiple accesses that would otherwise require multiple operations can be merged into a single SRAM access, significantly reducing the number of SRAM read / write operations, improving data transfer efficiency between the AXI bus and SRAM, effectively increasing system bandwidth utilization, and reducing access latency.

[0071] Figure 5 This is a schematic diagram of the structure of the data processing apparatus of the SRAM controller according to an embodiment of the present disclosure. The apparatus may include the following modules: The request receiving module 502 is used to receive access requests from the AXI bus; Address splitting module 504 is used to split the address according to the size of the data transmitted in the access request when the access request is a burst transmission, so as to obtain multiple access addresses. Address caching module 506 is used to calculate error correction codes for the access addresses and store the access addresses carrying error correction codes into the cache queue in sequence. Address range determination module 508 is used to retrieve the first access address from the cache queue and determine the address range accessed by the SRAM controller based on the first access address and the bit width of the SRAM device. The address merging module 510 is used to merge the access addresses within the address range into a single access operation from the remaining access addresses in the cache queue. Access module 512 is used to access the SRAM device based on the access operation.

[0072] The device provided in this embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0073] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Figure 6 As shown, the electronic device 600 includes one or more processors 601 and memory 602.

[0074] The processor 601 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 600 to perform desired functions.

[0075] The memory 602 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 601 may execute the program instructions to implement the data processing method of the SRAM controller of the embodiments of this disclosure described above, and / or other desired functions. Various contents such as input signals, signal components, and noise components may also be stored in the computer-readable storage medium.

[0076] In one example, the electronic device 600 may also include an input device 603 and an output device 604, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0077] In addition, the input device 603 may also include, for example, a keyboard, a mouse, etc.

[0078] The output device 604 can output various information to the outside, including determined distance information, direction information, etc. The output device 604 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0079] Of course, for the sake of simplicity, Figure 6 Only some of the components of the electronic device 600 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 600 may include any other suitable components depending on the specific application.

[0080] Furthermore, this embodiment also provides a computer-readable storage medium storing a computer program for executing the data processing method of the SRAM controller described above.

[0081] The present disclosure provides a computer program product for a data processing method, apparatus, electronic device, and medium for an SRAM controller, including a computer-readable storage medium storing program code. The program code includes instructions that can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0083] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing method for an SRAM controller, characterized in that, The method includes: Receive access requests from the AXI bus; In the case where the access request is a burst transmission, the address is split according to the size of the data transmitted in the access request to obtain multiple access addresses; Calculate the error correction code for the access address, and store the access addresses carrying the error correction code into the cache queue in sequence; The first access address is retrieved from the cache queue, and the address range accessed by the SRAM controller is determined based on the first access address and the bit width of the SRAM device. Among the remaining access addresses in the cache queue, the access addresses within the address range are merged into a single access operation; The SRAM device is accessed based on the access operation.

2. The method according to claim 1, characterized in that, The step of merging the remaining access addresses in the cache queue into a single SRAM access operation includes: Read the current access address from the cache queue; If the current access address falls within the address range, then a merge operation is performed on the current access address; Determine whether the cache queue is empty; If the cache queue is not empty, then the next access address will be used as the new current access address; If the cache queue is empty, multiple access addresses falling within the address range will be merged into a single SRAM access operation.

3. The method according to claim 2, characterized in that, The method further includes: After performing a merge operation on the current access addresses, record the number of addresses merged.

4. The method according to claim 1, characterized in that, The access request includes a write request, and correspondingly, the access operation includes a write transfer operation; The access to the SRAM device based on the access operation includes: Based on the write transfer operation and the number of addresses merged, the data in the cache queue and the effective number of bits of the data are merged to obtain the data to be written and the target effective number of bits. Based on the target number of valid bits, the first data of the SRAM device is read, and the first data is updated using the data to be written to obtain the second data; An error correction code is calculated for the second data, and the second data carrying the error correction code is written into the SRAM device.

5. The method according to claim 4, characterized in that, The process of reading first data from the SRAM device based on the target number of effective bits, and updating the first data using the data to be written to obtain second data, includes: If not all of the target valid bits are 1, read the first data of the SRAM device; The data to be written is used to update the data at the corresponding position in the first data, while keeping the data at other positions in the first data unchanged, to obtain the second data.

6. The method according to claim 4, characterized in that, After calculating the error correction code on the second data, the method includes: The second data carrying the error correction code is verified; If the verification fails, the second data carrying the error correction code is corrected. In the event of error correction failure, an error report is generated and a write response error message is returned to the AXI bus.

7. The method according to claim 1, characterized in that, The access request includes a read request, and correspondingly, the access operation includes a read transfer operation; The access to the SRAM device based on the access operation includes: Third data is read from the SRAM device according to the read transfer operation; An error correction code is calculated for the third data, and the third data carrying the error correction code is returned to the AXI bus.

8. A data processing device for an SRAM controller, characterized in that, The device includes: The request receiving module is used to receive access requests from the AXI bus. The address splitting module is used to split the address according to the size of the data transmitted in the access request when the access request is a burst transmission, so as to obtain multiple access addresses. The address caching module is used to calculate the error correction code for the access address and store the access address carrying the error correction code into the cache queue in sequence. The address range determination module is used to retrieve the first access address from the cache queue and determine the address range accessed by the SRAM controller based on the first access address and the bit width of the SRAM device. The address merging module is used to merge the access addresses within the address range into a single access operation from the remaining access addresses in the cache queue. An access module is used to access the SRAM device based on the access operation.

9. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a terminal device, cause the terminal device to perform the method as described in any one of claims 1-7.

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