ATSU board data reading and writing system and method based on JTAG interface

Abstract

The application belongs to the technical field of avionics, and particularly relates to a JTAG interface-based ATSU board data reading and writing system and method, which comprises an upper computer and an embedded control device, the embedded control device comprises an STM32 module, an FPGA module, a JTAG module and a first relay module, the upper computer and the FPGA module are in communication connection with the STM32 module respectively, the JTAG module is connected with the FPGA module and the first relay module respectively, the FPGA module is in communication connection with the first relay module, and the first relay module is used for controlling the on-off between the JTAG module and the ATSU board. The application can reduce manual operation actions on the ATSU board and reduce the probability of manual operation failure.

Description

Technical Field

[0001] This invention belongs to the technical field of avionics, specifically relating to an ATSU board data read / write system and method based on a JTAG interface. Background Technology

[0002] Typically, an ATSU CPU A10 board contains four Flash chips and one EEPROM. The current approach is to remove the required memory chip when data reading or writing is needed, insert it into a programmer to read or write data to the memory chip, and then solder the memory chip back on after completion.

[0003] The disadvantages of the aforementioned prior art are: 1. Soldering is required on the circuit board, which increases the probability of human error and can easily damage the solder pads on the circuit board.

[0004] 2. It is necessary to disassemble, assemble, and store the memory chip. Since the chip pins are small, too many operations can easily cause the pins to be twisted or broken.

[0005] 3. When multiple tests are required, multiple disassembly and assembly operations are necessary.

[0006] Therefore, how to avoid disassembling and reassembling storage chips when reading or writing data has become an urgent problem to be solved. Summary of the Invention

[0007] This application discloses an ATSU board data read / write system and method based on the JTAG interface, which can reduce manual operation of the ATSU board and lower the probability of human error.

[0008] The first aspect of this application discloses an ATSU board data read / write system based on a JTAG interface. The system includes a host computer and an embedded control device. The embedded control device includes an STM32 module, an FPGA module, a JTAG module, and a first relay module. The host computer and the FPGA module are respectively communicatively connected to the STM32 module. The JTAG module is respectively connected to the FPGA module and the first relay module. The FPGA module is communicatively connected to the first relay module. The first relay module is used to control the connection and disconnection between the JTAG module and the ATSU board.

[0009] As an optional implementation, in the first aspect of the embodiments of this application, the embedded control device further includes a power supply module and a second relay module. The power supply module is electrically connected to the STM32 module, the FPGA module and the second relay module respectively. The FPGA module is communicatively connected to the second relay module. The second relay module is used to control the on / off connection between the power supply module and the ATSU board.

[0010] As an optional implementation, in the first aspect of the embodiments of this application, the host computer includes: The first device self-test unit is used to send device self-test commands to the embedded control device, process the returned self-test data and display it in the message window of the host computer. The first chip ID reading unit is used to send chip ID reading instructions to the embedded control device, process the returned chip ID data, and display it in the message window of the host computer.

[0011] As an optional implementation, in the first aspect of the embodiments of this application, the host computer further includes: The first EEPROM reading unit is used to send EEPROM reading instructions to the embedded control device, perform integrity checks on the returned EEPROM data, and generate EEPROM data file one. If the data is incomplete, the EEPROM reading task is repeated. The first EEPROM writing unit is used to read EEPROM data file two, unpack EEPROM data file two, send EEPROM write command to embedded control device to make device prepare to receive EEPROM data file two, send EEPROM data file two to embedded control device and wait for device response to confirm that EEPROM data file writing is complete. The first FLASH reading unit is used to send FLASH reading instructions to the embedded control device. After checking the integrity of the returned FLASH data packets, it generates FLASH data packet file one. If the data is incomplete, the FLASH reading task is repeated. After waiting for FLASH data packet file one to be received, the data packet files are integrated to generate a FLASH data file. The first FLASH writing unit is used to read FLASH data packet file two, send FLASH write instructions to the embedded control device, so that the device is ready to receive FLASH data packet file two, and after sending FLASH data packet file two to the embedded control device, wait for the device to respond and confirm that the FLASH data packet file writing is complete.

[0012] As an optional implementation, in a first aspect of the embodiments of this application, the embedded control device includes: The second device self-test unit is used to receive device self-test commands, perform a self-test and record the status of pins, memory chips and voltages in the device, and integrate the self-test data for transmission back. The second chip ID reading unit is used to receive chip ID reading instructions, find the corresponding list segment one, control the ATSU board to perform chip ID reading operations according to list segment one, and read the corresponding chip ID according to the data in list segment one. After reading, the chip ID data is sent to the host computer. As an optional implementation, in the first aspect of the embodiments of this application, the embedded control device further includes: The second EEPROM reading unit is used to receive EEPROM reading instructions, find the corresponding list segment two, control the ATSU board to perform EEPROM reading operations according to list segment two, read the corresponding EEPROM data file one according to the data in list segment two, wait for EEPROM data file one to complete the full verification, and send EEPROM data file one to the host computer. The second EEPROM writing unit is used to receive the EEPROM write command, then receive the EEPROM data file two sent by the host computer, find the corresponding list segment three, control the ATSU board to perform the EEPROM write operation according to the list segment three, and write the EEPROM according to the data in the list segment three and the EEPROM data file two. After waiting for the EEPROM data file two to be written, it sends the EEPROM data file write completion signal to the host computer. The second FLASH reading unit is used to receive FLASH reading instructions, find the corresponding list segment four, control the ATSU board to perform FLASH reading operations according to list segment four, read the corresponding FLASH data packet file one according to the data in list segment four, wait for the FLASH data to complete the full verification, integrate the FLASH data packet file one into a FLASH data file, and send the FLASH data file to the host computer. The second FLASH writing unit is used to receive FLASH writing instructions, then receive FLASH data packet file two sent by the host computer, find the corresponding list segment five, control the ATSU board to perform FLASH writing operation according to list segment five, and write FLASH according to the data in list segment five in combination with FLASH data packet file two. After waiting for FLASH data packet file two to be written, it sends a FLASH data file writing completion signal to the host computer.

[0013] As an optional implementation, in the first aspect of the embodiments of this application, the first relay module is connected to the ATSU board through an interface module, and the second relay module is connected to the ATSU board through an interface board; the FPGA module is also connected to the first relay module through a JTAG loopback line, wherein the signal output terminal of the JTAG module is selectively connected to the interface module or the JTAG loopback line through the first relay module.

[0014] The second aspect of this application discloses a method for reading and writing data on an ATSU board based on a JTAG interface, which employs the ATSU board data reading and writing system based on a JTAG interface disclosed in the first aspect of this application, and includes the following steps: S1. Equipment self-test: Performs self-test on the equipment according to the equipment self-test command from the host computer and sends back the self-test data; S2. Chip ID Reading: Read the chip ID data of the ATSU board according to the chip ID reading command of the host computer, and send the chip ID data back; S3, EEPROM Read: Read the EEPROM data file 1 from the ATSU board according to the EEPROM read command from the host computer, and then send the EEPROM data file 1 back. S4, EEPROM writing: Write the EEPROM data file 2 to the ATSU board according to the EEPROM writing instruction from the host computer, and send the EEPROM writing completion signal to the host computer; S5. FLASH Read: Read the FLASH data file 1 of the ATSU board according to the FLASH read command of the host computer, and send the FLASH data file 1 back; S6, FLASH Writing: Write the FLASH data file 2 to the ATSU board according to the FLASH writing command from the host computer, and send the FLASH writing completion signal to the host computer.

[0015] As an optional implementation method, in the first aspect of the embodiments of this application, In step S1: After the host computer sends a device self-test command to the embedded control device, the embedded control device will perform a self-test on the pin status, memory chip and voltage in the device, and send the self-test data back. The host computer processes the sent self-test data and displays it in the host computer's message window. In step S2: After the host computer sends the chip ID reading instruction to the embedded control device, the device will find the corresponding list segment one, use the JTAG interface to control the control chip on the ATSU board, use the control chip in combination with list segment one to perform the chip ID reading operation on the ATSU board, and send the chip ID data back. The host computer processes the sent chip ID data and displays it in the host computer's message window. In step S3: After the host computer sends the EEPROM read command to the embedded control device, the device will find the corresponding list segment two, use the JTAG interface to control the control chip on the ATSU board, use the control chip in conjunction with list segment two to perform EEPROM read operation on the ATSU board, read the corresponding EEPROM data according to the data in list segment two, and send back the read EEPROM data. Then, the EEPROM data is completely checked and EEPROM data file one is generated. If the data is incomplete, the EEPROM read task will be repeated. In step S4: the EEPROM data file two stored by the host computer is read and unpacked. An EEPROM write command is sent to the embedded control device to prepare the device to receive the EEPROM data file two. The embedded control device will find the corresponding list segment three, use the JTAG interface to control the control chip on the ATSU board, and use the control chip in conjunction with list segment three to perform the EEPROM write operation on the ATSU board. The corresponding EEPROM data file two is written according to the data in list segment three. After waiting for the EEPROM data file two to be written, the EEPROM write completion signal is sent to the host computer. In step S5: After the host computer sends the FLASH read command to the embedded control device, the device will find the corresponding list segment four, use the JTAG interface to control the control chip on the ATSU board, and use the control chip in conjunction with list segment four to perform FLASH read operation on the ATSU board. According to the data in list segment four, the corresponding EEPROM data is read, and the read FLASH data packet is sent back in a packetized form. Then, the FLASH data packet is checked for completeness and FLASH data packet file one is generated. If the data is incomplete, the FLASH read task will be repeated. After the FLASH data packet file one is received, the FLASH data packet file one is integrated to generate a FLASH data file, and the FLASH data file is sent to the host computer. In step S6: the second FLASH data packet file saved by the host computer is read, and a FLASH write command is sent to the embedded control device to prepare the device to receive the second FLASH data packet file. The embedded control device will find the corresponding list segment five, use the JTAG interface to control the control chip on the ATSU board, and use the control chip in conjunction with list segment five to perform a FLASH write operation on the ATSU board. The corresponding FLASH data packet file two is written according to the data in list segment five. After waiting for the FLASH data to be written, the FLASH write completion signal is sent to the host computer.

[0016] The third aspect of this application discloses a computer-readable storage medium storing a computer program, wherein the computer program causes a computer to execute the ATSU board data read / write method based on the JTAG interface disclosed in the second aspect of this application.

[0017] Compared with related technologies, the embodiments of this application have the following beneficial effects: This invention includes a host computer and an embedded control device. The embedded control device includes an STM32 module, an FPGA module, a JTAG module, and a first relay module. The host computer and the FPGA module are communicatively connected to the STM32 module. The JTAG module is connected to both the FPGA module and the first relay module. The FPGA module is communicatively connected to the first relay module, which controls the connection and disconnection between the JTAG module and the ATSU board. This invention uses a universal JTAG interface for data reading, which reduces manual operation of the ATSU board and lowers the probability of human error. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the overall structure of an ATSU board data read / write system based on a JTAG interface disclosed in an embodiment of this application; Figure 2 This is a circuit block diagram of an ATSU board data read / write system based on a JTAG interface disclosed in an embodiment of this application; Figure 3 This is a schematic diagram of the host computer software of an ATSU board data read / write system based on a JTAG interface disclosed in an embodiment of this application. Figure 4This is a schematic diagram of the lower-level machine software of an ATSU board data read / write system based on a JTAG interface disclosed in an embodiment of this application; Figure 5 This is a flowchart illustrating an ATSU board data read / write method based on a JTAG interface disclosed in an embodiment of this application. Figure 6 This is a schematic diagram of the operation flow of the host computer software for an ATSU board data reading and writing method based on the JTAG interface disclosed in an embodiment of this application. Figure 7 This is a schematic diagram of the operation flow of the lower-level software for an ATSU board data reading and writing method based on the JTAG interface disclosed in an embodiment of this application.

[0020] The components are as follows: 1. Host computer; 11. First device self-test unit; 12. First chip ID reading unit; 13. First EEPROM reading unit; 14. First EEPROM writing unit; 15. First FLASH reading unit; 16. First FLASH writing unit; 2. Embedded control device; 21. STM32 module; 22. FPGA module; 23. JTAG module; 24. First relay module; 25. Power supply module; 26. Second relay module; 27. Second device self-test unit; 28. Second chip ID reading unit; 29. ​​Second EEPROM reading unit; 210. Second EEPROM writing unit; 211. Second FLASH reading unit; 212. Second FLASH writing unit; 3. ATSU board; 4. Interface module; 5. Interface board; 6. JTAG loopback circuit. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms “comprising” and “having”, and any variations thereof, in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0023] In the embodiments of this application, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0024] This application discloses an ATSU board 3 data reading and writing system and method based on the JTAG interface. By using the common JTAG interface for data reading, manual operation of the ATSU board 3 can be reduced, thereby lowering the probability of human error.

[0025] The technical solution of this application will be described in detail below with reference to specific embodiments.

[0026] Please see Figure 1An ATSU (Air Traffic Service Unit) board data read / write system based on a JTAG interface includes: a host computer 1 and an embedded control device 2. The embedded control device 2 is connected to the host computer 1 via a USB (Universal Serial Bus) interface to control the host computer 1, send and download data, and connect to the ATSU board 3 via a JTAG interface to control the ATSU board 3 and send and download data. The host computer 1 can be a computer. The embedded control device 2 includes an STM32 module 21, an FPGA module 22, a JTAG module 23, and a first relay module 24. The host computer 1 and the FPGA module 22 are connected to the STM32 module 21, and the JTAG module 23 is connected to both the FPGA module 22 and the first relay module 24. The FPGA module 22 is connected to the first relay module 24, and the first relay module 24 is used to control the connection and disconnection between the JTAG module 23 and the ATSU board 3. STM32 module 21 is used for communication with host computer 1 and for parsing instructions from host computer 1. FPGA module 22 is used to control the JTAG interface, the relay for JTAG interface loopback testing, and the external power relay control. STM32 module 21 can be an STM32 series microcontroller from STMicroelectronics. FPGA module 22 (Field-Programmable Gate Array) can be a field-programmable gate array. JTAG module 23 serves as a test and debug interface module, configured to communicate with host computer 1 and generate test signals conforming to the JTAG protocol according to instructions from host computer 1 to read and write data to ATSU board 3.

[0027] In some embodiments, please refer to Figure 1 and 2The embedded control device 2 also includes a power supply module 25 and a second relay module 26. The power supply module 25 is electrically connected to the STM32 module 21, the FPGA module 22, and the second relay module 26, respectively, to supply power to the STM32 module 21 and the FPGA module 22. The second relay module 26 is electrically connected to the ATSU board 3 to supply power to the ATSU board 3. The FPGA module 22 is communicatively connected to the second relay module 26, which controls the on / off connection between the power supply module 25 and the ATSU board 3. In some embodiments, the host computer 1 sends instructions to the STM32 module 21 for parsing, and then sends them to the FPGA module 22. The FPGA module 22 controls the first relay module 24 and the second relay module 26, respectively, to connect the JTAG module 23 to the ATSU board 3, thereby establishing a data reading path that sequentially connects the host computer 1, the STM32 module 21, the FPGA module 22, the JTAG module 23, and the ATSU board 3, and also connecting the power supply module 25 to the ATSU board 3, thereby establishing a power supply path between the power supply module 25 and the ATSU board 3.

[0028] In some embodiments, please refer to Figure 1 and 2 The first relay module 24 is connected to the ATSU board 3 via the interface module 4, and the second relay module 26 is connected to the ATSU board 3 via the interface board 5. The FPGA module 22 is also connected to the first relay module 24 via the JTAG loopback line 6. The signal output terminal of the JTAG module 23 is selectively connected to either the interface module 4 or the JTAG loopback line 6 via the first relay module 24. After receiving instructions from the STM32 module 21, the FPGA module 22 can establish connections between the STM32 module 21 and the JTAG loopback line 6, the JTAG module 23, the first relay module 24, and the second relay module 26, respectively. This allows the STM32 module 21 to control the first relay module 24 and the second relay module 26, enabling the first relay module 24 to control the connection between the JTAG module 23 and the ATSU board 3, or the connection between the JTAG module 23 and the JTAG loopback line 6, thereby ensuring data reading / writing or JTAG loopback testing of the ATSU board 3. It also enables the second relay module 26 to control the connection between the power supply module 25 and the ATSU board 3. By setting the second relay module 26, the power-on sequence of the ATSU board 3 can be controlled to ensure normal power-on. In some embodiments, the power-on sequence control is as follows: the power-on stage is a progressive power supply, sequentially turning on the output of the two 5V power supplies. Since the ATSU board 1 needs to be connected to two 5V power supplies, it cannot be powered on simultaneously and needs to be powered on at certain intervals. The second relay module 26 can sequentially power on the ATSU board 1 to ensure normal power-on.

[0029] In some embodiments, please refer to Figure 3 The host computer 1 is equipped with host computer software, which is installed as an application program on the host computer 1. It communicates with the embedded control device 2 via a serial port. It uses the serial port refresh function to update the serial port number of the embedded control device 2 that is connected to the host computer 1 and establishes a connection. After the serial port connection is established, it will perform task polling until a task is triggered to proceed to the next step. The host computer software includes: The first device self-test unit 11 is used to send a device self-test command to the embedded control device 2. The embedded control device 2 will perform a self-test on the pin status, memory chip and voltage in the device and send back the self-test data. The first device self-test unit 11 processes the sent-back self-test data and displays it in the message window of the host computer 1. The first chip ID reading unit 12 is used to send a chip ID (Identification) reading instruction to the embedded control device 2. The embedded control device 2 will use the JTAG interface to read the ID of the control chip on the ATSU board 3 and send the ID data back. The first chip ID reading unit 12 processes the sent chip ID data and displays it in the message window of the host computer 1. The first EEPROM reading unit 13 is used to send EEPROM (Electrically Erasable Programmable Read-Only Memory) read instructions to the embedded control device 2. The embedded control device 2 will use the JTAG interface to control the control chip on the ATSU board 3, use the control chip to perform EEPROM read operations, and send back the read EEPROM data. Then, the first EEPROM reading unit 13 will perform integrity checks on the sent back EEPROM data and generate EEPROM data file one. If the data is incomplete, the EEPROM read task will be repeated. The first EEPROM writing unit 14 is used to read the second EEPROM data file stored in the host computer 1, unpack the second EEPROM data file, send an EEPROM write command to the embedded control device 2 so that the embedded control device 2 is ready to receive the second EEPROM data file. After sending the second EEPROM data file to the embedded control device 2, it waits for the embedded control device 2 to respond and confirm that the EEPROM data file writing is complete. If the writing fails, the EEPROM writing task will be repeated. The first FLASH reading unit 15 is used to send FLASH (Flash Memory) read instructions to the embedded control device 2. The embedded control device 2 will use the JTAG interface to control the control chip on the ATSU board 3 and use the control chip to perform FLASH read operations. Since the FLASH data is large, it will be transmitted in packets. The read FLASH data packets will be sent back. The first FLASH reading unit 15 will perform an integrity check on the returned FLASH data packets and generate FLASH data packet file one. If the data is incomplete, the FLASH read task will be repeated. After the FLASH data packet file one is received, the FLASH data packet file one will be integrated to generate a FLASH data file. The first FLASH writing unit 16 is used to read the second FLASH data packet file stored in the host computer 1, and send a FLASH write command to the embedded control device 2 so that the embedded control device 2 is ready to receive the second FLASH data packet file. After sending the second FLASH data packet file to the embedded control device 2, it waits for the device to respond and confirm that the FLASH data packet file writing is complete. It waits for all second FLASH data packets to be written.

[0030] In some embodiments, please refer to Figure 4 The embedded control device 2 is equipped with lower-level software, which is programmed into the control chip (STM32 module 21) of the embedded control device 2. It communicates with the upper-level software on the upper-level computer 1 via a serial port. It executes different tasks by receiving different instructions from the upper-level computer 1. The JTAG interface control adopts an active lookup table method, that is, all operations are stored in a list in advance in the form of data. Different list segments are read according to different task requirements to control the JTAG interface. At the same time, the data in the list can be actively modified according to different task requirements to adapt to different read and write tasks. The lower-level software includes: The second device self-test unit 27 is used to perform a self-test and record the pin status, memory chip and voltage of the device after receiving the device self-test command sent by the host computer software, and to integrate the self-test data and send it back. The second chip ID reading unit 28 is used to receive the chip ID reading instruction sent by the host computer software. The internal program will search for the corresponding list segment one, control the ATSU board 3 to perform the chip ID reading operation according to the list segment one, and read the corresponding chip ID according to the data in the list segment one. After reading, the chip ID data will be integrated and sent to the host computer software. The second EEPROM reading unit 29 is used to receive the EEPROM reading instruction sent by the host computer software. The internal program will search for the corresponding list segment two, control the ATSU board 3 to perform the EEPROM reading operation according to the list segment two, and read the corresponding EEPROM data file one according to the data in the list segment two. After waiting for the EEPROM data file one to complete the full verification, the EEPROM data file one is integrated and sent to the host computer software. The second EEPROM writing unit 210 is used to receive the EEPROM write instruction sent by the host computer software, receive the EEPROM data file 2 sent by the host computer 1, and the internal program will find the corresponding list segment 3. According to the list segment 3, it controls the ATSU board 3 to perform the EEPROM write operation, and writes the EEPROM according to the data in the list segment 3 and the EEPROM data file 2. After waiting for the EEPROM data file 2 to be written, it sends the EEPROM data file write completion signal to the host computer 1. The second FLASH reading unit 211 is used to receive the FLASH reading instruction sent by the host computer software. Its internal program searches for the corresponding list segment four, controls the ATSU board 3 to perform the FLASH reading operation based on list segment four, reads the corresponding FLASH data packet file one based on the data in list segment four, integrates the read data, waits for the FLASH data to complete verification, integrates the FLASH data packet file one into a FLASH data file, and sends the FLASH data file to the host computer 1. In other embodiments, the FLASH data is transmitted in packets, with each packet containing 512 bytes of data; a data integrity verification and automatic retransmission mechanism is implemented; a binary format FLASH data file is generated; and a segmented FLASH data packet file is generated.

[0031] The second FLASH writing unit 212 is used to receive the FLASH writing instruction sent by the host computer software, receive the FLASH data packet file two sent by the host computer software, and the internal program will find the corresponding list segment five. According to the list segment five, it controls the ATSU board 3 to perform the FLASH writing operation, and writes the FLASH data packet file two according to the data in the list segment five. After waiting for the FLASH data packet file two to be written, it sends the FLASH data file writing completion signal to the host computer 1.

[0032] In some other implementations, the JTAG interface control chain includes three levels of processing: the ATSU board 1 main processor, which directly operates the onboard EEPROM and FLASH; the signal conditioning circuit matches the JTAG level with the memory level; and the onboard memory includes: four NOR FLASH memories, each with a capacity of not less than 16Mb; one EEPROM memory with a capacity of not less than 128Kb; and all memories are accessed through the processor's internal bus.

[0033] Please see Figure 5 This application discloses a data read / write method for an ATSU board 3 based on a JTAG interface, using the system disclosed in the above embodiments. The method includes the following steps: S1. Equipment self-test: Performs self-test on the equipment according to the equipment self-test command of the host computer 1, and sends back the self-test data; S2. Chip ID Reading: Read the chip ID data of ATSU board 3 according to the chip ID reading instruction of host computer 1, and send the chip ID data back; S3, EEPROM Read: Read the EEPROM data file 1 from ATSU board 3 according to the EEPROM read instruction from host computer 1, and return the EEPROM data file 1. S4, EEPROM writing: Write the EEPROM data file 2 to the ATSU board 3 according to the EEPROM writing instruction of the host computer 1, and send the EEPROM writing completion signal to the host computer 1; S5, FLASH Read: Read the FLASH data file 1 of ATSU board 3 according to the FLASH read command of host computer 1, and send the FLASH data file 1 back; S6. FLASH Writing: Write the FLASH data file 2 to the ATSU board 3 according to the FLASH writing instruction of the host computer 1, and send the FLASH writing completion signal to the host computer 1.

[0034] Please see Figures 5-7 In another embodiment, In step S1: After the host computer 1 sends the device self-test command to the embedded control device 2, the embedded control device 2 will perform a self-test on the pin status, memory chip and voltage in the device, and send back the self-test data. The host computer 1 processes the sent-back self-test data and displays it in the message window of the host computer 1. In step S2: After the host computer 1 sends the chip ID reading instruction to the embedded control device 2, the device will find the corresponding list segment 1, use the JTAG interface to control the control chip on the ATSU board 3, use the control chip in combination with list segment 1 to perform the chip ID reading operation on the ATSU board 3, and send the chip ID data back. The host computer 1 processes the sent chip ID data and displays it in the message window of the host computer 1. In step S3: After the host computer 1 sends the EEPROM read command to the embedded control device 2, the device will find the corresponding list segment two, use the JTAG interface to control the control chip on the ATSU board 3, and use the control chip in conjunction with list segment two to perform EEPROM read operation on the ATSU board 3. According to the data in list segment two, the corresponding EEPROM data is read and the read EEPROM data is sent back. Then, the EEPROM data is checked for completeness and EEPROM data file one is generated. If the data is incomplete, the EEPROM read task will be repeated. In step S4: the EEPROM data file 2 saved by the host computer 1 is read and unpacked. An EEPROM write command is sent to the embedded control device 2 so that the device is ready to receive the EEPROM data file 2. The embedded control device 2 will find the corresponding list segment 3, use the JTAG interface to control the control chip on the ATSU board 3, and use the control chip in conjunction with list segment 3 to perform the EEPROM write operation on the ATSU board 3. The corresponding EEPROM data file 2 is written according to the data in list segment 3. After waiting for the EEPROM data file 2 to be written, the EEPROM write completion signal is sent to the host computer 1. In step S5: After the host computer 1 sends the FLASH read command to the embedded control device 2, the device will find the corresponding list segment four, use the JTAG interface to control the control chip on the ATSU board 3, and use the control chip in conjunction with list segment four to perform FLASH read operation on the ATSU board 3. According to the data in list segment four, the corresponding EEPROM data is read, and the read FLASH data packet is sent back in a packetized form. Then, the FLASH data packet is checked for completeness and FLASH data packet file one is generated. If the data is incomplete, the FLASH read task will be repeated. After the FLASH data packet file one is received, the FLASH data packet file one is integrated to generate a FLASH data file, and the FLASH data file is sent to the host computer 1. In step S6: Read the FLASH data packet file two saved by the host computer 1, and send a FLASH write command to the embedded control device 2 so that the device is ready to receive the FLASH data packet file two. The embedded control device 2 will find the corresponding list segment five, use the JTAG interface to control the control chip on the ATSU board 3, and use the control chip in conjunction with list segment five to perform a FLASH write operation on the ATSU board 3. Write the corresponding FLASH data packet file two according to the data in list segment five, wait for the FLASH data to be written, and send the FLASH write completion signal to the host computer 1.

[0035] This application discloses a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it performs the ATSU board data read / write method based on the JTAG interface disclosed in the above embodiments.

[0036] This application also discloses an application publishing platform, which is used to publish computer program products. When the computer program products are run on a computer, the computer performs some or all of the steps of the methods described in the above method embodiments.

[0037] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0038] In the various embodiments of this application, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0039] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they can be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0040] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0041] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-accessible memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several requests to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute some or all of the steps of the methods described in the various embodiments of this application.

[0042] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0043] Based on the disclosure and teachings of the foregoing specification, those skilled in the art can make changes and modifications to the above embodiments. Therefore, the invention is not limited to the specific embodiments described above, and any obvious improvements, substitutions, or modifications made by those skilled in the art based on this invention are within the scope of protection of this invention. Furthermore, although some specific terms are used in this specification, these terms are only for convenience of explanation and do not constitute any limitation on the invention.

Claims

1. An ATSU board data read / write system based on a JTAG interface, characterized in that, include: The host computer (1) and the embedded control device (2) include an STM32 module (21), an FPGA module (22), a JTAG module (23) and a first relay module (24). The host computer (1) and the FPGA module (22) are respectively connected to the STM32 module (21). The JTAG module (23) is respectively connected to the FPGA module (22) and the first relay module (24). The FPGA module (22) is connected to the first relay module (24). The first relay module (24) is used to control the connection and disconnection between the JTAG module (23) and the ATSU board (3).

2. The ATSU board data read / write system based on the JTAG interface as described in claim 1, characterized in that, The embedded control device (2) further includes a power module (25) and a second relay module (26). The power module (25) is electrically connected to the STM32 module (21), the FPGA module (22) and the second relay module (26) respectively. The FPGA module (22) is communicatively connected to the second relay module (26). The second relay module (26) is used to control the connection and disconnection between the power module (25) and the ATSU board (3).

3. The ATSU board data read / write system based on the JTAG interface as described in claim 1, characterized in that, The host computer (1) includes: The first device self-test unit (11) is used to send device self-test instructions to the embedded control device (2), and to process the returned self-test data and display it in the message window of the host computer (1). The first chip ID reading unit (12) is used to send chip ID reading instructions to the embedded control device (2), and after processing the returned chip ID data, it displays it in the message window of the host computer (1).

4. The ATSU board data read / write system based on the JTAG interface as described in claim 3, characterized in that, The host computer (1) also includes: The first EEPROM reading unit (13) is used to send EEPROM reading instructions to the embedded control device (2), and generate EEPROM data file 1 after performing integrity checks on the returned EEPROM data. If the data is incomplete, the EEPROM reading task is repeated. The first EEPROM writing unit (14) is used to read EEPROM data file 2, unpack EEPROM data file 2, send EEPROM writing instructions to the embedded control device (2), make the device ready to receive EEPROM data file 2, send EEPROM data file 2 to the embedded control device (2), and wait for the device to respond and confirm that the EEPROM data file writing is complete. The first FLASH reading unit (15) is used to send FLASH reading instructions to the embedded control device (2), and after performing integrity checks on the returned FLASH data packets, it generates FLASH data packet file one. If the data is incomplete, the FLASH reading task is repeated, and the data packet file one is waited to be received. The data packet file is then integrated to generate a FLASH data file. The first FLASH writing unit (16) is used to read FLASH data packet file 2, send FLASH writing instructions to the embedded control device (2), make the device ready to receive FLASH data packet file 2, send FLASH data packet file 2 to the embedded control device (2), and wait for the device to respond and confirm that the FLASH data packet file writing is complete.

5. The ATSU board data read / write system based on the JTAG interface as described in claim 4, characterized in that, The embedded control device (2) includes: The second device self-test unit (27) is used to receive the device self-test command, perform a self-test and record the pin status, memory chip and voltage in the device, and integrate the self-test data and send it back. The second chip ID reading unit (28) is used to receive the chip ID reading instruction, find the corresponding list segment one, control the ATSU board (3) to perform the chip ID reading operation according to the list segment one, and read the corresponding chip ID according to the data in the list segment one. After reading, the chip ID data is sent to the host computer (1).

6. The ATSU board data read / write system based on the JTAG interface as described in claim 5, characterized in that, The embedded control device (2) further includes: The second EEPROM reading unit (29) is used to receive the EEPROM reading instruction, find the corresponding list segment two, control the ATSU board (3) to perform the EEPROM reading operation according to the list segment two, and read the corresponding EEPROM data file one according to the data in the list segment two, wait for the EEPROM data file one to complete the full verification, and send the EEPROM data file one to the host computer (1). The second EEPROM writing unit (210) is used to receive the EEPROM writing instruction, then receive the EEPROM data file two sent by the host computer (1), find the corresponding list segment three, control the ATSU board (3) to perform the EEPROM writing operation according to the list segment three, and write the EEPROM according to the data in the list segment three in combination with the EEPROM data file two, wait for the EEPROM data file two to be written, and send the EEPROM data file writing completion signal to the host computer (1). The second FLASH reading unit (211) is used to receive FLASH reading instructions, find the corresponding list segment four, control the ATSU board (3) to perform FLASH reading operation according to list segment four, and read the corresponding FLASH data packet file one according to the data in list segment four, wait for the FLASH data to complete the full verification, integrate the FLASH data packet file one into a FLASH data file, and send the FLASH data file to the host computer (1). The second FLASH writing unit (212) is used to receive the FLASH writing instruction, then receive the FLASH data packet file two sent by the host computer (1), find the corresponding list segment five, control the ATSU board (3) to perform the FLASH writing operation according to the list segment five, and write the FLASH according to the data in the list segment five combined with the FLASH data packet file two, wait for the FLASH data packet file two to be written, and send the FLASH data file writing completion signal to the host computer (1).

7. The ATSU board data read / write system based on the JTAG interface as described in claim 1, characterized in that, The first relay module (24) is connected to the ATSU board (3) through the interface module (4), and the second relay module (26) is connected to the ATSU board (3) through the interface board (5); the FPGA module (22) is also connected to the first relay module (24) through the JTAG loopback line (6), wherein the signal output terminal of the JTAG module (23) is selectively connected to the interface module (4) or the JTAG loopback line (6) through the first relay module (24).

8. A data read / write method for an ATSU board based on a JTAG interface, characterized in that, The system described in any one of claims 1 to 7 comprises the following steps: S1. Equipment self-test: Perform self-test on the equipment according to the equipment self-test command of the host computer (1) and send back the self-test data; S2, Chip ID Reading: Read the chip ID data of ATSU board (3) according to the chip ID reading instruction of the host computer (1), and send the chip ID data back; S3, EEPROM read: Read the EEPROM data file 1 of ATSU board (3) according to the EEPROM read instruction of the host computer (1), and return the EEPROM data file 1; S4, EEPROM writing: Write the EEPROM data file 2 to the ATSU board (3) according to the EEPROM writing instruction of the host computer (1), and send the EEPROM writing completion signal to the host computer (1). S5, FLASH read: Read the FLASH data file 1 of ATSU board (3) according to the FLASH read instruction of the host computer (1), and send the FLASH data file 1 back; S6, FLASH writing: Write the FLASH data file 2 to the ATSU board (3) according to the FLASH writing instruction of the host computer (1), and send the FLASH writing completion signal to the host computer (1).

9. The ATSU board data read / write method based on the JTAG interface as described in claim 8, characterized in that, In step S1: After the host computer (1) sends the device self-test command to the embedded control device (2), the embedded control device (2) will perform a self-test on the pin status, memory chip and voltage in the device and send back the self-test data. The host computer (1) processes the self-test data and displays it in the message window of the host computer (1). In step S2: After the host computer (1) sends the chip ID reading instruction to the embedded control device (2), the device will find the corresponding list segment one, use the JTAG interface to control the control chip on the ATSU board (3), use the control chip in combination with list segment one to perform chip ID reading operation on the ATSU board (3), and send back the chip ID data. The host computer (1) processes the sent chip ID data and displays it in the message window of the host computer (1). In step S3: After the host computer (1) sends the EEPROM read instruction to the embedded control device (2), the device will find the corresponding list segment two, use the JTAG interface to control the control chip on the ATSU board (3), use the control chip in combination with list segment two to perform EEPROM read operation on the ATSU board (3), read the corresponding EEPROM data according to the data in list segment two, and send back the read EEPROM data. Then, the EEPROM data is completely checked and EEPROM data file one is generated. If the data is incomplete, the EEPROM read task will be repeated. In step S4: the EEPROM data file 2 saved by the host computer (1) is read and the EEPROM data file 2 is unpacked. The EEPROM write command is sent to the embedded control device (2) so that the device is ready to receive the EEPROM data file 2. The embedded control device (2) will find the corresponding list segment 3 and use the JTAG interface to control the control chip on the ATSU board (3). The control chip is used in conjunction with the list segment 3 to perform the EEPROM write operation on the ATSU board (3). The corresponding EEPROM data file 2 is written according to the data in the list segment 3. The EEPROM data file 2 is waited for to be written and the EEPROM write completion signal is sent to the host computer (1). In step S5: After the host computer (1) sends the FLASH read instruction to the embedded control device (2), the device will find the corresponding list segment four, use the JTAG interface to control the control chip on the ATSU board (3), use the control chip in combination with list segment four to perform FLASH read operation on the ATSU board (3), read the corresponding EEPROM data according to the data in list segment four, and use the packet form to send back the read FLASH data packet, then check the FLASH data packet completely and generate FLASH data packet file one. If the data is incomplete, the FLASH read task will be repeated. After waiting for FLASH data packet file one to be received, FLASH data packet file one will be integrated to generate FLASH data file, and FLASH data file will be sent to the host computer (1). In step S6: the FLASH data packet file 2 saved by the host computer (1) is read, and the FLASH write instruction is sent to the embedded control device (2) so that the device is ready to receive the FLASH data packet file 2. The embedded control device (2) will find the corresponding list segment 5, use the JTAG interface to control the control chip on the ATSU board (3), use the control chip in combination with list segment 5 to perform FLASH write operation on the ATSU board (3), write the corresponding FLASH data packet file 2 according to the data in list segment 5, wait for the FLASH data to be written, and send the FLASH write completion signal to the host computer (1).

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 9.

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