A pulse width high-precision measuring device and measuring method
By accurately measuring pulse width using a calibration loop and a reference clock counter assembly, the problem of high-precision measurement error in existing technologies is solved, achieving simple and efficient nanosecond-level measurement accuracy and simplifying hardware design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN GREAT LEO MICROELECTRONICS CO LTD
- Filing Date
- 2025-01-22
- Publication Date
- 2026-07-24
AI Technical Summary
Existing technologies struggle to achieve high-precision pulse width measurement, especially in measuring 100.2ns high-level pulses where significant errors exist. Furthermore, existing solutions increase hardware design complexity or fail to guarantee nanosecond-level measurement accuracy.
The system employs components such as a calibration loop, a reference clock counter, a calibration loop clock counter, an input signal capture latch group, and a capture result encoder. The calibration loop generates a periodic clock signal, and by combining the reference clock and the calibration loop clock count, the system accurately measures the time difference between the edge of the input signal and the edge of the reference clock, and calculates the pulse width.
It achieves high-precision pulse width measurement, with a simple structure and easy operation. The measurement error is mainly determined by the reference clock error, avoiding complex DLL locking and system clock frequency limitations. The measurement accuracy can reach the nanosecond level.
Smart Images
Figure CN122449221A_ABST
Abstract
Description
Technical Field
[0001] This invention mainly relates to the field of pulse width measurement technology, specifically a high-precision pulse width measurement device and method. Background Technology
[0002] Traditional pulse width measurement techniques typically use the system clock cycle as the minimum resolution to measure pulse width. However, some applications require more precise pulse width measurements, such as 100.2ns high-level pulses. Achieving this through higher system clock frequencies is difficult; for example, achieving a resolution of 0.2ns would require a system clock of at least 5GHz.
[0003] Some practitioners have proposed US patent US10177747B2 and Chinese patent CN202210191682. These technical solutions all use an inaccurate clock (HRCLK) to measure the pulse width, which will introduce a large measurement error.
[0004] Another practitioner has proposed a Chinese patent CN202310409134, which requires a clock higher than the system clock, such as a PLL clock, for preprocessing the signal to be measured, increasing the complexity of the software and hardware design.
[0005] Another industry practitioner has proposed Chinese patent CN202410023249. This technical solution does not describe how the duty cycle of the second enable signal is obtained. In fact, the clock duty cycle in the chip cannot be measured in real time, and the pulse measurement accuracy cannot be guaranteed to reach the nanosecond level.
[0006] In conclusion, a device and method that can support high-resolution pulse width measurement is still needed. Summary of the Invention
[0007] The technical problem to be solved by this invention is to provide a high-precision pulse width measuring device and method that is simple in structure, easy to operate, has high measurement accuracy, and good stability, in response to the technical problems existing in the prior art.
[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0009] A high-precision pulse width measuring device, comprising:
[0010] The calibration loop is used to generate the calibration loop clock.
[0011] A reference clock counter, used to count a reference clock;
[0012] The calibration loop clock counter is used to count the calibration loop clock.
[0013] An input signal capture latch group is used to latch the input signal under the control of a reference clock;
[0014] The capture result encoder is used to encode the output of the input signal capture latch and convert it into the number of delay units.
[0015] As a further improvement to the device of the present invention: the calibration loop is composed of N identical delay units, connected end to end by an inverter to form a loop, which is used to generate a periodic clock signal as the calibration loop clock.
[0016] As a further improvement to the device of the present invention, it also includes a calibration loop enable register, which, when configured to be enabled, causes the calibration loop clock counter and the reference clock counter to start counting respectively; when configured to be disabled, the calibration loop, the calibration loop clock counter and the reference clock counter do not work.
[0017] As a further improvement to the device of the present invention: the reference clock counter is composed of an I-bit register, with a period of T... REF Driven by a reference clock signal, it counts continuously until it equals a certain set value P.
[0018] As a further improvement to the device of the present invention: the counting method is to add 1 to each reference clock.
[0019] As a further improvement to the device of the present invention, it also includes a reference period register, which is used to set the value of the reference period register; when the reference clock counter is equal to the value of the reference period register, the counting stops.
[0020] As a further improvement to the device of the present invention: the calibration loop clock counter is composed of a K-bit register, which counts continuously under the drive of the calibration loop clock until the reference clock counter is equal to the set value P.
[0021] As a further improvement to the device of the present invention, it also includes a calibration result register, which is used to continuously calibrate the calibration loop clock period; when the reference clock counter is equal to the set value P, the result of the calibration loop clock counter is sent to the calibration result register, and the calibration loop clock counter and the reference clock counter start counting again.
[0022] As a further improvement to the device of the present invention: the input signal edge catcher consists of a delay chain, M registers, and a clock counter, wherein the delay chain consists of M delay units identical to the calibration loop; the input signal is connected to the input terminal of the first delay unit of the delay chain; under the control of the reference clock, the M registers latch the value at the output terminal of each delay unit. The clock counter continuously counts the reference clock.
[0023] As a further improvement to the device of the present invention: the capture result encoder encodes the latch values of L registers.
[0024] The present invention further provides a measurement method based on the above-mentioned high-precision pulse width measurement device, the steps of which include:
[0025] Step S100: Calibration delay; After power-on, the calibration loop generates a periodic calibration loop clock; The reference clock counter and the calibration loop clock counter count continuously under the reference clock and calibration loop clock respectively; When the reference clock counter equals the set value P, the reference clock counter and the calibration loop clock counter stop counting or latch the current value of the calibration loop clock counter and start counting again;
[0026] Step S200: Measure the time difference between the edge of the input signal and the edge of the reference clock; connect the input signal to the input terminal of the first delay unit of the delay chain; latch the output of the delay chain to record how many delay units have passed between the edge of the input signal and the rising edge of the reference clock; capture the result encoder to encode the output of the delay chain to obtain the number of delay units reflecting the delay between the edge of the input signal and the rising edge of the reference clock.
[0027] Step S300: Measure the pulse width; First, measure the time difference between two consecutive edges of the input signal, SigEdgeA and SigEdgeB, and their respective subsequent reference clock edges, ClkEdgeA and ClkEdgeB, as DelayA and DelayB, respectively. The time difference encoding results are DA and DB, respectively. When the two reference clock edges, ClkEdgeA and ClkEdgeB, occur, the values of the clock counter in the input signal edge catcher, CntA and CntB, are recorded by software or circuitry, respectively. The delay between two consecutive edges of the input signal is the high pulse or low pulse width of the input signal.
[0028] As a further improvement to the method of the present invention: the pulse width is expressed as:
[0029] (DA-DB)*T Unit +T REF *(CntB-CntA)=(DB-DA)*T Loop / 2N+T REF *(CntB-CntA).
[0030] Compared with the prior art, the advantages of the present invention are as follows:
[0031] 1. The pulse width high-precision measuring device and method of the present invention has a simple structure, is easy to operate, has high measurement accuracy, and good stability. The whole scheme does not require the use of complex DLL to lock other clocks, making the structure very simple. Moreover, there is no limitation on the minimum operating frequency of the system clock, and the system clock frequency can be changed arbitrarily.
[0032] 2. In the pulse width high-precision measurement device and method of the present invention, during the calculation process of signal pulse width measurement, only the delay calculation of the input signal edge and the reference clock edge requires the use of a lower precision calibration loop clock; at other times, the reference clock is used for counting. Therefore, the pulse width measurement error mainly comes from the reference clock error. When the reference clock accuracy is high, the pulse width measurement result can be more accurate. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the structural principle of the present invention in a specific embodiment.
[0034] Figure 2 This is a schematic diagram of the calibration loop structure before optimization.
[0035] Figure 3 This is a schematic diagram of the optimized calibration loop structure in a specific embodiment of the present invention.
[0036] Figure 4 This is a schematic diagram of the input signal and reference clock timing in a specific embodiment of the present invention.
[0037] Figure 5 This is a schematic diagram of the output of the delay chain in the input signal edge catcher at time ClkEdgeA in a specific embodiment of the present invention.
[0038] Figure 6 This is a schematic diagram of the output of the delay chain in the input signal edge catcher at time ClkEdgeB in a specific embodiment of the present invention. Detailed Implementation
[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0040] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0042] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0043] like Figures 1 to 6 As shown, the present invention provides a high-precision pulse width measurement device, comprising:
[0044] A calibration loop is used to generate a calibration loop clock; in specific application examples, the calibration loop is composed of multiple delay units and other units.
[0045] A reference clock counter, used to count a reference clock;
[0046] The calibration loop clock counter is used to count the calibration loop clock.
[0047] An input signal capture latch group is used to latch the input signal under the control of a reference clock;
[0048] The capture result encoder is used to encode the output of the input signal capture latch and convert it into the number of delay units.
[0049] In a specific application example, the calibration loop consists of N identical delay units connected end-to-end by inverters to form a loop, which can generate a periodic clock signal, hereinafter referred to as the calibration loop clock. In a preferred embodiment, N is a power of 2.
[0050] In specific application examples, to reduce power consumption, the present invention further includes a calibration loop enable register. When configured to be enabled, the calibration loop clock counter and the reference clock counter each begin counting. When configured to be disabled, the calibration loop, the calibration loop clock counter, and the reference clock counter do not operate.
[0051] In a specific application example, the reference clock counter consists of an I-bit register and can operate with a period of T.REF Driven by a reference clock signal, it continuously counts until it equals a certain set value P. In a preferred embodiment, the counting method can increment by 1 for each reference clock.
[0052] In a specific application example, the present invention further includes a reference period register, the value of which can be set by software or other means. Counting stops when the reference clock counter equals the value of the reference period register. In other embodiments, the reference period register may also use a fixed reference period value, depending on actual needs.
[0053] In a specific application example, the calibration loop clock counter consists of a K-bit register, which can continuously count under the drive of the calibration loop clock until the reference clock counter equals the set value P. As a preferred embodiment, depending on actual needs, the counting method can increment by 1 for each calibration loop clock cycle.
[0054] In a specific application example, to continuously calibrate the calibration loop clock cycle, the present invention further includes a calibration result register. When the reference clock counter equals the set value P, the result of the calibration loop clock counter is sent to the calibration result register, and both the calibration loop clock counter and the reference clock counter restart counting.
[0055] In a specific application example, the input signal edge catcher consists of a delay chain, M registers, and a clock counter. The delay chain comprises M delay units identical to those in the calibration loop. The input signal is connected to the input of the first delay unit in the delay chain. Under the control of a reference clock, the M registers latch the value at the output of each delay unit. The clock counter continuously counts the reference clock. As a preferred embodiment, M is a power of 2, depending on actual needs.
[0056] In a specific application example, the capture result encoder encodes the latched values of L registers. The encoding bit width can be...
[0057] Working principle: After power-on, the calibration loop clock counter and the reference clock counter of this invention each begin counting. When the value of the reference clock counter equals the set value P, the current value C of the calibration loop clock counter reflects the period T of the calibration loop clock over a recent period. LOOP .
[0058] T Loop =P*T REF / C, where the reference clock period T REF It is known.
[0059] When N is large and the measurement accuracy requirement is not very high, the delay of the calibration loop inverter can be ignored. Therefore, the delay time of one delay unit is:
[0060] T Unit =T Loop / 2N=P*T REF / C / 2N
[0061] When high measurement accuracy is required, the measurement accuracy of the unit delay can be further improved through improved technical solutions. That is, a selection path is added to the calibration loop, and the delay of the inverter and the selection path itself is eliminated by selecting different chain lengths.
[0062] The optimized delay unit delay measurement and calculation process is as follows:
[0063] Step S10: Select a calibration loop consisting of N delay units and calculate the clock delay T of the calibration loop at this time. Loop1 ;
[0064] Step S20: Select a calibration loop consisting of X delay units and calculate the clock delay T of the calibration loop at this time. Loop2 ;
[0065] Step S30: Calculate the delay TUnit for each delay unit = (T Loop1 -T Loop2 ) / 2(NX).
[0066] The present invention further provides a method based on the above-described apparatus, the steps of which include: Detailed implementation:
[0067] Step S100: Calibrate the delay unit. The calibration loop consists of N identical delay units connected end-to-end by inverters to form a loop. After power-on, the calibration loop generates a periodic calibration loop clock. The reference clock counter and the calibration loop clock counter count continuously under the reference clock and calibration loop clock, respectively. When the reference clock counter equals the set value P, both the reference clock counter and the calibration loop clock counter stop counting (at this time, the current value of the calibration loop clock counter is C) or the current value of the calibration loop clock counter is latched and counting restarts. Based on the reference clock period, P, and the current value C of the calibration loop clock counter, the calibration loop clock period T can be calculated. Loop =P*T REF / C, and thus the delay T of each delay unit can be calculated. Unit =T Loop / N. When N is large, the inverter delay can be ignored, so the delay time of the delay unit can be determined by the reference clock, i.e., calibration.
[0068] Step S200: Measure the time difference between the input signal edge and the reference clock edge. The input signal is connected to the input terminal of the first delay unit of the delay chain. When the input signal is stable, the output level of all delay units is 0 or 1. When the input signal has a rising or falling edge, the input signal edge propagates in the delay chain (taking 8 delay units as an example). At a certain rising edge of the reference clock, the output of the delay chain (i.e., the output from the first delay unit to the last delay unit) may be 0011111 (falling edge) or 1111000 (rising edge). Therefore, latching the delay chain output can record how many delay units have passed between the input signal edge and the rising edge of the reference clock. The capture result encoder is used to encode the delay chain output to obtain the number of delay units reflecting the delay from the input signal edge to the rising edge of the reference clock.
[0069] Step S300: Measure the pulse width. First, measure the time difference between two consecutive edges of the input signal (SigEdgeA and SigEdgeB) and their respective subsequent reference clock edges (ClkEdgeA and ClkEdgeB), which are DelayA and DelayB, respectively. The time difference encoding results are DA and DB, respectively. When the two reference clock edges (ClkEdgeA and ClkEdgeB) occur, the values CntA and CntB of the clock counter in the input signal edge catcher are recorded by software or circuitry, respectively. The delay between two consecutive edges of the input signal is the high or low pulse width of the input signal, which can be expressed as:
[0070] (DA-DB)*T Unit +T REF *(CntB-CntA)=(DB-DA)*T Loop / 2N+T REF *(CntB-CntA).
[0071] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.
Claims
1. A high-precision pulse width measuring device, characterized in that, include: The calibration loop is used to generate the calibration loop clock. A reference clock counter, used to count a reference clock; The calibration loop clock counter is used to count the calibration loop clock. An input signal capture latch group is used to latch the input signal under the control of a reference clock; The capture result encoder is used to encode the output of the input signal capture latch and convert it into the number of delay units.
2. The high-precision pulse width measuring device according to claim 1, characterized in that, The calibration loop consists of N identical delay units connected end-to-end by inverters to form a loop, which is used to generate a periodic clock signal as the calibration loop clock.
3. The high-precision pulse width measuring device according to claim 1, characterized in that, It also includes a calibration loop enable register, which, when configured to be enabled, causes the calibration loop clock counter and the reference clock counter to start counting; when configured to be disabled, the calibration loop, the calibration loop clock counter, and the reference clock counter do not operate.
4. The high-precision pulse width measuring device according to claim 1, characterized in that, The reference clock counter consists of an I-bit register with a period of T. REF Driven by a reference clock signal, it counts continuously until it equals a certain set value P.
5. The high-precision pulse width measuring device according to claim 4, characterized in that, The counting method increments by 1 for each reference clock.
6. The high-precision pulse width measuring device according to any one of claims 1-5, characterized in that, It also includes a reference period register, which is used to set the value of the reference period register; when the reference clock counter is equal to the value of the reference period register, the counting stops.
7. The high-precision pulse width measuring device according to any one of claims 1-5, characterized in that, The calibration loop clock counter consists of a K-bit register and counts continuously under the drive of the calibration loop clock until the reference clock counter equals the set value P.
8. The high-precision pulse width measuring device according to any one of claims 1-5, characterized in that, It also includes a calibration result register, which is used to continuously calibrate the calibration loop clock cycle; When the reference clock counter equals the set value P, the result of the calibration loop clock counter is sent to the calibration result register, and the calibration loop clock counter and the reference clock counter start counting again.
9. The high-precision pulse width measuring device according to any one of claims 1-5, characterized in that, The input signal edge catcher consists of a delay chain, M registers, and a clock counter. The delay chain consists of M delay units identical to the calibration loop. The input signal is connected to the input terminal of the first delay unit of the delay chain. Under the control of the reference clock, M registers latch the value at the output of each delay unit, and the clock counter continuously counts the reference clock.
10. The high-precision pulse width measuring device according to any one of claims 1-5, characterized in that, The capture result encoder encodes the latch values of L registers.
11. A measurement method based on the pulse width high-precision measuring device according to any one of claims 1-10, characterized in that the steps include... include: Step S100: Calibration delay; After power-on, the calibration loop generates a periodic calibration loop clock; The reference clock counter and the calibration loop clock counter count continuously under the reference clock and calibration loop clock respectively; When the reference clock counter equals the set value P, the reference clock counter and the calibration loop clock counter stop counting or latch the current value of the calibration loop clock counter and start counting again; Step S200: Measure the time difference between the edge of the input signal and the edge of the reference clock; connect the input signal to the input terminal of the first delay unit of the delay chain; latch the output of the delay chain to record how many delay units have passed between the edge of the input signal and the rising edge of the reference clock; capture the result encoder to encode the output of the delay chain to obtain the number of delay units reflecting the delay between the edge of the input signal and the rising edge of the reference clock. Step S300: Measure the pulse width; First, measure the time difference between two consecutive edges of the input signal, SigEdgeA and SigEdgeB, and their respective subsequent reference clock edges, ClkEdgeA and ClkEdgeB, as DelayA and DelayB, respectively. The time difference encoding results are DA and DB, respectively. When the two reference clock edges, ClkEdgeA and ClkEdgeB, occur, the values of the clock counter in the input signal edge catcher, CntA and CntB, are recorded by software or circuitry, respectively. The delay between two consecutive edges of the input signal is the high pulse or low pulse width of the input signal.
12. The measurement method according to claim 11, characterized in that, The pulse width is expressed as: (DA-DB)*T Unit +T REF *(CntB-CntA)=(DB-DA)*T Loop / 2N+T REF *(CntB-CntA)。