Data transmission method, system and device, storage medium and electronic equipment

Abstract

The application discloses a data transmission method, system and device, a storage medium and an electronic device, and relates to the technical field of chip design. The method comprises the following steps: sending a plurality of data reading requests of a first cache to a second cache, wherein the plurality of data reading requests do not wait for handshake signal transmission between the first cache and the second cache; receiving a target data packet sent by the second cache, wherein the target data packet comprises a reading address corresponding to the target data packet in the second cache, the target data packet is obtained by data reading based on a target data reading request, and the target data reading request is a remaining data reading request obtained after invalid request screening of the plurality of data reading requests; and sending the target data packet to the first cache, wherein the reading address is used for screening a valid data packet from the target data packet, and the target data packet does not wait for the handshake signal transmission.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a data transmission method, system, device, storage medium and electronic device. Background Technology

[0002] In AI inference and computing chip applications, a common architecture design is to have multiple AI processors running the same core simultaneously. To reduce the overall chip area, the industry typically uses a layered approach to instruction memory. The main program is stored in the L2 instruction cache (L2ICACHE), while the L1 instruction cache uses an on-demand fetch mode, thus minimizing the allocation of storage resources.

[0003] Since L1ICACHE and L2ICACHE are independent IP cores, each has its own fixed hardware processing cycle and a large physical layout distance. In addition, the address transmission path and the data return path overlap, resulting in extremely high latency in data transmission between the two instruction caches, with transmission time reaching tens or even hundreds of clock cycles.

[0004] Currently, the industry commonly uses traditional buses such as AXI to implement data exchange between L1ICACHE and L2ICACHE. However, to ensure the accuracy of data exchange, this type of bus protocol requires maintaining a complete queue of outstanding requests. This forces the L1ICACHE to wait for the L2ICACHE to return all data packets corresponding to the initiated data read requests before it can initiate a new data read request. Especially when faced with invalid requests generated by cancellation and retransmission during transmission, it is also necessary to wait for all invalid request data packets to return before initiating a new data read request, resulting in low transmission efficiency and poor resource utilization. Summary of the Invention

[0005] In view of this, this application provides a data transmission method, system, apparatus, storage medium, and electronic device, which can optimize the data interaction process between caches, effectively improve the overall transmission efficiency, and ensure the accuracy of data interaction.

[0006] In a first aspect, this application provides a data transmission method, including: Multiple data read requests from the first cache are sent to the second cache without waiting for a handshake signal to be sent between the first and second caches.

[0007] Receive the target data packet sent by the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests.

[0008] The target data packet is sent to the first buffer. The read address is used to filter valid data packets from the target data packet. The target data packet does not wait for the handshake signal to be sent.

[0009] Secondly, this application provides a data transmission method, including: Send multiple data read requests without waiting for the handshake signal to be sent between the first and second caches; Receive the target data packet in the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests. The target data packet does not wait for the handshake signal to be sent. Based on the read address, filter valid data packets from the target data packets.

[0010] Thirdly, this application provides a data transmission method, including: Receive multiple data read requests, and these multiple data read requests do not wait for the handshake signal to be sent between the first and second caches; Filter out invalid data read requests from multiple data read requests to obtain the target read request; The target data packet is obtained by reading data according to the target read request. The target data packet includes the read address corresponding to the target data packet in the second cache. The read address is used to filter valid data packets from the target data packet.

[0011] Send the target data packet; the target data packet does not wait for the handshake signal to be sent.

[0012] Fourthly, this application provides a data transmission system, including: a first buffer, a second buffer, and a transmission bus; The first buffer is used to send multiple data read requests via the transmission bus, and the multiple data read requests do not wait for the handshake signal to be sent between the first buffer and the second buffer; to receive the target data packet from the second buffer; and to filter valid data packets from the target data packet based on the read address corresponding to the target data packet.

[0013] The second buffer is used to receive multiple data read requests through the transmission bus; to filter invalid requests from the multiple data read requests to obtain the target read request; to read data according to the target read request to obtain the target data packet; and to send the target data packet without waiting for the handshake signal to be sent.

[0014] The transmission bus is used to send multiple data read requests from the first buffer to the second buffer; receive target data packets sent by the second buffer; and send target data packets to the first buffer.

[0015] Fifthly, this application provides a data transmission apparatus, comprising: a first transmitting module, a first receiving module, and a second transmitting module; wherein: The first sending module is configured to send multiple data read requests from the first cache to the second cache, and the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache.

[0016] The first receiving module is configured to receive the target data packet sent by the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests.

[0017] The second sending module is configured to send target data packets to the first buffer, and read the address to filter valid data packets from the target data packets. The target data packets do not wait for the handshake signal to be sent.

[0018] Sixthly, this application provides a data transmission apparatus, which includes a second transmitting module, a second receiving module, and an address verification module; wherein: The second sending module is configured to send multiple data read requests, which do not wait for the handshake signal to be sent between the first and second caches.

[0019] The second receiving module is configured to receive the target data packet in the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests. The target data packet does not wait for the handshake signal to be sent.

[0020] The address verification module is configured to filter valid data packets from target data packets based on the read address.

[0021] In a seventh aspect, this application provides a data transmission apparatus, which includes a third receiving module, a request filtering module, a data acquisition module, and a third sending module; wherein: The third receiving module is configured to receive multiple data read requests, which do not wait for the handshake signal to be sent between the first and second buffers.

[0022] The request filtering module is configured to filter multiple data read requests for invalid requests to obtain the target read request.

[0023] The data acquisition module is configured to read data based on the target read request to obtain the target data packet. The target data packet includes the read address corresponding to the target data packet in the second cache. The read address is used to filter valid data packets from the target data packet.

[0024] The third sending module is configured to send target data packets without waiting for a handshake signal.

[0025] Eighthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect, or the second aspect, or the third aspect.

[0026] Ninthly, this application provides an electronic device including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement the method described in the first aspect, or the second aspect, or the third aspect.

[0027] In view of the above embodiments, this application provides a data transmission method, system, apparatus, storage medium, and electronic device. Multiple data read requests from a first buffer can be continuously sent to a second buffer without waiting for the return of data packets corresponding to previous requests. The second buffer filters invalid requests from the received multiple data read requests, generating and sending back target data packets only based on valid data read requests. The first buffer then uses the read address carried in the target data packet to complete the valid packet filtering. Thus, this solution can achieve uninterrupted transmission of data read requests, effectively improving the data interaction efficiency between buffers, while also improving bus bandwidth and resource utilization. Especially in scenarios with high latency transmission between the first and second buffers and cancellation / retransmission actions, the design of continuous data read request transmission, invalid request filtering, and address verification eliminates the need to wait for all invalid request data packets generated during cancellation / retransmission to return before continuously sending new requests. This avoids invalid requests occupying transmission flow and bus resources, effectively solving the defects of transmission blocking, low efficiency, and poor resource utilization in high-latency scenarios.

[0028] It should be noted that the above content is only a general overview of the technical solution of this application. In order to enable those skilled in the art to clearly understand the core technical means of this application and to accurately implement this solution based on the content disclosed in the specification, the technical details of this application will be described in detail below in conjunction with specific embodiments. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of a cache structure according to an embodiment of this application is shown; Figure 2 A schematic diagram of another cache structure according to an embodiment of this application is shown; Figure 3 A schematic flowchart of a data transmission method provided in an embodiment of this application is shown; Figure 4 A flowchart illustrating another data transmission method provided in an embodiment of this application is shown; Figure 5 A flowchart illustrating another data transmission method provided in an embodiment of this application is shown; Figure 6 This illustration shows a timing diagram of an ordered serial transmission provided in an embodiment of this application; Figure 7 This illustration shows one of the detailed timing diagrams of an ordered serial transmission provided in an embodiment of this application; Figure 8 This is a second detailed schematic diagram of an ordered serial transmission timing provided in an embodiment of this application; Figure 9 This is the third detailed schematic diagram of an ordered serial transmission timing provided in an embodiment of this application; Figure 10 This is illustrated in the fourth detailed schematic diagram of an ordered serial transmission timing provided in an embodiment of this application; Figure 11 This illustration shows a transmission timing diagram of out-of-order and interleaved transmission according to an embodiment of this application; Figure 12 This illustration shows one of the detailed timing diagrams of out-of-order and interleaved transmissions provided in an embodiment of this application; Figure 13 This is a second detailed schematic diagram of out-of-order and interleaved transmission timing provided in an embodiment of this application; Figure 14 This is the third detailed schematic diagram of out-of-order and interleaved transmission timing provided in an embodiment of this application; Figure 15 This is illustrated in the fourth detailed schematic diagram of out-of-order and interleaved transmission timing provided in an embodiment of this application; Figure 16 This illustration shows a transmission timing diagram for canceling retransmission according to an embodiment of this application; Figure 17 This illustration shows one of the detailed timing diagrams for canceling retransmission provided in an embodiment of this application; Figure 18 This is a second detailed schematic diagram of the transmission timing for canceling retransmission provided in an embodiment of this application; Figure 19 This is shown as a third detailed schematic diagram of a transmission timing method for canceling retransmission provided in an embodiment of this application; Figure 20 This is shown as the fourth detailed schematic diagram of the transmission timing for canceling retransmission provided in an embodiment of this application; Figure 21 This illustration shows another transmission timing diagram for canceling retransmission provided in an embodiment of this application; Figure 22 This illustration shows one of the detailed transmission timing diagrams for canceling retransmission provided in an embodiment of this application; Figure 23 This is a second detailed schematic diagram of another transmission timing method for canceling retransmission provided in an embodiment of this application; Figure 24 This is the third detailed schematic diagram of another transmission timing method for canceling retransmission provided in an embodiment of this application; Figure 25 This illustration shows a timing diagram of a first cache low-power sleep mode provided in an embodiment of this application; Figure 26 This illustration shows one of the detailed timing diagrams of a first cache low-power sleep mode provided in an embodiment of this application; Figure 27 This is the second detailed timing diagram of a first cache low-power sleep provided in an embodiment of this application; Figure 28 This is the third detailed timing diagram of a first cache low-power sleep provided in an embodiment of this application; Figure 29 This is the fourth detailed timing diagram of a first cache low-power sleep provided in an embodiment of this application; Figure 30 This illustration shows an execution diagram of a cache provided in an embodiment of this application; Figure 31 This illustration shows a schematic diagram of the structure of a data transmission device provided in an embodiment of this application; Figure 32 This paper shows a schematic diagram of another data transmission device provided in an embodiment of the present application; Figure 33 A schematic diagram of the structure of another data transmission device provided in an embodiment of this application is shown. Detailed Implementation

[0032] The data transmission method provided in this embodiment can be applied to data interaction scenarios between the Level 1 Instruction Cache (L1ICACHE) and the Level 2 Instruction Cache (L2ICACHE) in a multi-AI processor architecture. It is particularly suitable for chip instruction transmission scenarios where the physical distance between the two caches is long, the transmission latency is high, and instruction prefetching operations frequently trigger cancellation and retransmission actions. This method relies on the L1ICBus transmission bus to complete the data interaction. The Level 1 Instruction Cache is also known as the first cache of this application, and can also be referred to as the L1 cache. The Level 2 Instruction Cache is also known as the second cache of this application, and can also be referred to as the L2 cache.

[0033] like Figure 1 The diagram illustrates a cache structure comprising several AI kernels (AI kernel 0, AI kernel 1 to AI kernel N). Each AI kernel deploys an independent L1 cache. Each L1 cache is connected to a shared L2 cache via a transmission bus L1ICBus. This application will select any AI kernel's L1 cache, the transmission bus L1ICBus, and the L2 cache as the data interaction link to describe the data transmission method of this embodiment.

[0034] like Figure 2The diagram illustrates another cache structure. An L1 cache is deployed internally within the AI ​​kernel, connected to the L2 cache via a transmission bus, L1ICBus. The L1ICBus includes a read address channel (c channel) and a read data channel (d channel). The L1 cache parses the instruction read and prefetch tasks issued by the AI ​​kernel, then queries the tag table (i Tag Table) to determine the instruction cache hit status. If the local cache hits, the instruction data is directly retrieved from local memory and fed back to the AI ​​kernel. If the L1 cache misses, a corresponding data read request is generated. This data read request is transmitted to the L2 cache via the read address channel. Upon receiving the data read request, the L2 cache sends the matching data packet back to the L1 cache via the read data channel. Upon receiving the returned data packet, the L1 cache synchronously updates its tag table and local memory, storing the instruction data from the data packet into local memory, thus completing the AI ​​kernel's instruction read and prefetch tasks.

[0035] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0036] This embodiment provides a data transmission method. This data transmission method is applied to a transmission bus, which is a dedicated interconnect bus adapted for high-speed data interaction between a first cache and a second cache. The two ends of the transmission bus are respectively connected to the first cache and the second cache. The first cache is a Level 1 instruction cache (L1ICACHE), which serves as a near-end instruction access unit, responsible for receiving and responding to kernel instruction fetch requests in real time. The second cache is a Level 2 instruction cache (L2ICACHE), which serves as a remote, high-capacity instruction storage unit, used to store the main instruction data and respond to data read requests from the first cache.

[0037] like Figure 3 The diagram shows a data transmission method, which includes the following steps S101 to S103: S101. Send multiple data read requests from the first cache to the second cache.

[0038] Multiple data read requests can be sent to the second cache without waiting for a handshake signal to be sent between the first cache and the second cache. The handshake signal is a response signal between the first cache and the second cache used to indicate that the data is ready to receive. In other words, multiple data read requests from the first cache can be sent to the second cache without waiting for the second cache to send a handshake signal.

[0039] In one implementation, the transmission bus receives multiple data read requests sent by the first buffer, and then sends the multiple data read requests to the second buffer without waiting for a handshake signal from the second buffer.

[0040] For example, the multiple data read requests are sent sequentially to the second buffer in turn according to the system clock beat.

[0041] In another example, the multiple data read requests are multiple data read requests generated in parallel by the first cache, and the multiple data read requests are sorted by bus arbitration and then transmitted sequentially to the second cache through the transmission bus.

[0042] In one implementation, when a cancellation / retransmission action is triggered by events such as switching instruction fetch branches in the AI ​​kernel or terminating the prefetch process, due to the long transmission distance between the first and second buffers, the transmission bus will simultaneously contain new data read requests generated after the first buffer performs the cancellation / retransmission action, as well as invalid data read requests (i.e., invalid requests) that were sent to the transmission bus before the cancellation / retransmission action was triggered. Both types of requests coexist in the bus transmission queue, and the transmission bus sends multiple data read requests to the second buffer sequentially.

[0043] S102. Receive the target data packet sent by the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests.

[0044] Invalid requests refer to data read requests that are no longer valid and require no response. When cancellation and resending are triggered by events such as AI kernel branch switching or prefetching process termination, the first cache will identify previously sent data read requests to the second cache that are still in transit and have not yet been received as invalid requests. These invalid requests can be identified by the second cache during its invalid request filtering process, and the second cache can choose not to execute the invalid request.

[0045] In one implementation, when no cancellation retransmission operation is triggered, all data read requests are valid requests, and the transmission bus receives the target data packets returned by the second buffer based on multiple data read requests.

[0046] In one implementation, when a cancel retransmission operation is triggered, the new data read request generated after the cancel retransmission action is the target data read request. The transmission bus receives the target data packet returned by the second buffer based on the target data read request.

[0047] For example, the read address contained in the target data packet is a globally addressed address, which is consistent with the request address carried in the target data read request sent by the first cache.

[0048] S103. Send the target data packet to the first buffer. The read address is used to filter valid data packets from the target data packet. The target data packet does not wait for the handshake signal to be sent.

[0049] For example, the target data packet can be sent to the first buffer without waiting for the handshake signal to be sent, that is, without waiting for the first buffer to return the handshake signal.

[0050] In one implementation, the second buffer sends the target data packet carrying the read address back to the first buffer via the transmission bus. The first buffer performs address verification based on the read address attached to the target data packet and the request address of the target data read request stored locally. If the two addresses match, the first buffer receives the target data packet.

[0051] In one implementation, when no cancellation and retransmission operation is triggered, all returned target data packets can be received by the first buffer as valid data packets after address verification.

[0052] In one implementation, when a cancellation and retransmission operation is triggered, due to the large physical distance between the first and second buffers and the high overall transmission latency, the second buffer, even without receiving a new data read request, will still treat the invalid data read request as the target data read request and send the target data packet corresponding to the invalid data read request to the transmission bus. Upon receiving a new data read request, the second buffer will treat the new data read request as the target data read request and send the target data packet corresponding to the new data read request to the transmission bus.

[0053] The transmission bus transmits these two types of target data packets to the first buffer. The first buffer matches the global address (read address) carried in the target data packet with the global address (request address) corresponding to the new data read request. If they match, the data packet is determined to be a valid data packet corresponding to the new data read request. If they do not match, the data packet is determined to be an invalid data packet corresponding to an invalid data read request.

[0054] This embodiment provides a data transmission method. This data transmission method is applied to a first buffer.

[0055] like Figure 4 The flowchart of another data transmission method is shown, which includes the following steps S201~S203: S201. Send multiple data read requests without waiting for the handshake signal between the first and second caches.

[0056] In one implementation, the first cache parses the read and prefetch instructions issued by the AI ​​kernel and generates a data read request. If the AI ​​kernel issues instructions such as branch jump or prefetch termination, the first cache performs a cancel retransmission action, marks the in-transit data read requests before the cancel retransmission action is triggered as invalid requests, and the first cache generates and sends a new data read request.

[0057] S202. Receive the target data packet in the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests.

[0058] In one implementation, when no cancellation and retransmission operation is triggered, the second cache identifies multiple data read requests as target data read requests, and the first cache receives the corresponding target data packets via the transmission bus.

[0059] In one implementation, when a cancel retransmission operation is triggered, the newly generated data read request after the cancel retransmission action has not yet reached the second buffer. The second buffer generates the corresponding target data packet based on the previously received in-transit data read requests. After the new data read request is transmitted to the second buffer, the second buffer filters out invalid requests and only identifies the new data read request as the target data read request, generating a target data packet for return. Due to the long transmission distance and high transmission latency of the two-level buffers, the first buffer will acquire these two types of target data packets sequentially, and the target data packet does not wait for the handshake signal to be sent.

[0060] S203. Based on the read address, filter valid data packets from the target data packets.

[0061] In one implementation, the first cache extracts the read address carried in the target data packet and performs address verification with the request address corresponding to the sent data read request. When no cancellation / retransmission operation is triggered, the addresses of all target data packets can be matched, and the first cache receives all target data packets completely, synchronously updating its internal tag table and local storage unit. When a cancellation / retransmission operation is triggered, the first cache only retains target data packets corresponding to new data read requests, discarding target data packets marked as invalid requests. After filtering out valid data packets, the first cache updates its internal tag table and local storage unit.

[0062] This embodiment provides a data transmission method. This data transmission method is applied to a second buffer.

[0063] like Figure 5 The diagram shows another data transmission method, which includes the following steps S301 to S304: S301, Receive multiple data read requests, and the multiple data read requests do not wait for the handshake signal to be sent between the first buffer and the second buffer.

[0064] In one implementation, the second buffer receives multiple data read requests sequentially transmitted by the first buffer via a transmission bus. If the first buffer performs a cancel retransmission action, the transmission bus will simultaneously contain invalid requests already transmitted before the cancel retransmission and new data read requests generated after the cancel retransmission.

[0065] S302. Filter out invalid requests from multiple data read requests to obtain the target read request.

[0066] In one implementation, after receiving a new data read request, the second cache determines the data read requests received before the new data read request as invalid requests and determines the new data read request as the target read request.

[0067] For example, each data read request is configured with a transmission identifier. When the second cache receives a new data read request with the same transmission identifier, and there is an old request being processed for the same transmission identifier, the second cache recognizes that there is an old request being processed for the transmission identifier. Then, it determines all data read requests received before the new data read request as invalid, and only takes the new data read request and the data read requests obtained after the new data read request as the target read request.

[0068] S303. Based on the target read request, the target data packet is obtained by reading the data. The target data packet includes the read address corresponding to the target data packet in the second cache. The read address is used to filter valid data packets from the target data packet.

[0069] In one implementation, the second cache extracts the global request address carried inside the target read request, assigns the address as the read address of the target data packet, and then retrieves the data content matching the address from its own storage unit, encapsulates and combines it to obtain the target data packet.

[0070] S304. Send the target data packet. The target data packet does not wait for the handshake signal to be sent.

[0071] In one implementation, the second buffer sends the target data packet via the transmission bus.

[0072] Compared with existing technologies, this solution enables uninterrupted transmission of data read requests, effectively improving the data interaction efficiency between caches, while also increasing bus bandwidth and resource utilization. Especially in scenarios with high-latency transmission between the first and second caches and cancellation / retransmission actions, the design, based on continuous sending of data read requests, invalid request filtering, and address verification of packets, allows for continuous sending of new requests without waiting for all invalid request data packets generated during the cancellation / retransmission process to return. This avoids invalid requests consuming transmission flow and bus resources, effectively solving the problems of transmission congestion, low efficiency, and poor resource utilization in high-latency scenarios.

[0073] The data transmission method provided in the embodiments of this application will now be described in detail on the transmission bus side.

[0074] Optionally, this application also provides an embodiment of sending multiple data read requests from the first cache to the second cache. In this embodiment, each data read request from the first cache is sent to the second cache sequentially using a unidirectional streaming method.

[0075] In this unidirectional streaming transmission, the corresponding read address channel in the transmission bus has a fixed transmission direction: the first buffer points to the second buffer. Only a forward path is set up for the first buffer to send requests to the second buffer; no reverse feedback "ready" handshake signal is set up for the second buffer. The first buffer can continuously push various data read requests serially, and the second buffer unconditionally receives all arriving data read requests without the need for a bidirectional handshake response.

[0076] This embodiment, by employing unidirectional streaming transmission in the read address channel and eliminating the ready handshake signal, eliminates the timing overhead and interaction logic associated with bidirectional handshakes, simplifies bus transmission timing and hardware circuitry, reduces chip area footprint, and improves transmission timing performance. In high-latency transmission scenarios involving the first and second caches, the first cache can continuously and serially issue data read requests. When an instruction jump occurs requiring the cancellation of an old request and the retransmission of a new request, it can immediately continue pushing new data read requests, achieving real-time cancellation and retransmission of prefetch operations without waiting for the data corresponding to invalid requests, significantly improving cancellation and retransmission efficiency.

[0077] Optionally, each data read request includes a first transmission enable signal in the first buffer, which is used to identify the data read request as an acceptable data read request.

[0078] In one implementation, the first transmission enable signal corresponds to the cValid signal on the transmission bus. When the first buffer pulls the cValid signal high, it indicates that a data read request on the current read address channel can be received. After detecting the cValid signal, the second buffer directly receives the corresponding data read request without needing to send back a receive status.

[0079] This embodiment relies on the cValid signal and a one-way streaming transmission mechanism without a ready handshake, simplifying the channel interaction logic and eliminating the transmission delay caused by a two-way handshake. Even if there is a significant physical transmission delay between the first and second buffers, the first buffer can continuously and serially send data read requests. When it is necessary to cancel an old request and resend a new request, the first buffer can immediately push a new data read request, enabling rapid operation switching.

[0080] Optionally, each data read request may contain a first cached transport identifier, multiple data read requests may contain the same transport identifier, or each read request may contain a different transport identifier.

[0081] The transmission identifier (cId) is used to distinguish between the various data read requests generated in parallel by the first cache. For example, the first cache contains multiple independent state machines, each corresponding to a transmission task and bound to a unique cId. The state machine is responsible for generating and sending data read requests.

[0082] In one implementation, when an instruction jump occurs and a cancellation and retransmission operation is required for a single request, the newly generated data read request in the corresponding state machine continues to use the original cId. After detecting requests arriving sequentially under the same cId, the second-level cache can, based on its own operating state, choose to process the old data read request first (the request marked as invalid by the first cache) before responding to the new data read request, or directly flush the unprocessed old data read request with the new data read request.

[0083] In one implementation, when multiple state machines simultaneously initiate independent fetch and prefetch tasks, each data read request carries a unique cId. The transmission bus distinguishes between multiple data read requests based on these different cIds.

[0084] This embodiment uses cId to isolate and manage multiple data read requests, which can quickly replace old requests and ensure transmission efficiency in cancellation and retransmission scenarios. It can also support multi-task parallel transmission and out-of-order data interleaving, and adapt to high-latency transmission scenarios between the first and second caches.

[0085] Optionally, this application also provides an embodiment for receiving target data packets sent by a second buffer. In this embodiment, the target data packets sent by the second buffer are received sequentially using a unidirectional streaming transmission method.

[0086] In this unidirectional streaming transmission, the corresponding read data channel in the transmission bus has a fixed transmission direction: the second buffer points to the first buffer. Only a forward path is set up for data to be transmitted back from the second buffer to the first buffer; no ready handshake signal is set up for the first buffer to provide feedback. The second buffer can continuously push various target data packets serially, and the first buffer unconditionally receives all arriving data packets without the need for a bidirectional handshake response.

[0087] This embodiment simplifies bus transmission timing and hardware circuitry by employing unidirectional streaming transmission in the read data channel and eliminating the ready handshake signal, thus avoiding the timing overhead and interaction logic of bidirectional handshakes and reducing chip area. In high-latency transmission scenarios involving the first and second buffers, the second buffer can continuously serially transmit the target data packet back.

[0088] Optionally, the target data packet includes a second transmission enable signal in the second buffer, which is used to identify the target data packet as an receivable data packet.

[0089] In one implementation, the second transmission enable signal corresponds to the dValid signal on the transmission bus. When the second buffer pulls the dValid signal high, it indicates that the target data packet on the current read data channel can be received. After detecting the dValid signal, the first buffer directly receives the corresponding data packet without needing to send back the receive status.

[0090] This embodiment relies on the dValid signal and a one-way streaming transmission mechanism without a ready handshake, simplifying the channel interaction logic and eliminating the transmission delay caused by a two-way handshake. Even if there is a significant physical transmission delay between the first and second buffers, the second buffer can continuously and serially transmit the target data packet back. When a request to cancel and retransmit occurs, the first buffer can filter invalid packets using verification rules, ensuring the stable operation of the data reception process.

[0091] Optionally, the target data message may contain the same transport identifier as the target data read request.

[0092] In one implementation, the transmission identifier corresponds to the dId signal of the transmission bus, which strictly corresponds one-to-one with the cId in the data read request. When the second buffer sends back a data packet, it uses the cId of the requesting end as the dId. The first buffer first allocates the data to the corresponding processing path according to the dId, and then further verifies the read address in the packet.

[0093] This embodiment relies on the binding relationship between dId and cId to complete the data splitting of multiple parallel tasks. With the address verification mechanism, it identifies invalid data in the scenario of canceling retransmission. It can adapt to the high-latency transmission characteristics of the first and second buffers, and supports out-of-order and interleaved data transmission, effectively ensuring the accuracy of overall data reception and transmission efficiency.

[0094] Optionally, the target data message includes the target data block from among multiple data blocks corresponding to the cache line in the target data read request, as well as the offset address of the target data block, which indicates the position of the target data block in the cache line.

[0095] A cache line is a complete data unit corresponding to a single read operation between caches, and it is also the basic unit for a first-level cache to initiate a read request to a second-level cache. A cache line is composed of multiple data blocks of uniform size.

[0096] The data block is the smallest data unit transmitted on the bus in a single transmission. The complete cache line will be split into several independent data blocks and transmitted in batches.

[0097] In one implementation, the offset address is used to mark the specific position of the current data block within the cache line. After receiving a valid data packet, the first cache can store the data block in the corresponding position according to the offset address, without having to follow a fixed transmission order. This mechanism supports out-of-order and interleaved data transmission. Even if the transmission latency between the first and second level caches is high, or if a request to cancel and retransmit occurs, data splicing and storage can be completed smoothly, effectively improving the flexibility and overall efficiency of bus transmission.

[0098] The data transmission method provided in the embodiments of this application will now be described in detail on the first cache side.

[0099] Optionally, this application also provides an embodiment of sending multiple data read requests. In this embodiment, upon receiving a first signal, a target data read request is sent. The target data read request shares the same transmission identifier with at least one of the multiple data read requests. The first signal is used to invalidate the data read requests other than the target data read request.

[0100] For example, the first signal is issued by the AI ​​kernel when it detects an instruction jump (branch jump). When an instruction jump occurs in the program execution flow, the AI ​​kernel outputs the first signal to the first cache to terminate the currently unfinished instruction fetch and prefetch tasks.

[0101] In one implementation, after receiving the first signal, each state machine within the first cache marks all unprocessed data read requests as invalid and sends new data read requests using the same transmission identifier. Upon recognizing both new and old data read requests under the same transmission identifier, the second-level cache, based on its own operating state, chooses to process the two types of requests sequentially or directly flush the old data read requests with the new ones, thus enabling real-time cancellation and retransmission of requests and adapting to high-latency transmission scenarios between the first and second-level caches.

[0102] Optionally, this application also provides an embodiment for filtering valid data packets from target data packets based on the read address. In this embodiment, the read address carried by the target data packet is compared with the request address corresponding to the target data read request; if they match, the target data packet is determined to be a valid data packet.

[0103] In one implementation, the first cache first distributes the target data packet to the corresponding state machine based on the transmission identifier. Then, the state machine compares the read address carried in the target data packet with the request address of the target data transmission request stored locally. If the addresses do not match, the data packet is determined to be an invalid request and is discarded directly. If the addresses match, the data is determined to be valid and is stored normally. This method can accurately filter invalid data in scenarios such as instruction jumps, request retransmissions, and out-of-order data interleaving, ensuring accurate and reliable data reception.

[0104] Optionally, this application also provides an embodiment. In this embodiment, upon receiving a second signal, the target data packet is discarded, and the second signal is used to trigger the first buffer to enter a sleep mode.

[0105] For example, the second signal is a sleep enable signal, issued by the AI ​​kernel. When the current instruction has finished executing and the system has no instruction fetching or prefetching tasks, the AI ​​kernel outputs this second signal to control the first cache to enter a low-power sleep state. In one implementation, after receiving the second signal, all internal state machines of the first cache switch to the idle state and turn off the operating clock, entering a low-power mode. Subsequent target data packets are directly discarded. Since the transmission channel does not have a receive acknowledgment handshake signal, the sleep of the first cache will not interfere with the operation of the second-level cache, achieving independent low-power management and effectively avoiding bus deadlock problems.

[0106] The data transmission method provided in the embodiments of this application will now be described in detail on the second cache side.

[0107] Optionally, this application also provides an embodiment for filtering invalid requests from multiple data read requests to obtain a target read request. In this embodiment, when multiple data read requests include data read requests with the same transmission identifier, the latest received data read request with the same transmission identifier is selected as the target read request.

[0108] In one implementation, when the second cache receives multiple data read requests carrying the same transmission identifier, it determines that the first request is an expired old request and uses the latest received request as the target read request to be responded to. The second cache can choose, based on its own operating state, to continue processing old data read requests before responding to new data read requests, or directly flush and discard unprocessed old data read requests with new data read requests. This processing logic adapts to request cancellation and retransmission scenarios caused by instruction jumps. Combined with the decoupled architecture of the read address channel and read data channel, it can respond to new data read requests without waiting for the data transmission corresponding to the old data read request to complete, effectively improving request processing efficiency in high-latency transmission scenarios.

[0109] This application also provides a data transmission system comprising: a first buffer, a second buffer, and a transmission bus; The first buffer is used to send multiple data read requests through the transmission bus; receive target data packets from the second buffer; and filter valid data packets from the target data packets based on the read address corresponding to the target data packets.

[0110] The second buffer is used to receive multiple data read requests through the transmission bus; filter invalid requests from the multiple data read requests to obtain the target read request; read data according to the target read request to obtain the target data packet; and send the target data packet.

[0111] The transmission bus is used to send multiple data read requests from the first buffer to the second buffer; receive target data packets sent by the second buffer; and send target data packets to the first buffer.

[0112] As can be seen, the specific working methods, execution logic, and related embodiments of the first buffer, second buffer, and transmission bus included in the data transmission system have been described in detail in the corresponding content above, and will not be repeated here. Based on the design of bus-less handshake acknowledgment, channel decoupling, and address verification, this system can achieve fast request cancellation and retransmission, out-of-order interleaved data transmission, and independent low-power sleep mode for the first buffer, adapting to high-latency transmission scenarios between the first and second level buffers.

[0113] To clarify the data interaction rules and design basis between the transmission bus and the two-level buffer, the following examples illustrate the calculation and setting methods of key configuration items of the transmission bus from three aspects: parallel transmission configuration, bus width, and number of data fragments: Firstly, the number of parallel data read paths and the range of transmission flag values ​​are determined. This scheme uses a single cache line in the L1 cache as a complete instruction data block. The number of clock cycles required for the L1 cache to read this instruction data block is divided by the number of clock cycles required for the AI ​​kernel to execute it, thus calculating the number of parallel data read paths. This number of parallel paths determines the range of transmission flag values. In one example, the data capacity of a single cache line is set to 256 bytes. The L1 cache takes 64 clock cycles to read this cache line from the L2 cache, and this set of instructions can be continuously executed by the AI ​​kernel for 16 clock cycles. Calculations show that this scheme has 4 parallel data read paths, corresponding to 4 sets of available transmission flags configured on the transmission bus, numbered 0, 1, 2, and 3 respectively.

[0114] Secondly, the transmission bus width needs to be determined. The width of the transmission bus must be greater than the number of instruction bytes read by the AI ​​kernel in a single clock cycle. Continuing with the example above, the AI ​​kernel can read 16 bytes of instruction data per cycle; therefore, this solution sets the transmission bus width to 32 bytes.

[0115] Thirdly, the number of data fragments corresponding to a single read request is determined. Dividing the total capacity of a single cache line by the transmission bus width yields the total number of data fragments required for a single read request. Based on the aforementioned parameters, a single read request corresponds to 8 data fragments. In this scheme, the data unit corresponding to a single bus width is defined as a data fragment or data block.

[0116] The following section provides an exemplary description of the various interaction signals used by the first and second buffers to complete data exchange via the transmission bus.

[0117] The signals output from the L1 cache to the L2 cache include four types: First, the address signal cAddr, which is the requested address mentioned above. This address signal uses byte addressing. In instruction fetch scenarios, the byte addressing is aligned with the bus data width. In data prefetch scenarios, the byte addressing is aligned with the cache line set size. Second, the path identifier signal cId, also known as the transfer identifier, is used to mark the parallel fetch identifier number of the L1 cache. Third, the type distinction signal cQos, is a single-bit signal; a high level corresponds to instruction fetch, and a low level corresponds to data prefetch. Fourth, the validity indicator signal cValid, also known as the first transfer enable signal, is a single-bit signal used to indicate whether the aforementioned three types of signals are receptive.

[0118] The signals input from the L2 cache to the L1 cache include five categories: First, the path identifier signal dId, corresponding to the cId function, is used to match the front-end parallel instruction fetch path. Second, the return address signal dAddr, i.e., the read address, whose content is consistent with the cAddr issued by the L1 cache, and also includes the offset address of the data block. Third, the data signal dData, carrying the service data issued by the L2 cache, i.e., the data block. Fourth, the status feedback signal dStatus, a two-bit signal used to provide feedback on the transmission status, where 0x00 represents normal transmission, 0x01 represents a L2 cache parity error, 0x10 represents a bus transmission error, and 0x11 represents a simultaneous bus error and a memory parity error. Fifth, the validity indicator signal dValid, i.e., the second transmission enable signal, is a single-bit signal used to indicate whether the current group of return signals is receivable.

[0119] The data transmission timing under different operating conditions of this application will be described in detail below.

[0120] like Figure 6 The diagram shows an ordered serial transmission timing sequence, and Figures 7 to 10 Detailed schematic diagrams one through four illustrate the ordered serial transmission timing. They demonstrate the ordered serial data interaction between the first and second buffers. The first buffer sequentially initiates data read requests via the read address channel, and the second buffer sequentially sends back data packets via the read data channel.

[0121] During the global clock cycle (Clk) of the first and second caches, the first cache pulls the read address channel enable signal cValid high and synchronously outputs the read address signal cAddr, the transfer identifier signal cId, and the priority signal cQos in parallel with the read address channel transaction segment. See also Figure 7 , Figure 7 for Figure 6 The detailed diagram in section 61 shows that the first buffer sequentially sends three sets of data read requests configured with different transmission identifiers. The transmission identifiers for the three sets of data read requests are sent in the following order: cId=0, cId=1, and cId=2. The read addresses for the three sets of data read requests are cAddr=A+0x80, cAddr=A+0x100, and cAddr=A+0x200 (NA is the default value). The priority signal cQoS is pulled high at cId=0, indicating that the data read request corresponding to cId=0 is a fetch request, while the data read requests corresponding to cId=1 and cId=2 are prefetch requests. The relevant signals (cValid, cId, cQos, cAddr) are delivered to the second buffer after a fixed link latency.

[0122] The second cache splits the target cache line in the data read request into multiple data fragments (8 fragments). After completing the acquisition of fragmented data, it pulls the read data pipeline enable signal dValid high and synchronously sends back the data identifier dId matching the transmission identifier, the fragment address dAddr carrying fragment offset information, and the fragmented data dData. See also Figure 8 , Figure 8 for Figure 6 The detailed diagram in section 62 shows that the second buffer processes data read requests with different transmission identifiers sequentially according to the order in which the data read requests are received. For example, when the second buffer processes a data read request with cId=0, it pulls the read data passage enable signal dValid high and synchronously outputs the fragment addresses corresponding to the four groups of fragmented data dAddr=A+0x80, dAddr=A+0xa0, dAddr=A+0xc0, and dAddr=A+0xe0, along with the fragment address signal daddr. It also sequentially outputs the data identifiers corresponding to the four groups of fragmented data with dId=0. Finally, it sequentially transmits the fragmented data dData=D0-4, dData=D0-5, dData=D0-6, and dData=D0-7. (See also...) Figure 9 ,and Figure 10 , Figure 9 for Figure 6 Detailed diagram of part 63. Figure 10 for Figure 6 Detailed diagram of the 64 parts, and Figure 7Similarly, the second buffer, the fragment address signal daddr, outputs the fragment addresses corresponding to the 8 groups of fragmented data: dAddr=A+0x100, dAddr=A+0x120, dAddr=A+0x140, dAddr=A+0x160, dAddr=A+0x180, dAddr=A+0x1a0, dAddr=A+0x1e0; dAddr=A+0x200, dAddr=A+0x220, dAddr=A+0x240, dAddr=A+0x260, dAddr=A+0x280, dAddr=A+0x2a0, dAddr=A+0x2e0. The data identifier dId is output sequentially as the transmission identifier for the 8 groups of fragmented data with dId=1, followed by the transmission identifier for the 8 groups of fragmented data with dId=2. The 8-group fragmented data with dId=1 are dData=D1-0, dData=D1-1, dData=D1-2, dData=D1-3, dData=D1-4, dData=D1-5, dData=D1-7, and dData=D1-7, respectively; the 8-group fragmented data with dId=2 are dData=D2-0, dData=D2-1, dData=D2-2, dData=D2-3, dData=D2-4, dData=D2-5, dData=D2-6, and dData=D2-7, respectively.

[0123] After receiving the data packet returned by the second cache, the first cache first performs a consistency check between dId and cId, then compares dAddr and cAddr, and writes the fragmented data dData that has passed the check to the corresponding position in the cache line.

[0124] like Figure 11 This diagram illustrates a disordered and interleaved transmission timing scheme. Figures 12 to 15 Detailed schematic diagrams one to four of the out-of-order and interleaved transmission timing described above illustrate out-of-order and interleaved data interaction between the first and second buffers. The first buffer initiates a data read request out of order via the read address channel, and the second buffer returns out-of-order and interleaved data packets via the read data channel. It can be understood that the following... Figures 11 to 15 With the above Figures 6 to 10 The same parts will not be described in detail.

[0125] See Figure 12 , Figure 12 for Figure 11 The detailed diagram of section 111 shows that the first buffer outputs three sets of data read requests (cId=0, cId=2, and cId=1) upon transmitting the identification signal cId. These related signals are then delivered to the second buffer after a fixed link latency.

[0126] See Figures 13 to 15 , Figure 13 for Figure 11 Detailed diagram of section 112. Figure 14 for Figure 11 Detailed diagram of section 113. Figure 15 for Figure 11 A detailed diagram of section 114 is provided. After the second buffer receives three sets of data read requests in sequence, it transmits out-of-order and interleaved data packets (including fragment address daddr and fragment data dData) with dId=0, dId=1, and dId=2. The fragment data corresponding to the three sets of transmission identifiers are interleaved in the read data channel, and the dId, dAddr, and dData in each set of return data packets are matched one-to-one.

[0127] After receiving the data packet returned by the second cache, the first cache first performs a consistency check between dId and cId, then compares dAddr and cAddr, and writes the fragmented data dData that has passed the check to the corresponding position in the cache line.

[0128] like Figure 16 The diagram shows a timing illustration of canceling a retransmission, and... Figures 17 to 20 The diagrams shown are one through four, illustrating the timing details of a cancel retransmission operation. They illustrate how, after the first cache initiates data read requests (A+0x80, A+0x100) corresponding to transmission identifiers cId=0 and cId=1 via the read address channel, a cancel retransmission operation is triggered, and a new data read request (B) is initiated using the transmission identifier cId=0 on the read address channel. See also... Figures 17 to 20 , Figure 17 for Figure 16 Detailed diagram of section 161, Figure 18 for Figure 16 Detailed diagram of section 162, Figure 19 for Figure 16 Detailed diagram of section 163. Figure 20 for Figure 16 A detailed diagram of section 164. It can be seen that the following... Figures 16 to 20 In the middle and above Figures 6 to 10 The same parts will not be described in detail.

[0129] The first buffer first sends data read requests corresponding to transmission identifiers cId=0 and cId=1. After triggering the cancel retransmission operation, the data read requests corresponding to cId=0 and cId=1 are invalidated, and the data read request for read address cAddr=B is sent using transmission identifier cId=0. The relevant signals arrive at the second buffer after a fixed link latency.

[0130] The second cache continues to send back the data packets corresponding to the three sets of data read requests sequentially according to the original scheduling logic. The relevant signals (dValid, dId, dAddr, dData) arrive at the first cache after a fixed link latency.

[0131] After receiving the data packet returned by the second cache, the first cache performs a two-level check. For the fragment data corresponding to dAddr=A (A+0x80-A+0xe0, A+1x100-A+0x1e0), the first cache performs a double check on dId and dAddr. Finding that dAddr and cAddr do not match, the first cache discards all fragment data corresponding to dAddr=A (A+0x80-A+0xe0, A+1x100-A+0x1e0). When a subsequent data packet corresponding to dAddr=B (B+0x20-B+0xe0) arrives, the first cache performs a double check on its dId and dAddr. Finding that it matches cId and cAddr, the first cache writes the fragment data corresponding to dAddr=B (B+0x20-B+0xe0) to storage. Compared to the traditional AXI bidirectional handshake bus architecture, this solution does not require waiting for the old data read requests (the data read requests corresponding to cAddr=A+0x80 and cAddr=A+1x100) to complete the entire transmission link before sending out the new request (the data read request corresponding to cAddr=B). The data packets corresponding to the old data read requests that are stuck in the transmission link will not interfere with the data reception process of the new data read requests.

[0132] like Figure 21 The diagram shows another transmission timing diagram for canceling retransmission, and Figures 22 to 24 The diagrams shown in Figures 1 to 3 illustrate another method of canceling retransmission, where new data read requests flush out old data read requests on the second cache side. Figure 22 for Figure 21 Detailed schematic diagram of section 211, Figure 23 for Figure 21 Detailed schematic diagram of section 212. Figure 24 for Figure 21 A detailed schematic diagram of section 213. (As mentioned above) Figures 16 to 20 The example is similar. The first buffer first sends data read requests corresponding to transport identifiers cId=0 and cId=1 using transport identifier cId=0. Subsequently, a cancel retransmission operation is triggered, invalidating the data read requests corresponding to cId=0 and cId=1, and reusing transport identifier cId=0 to send a data read request for read address cAddr=B. The relevant signals (cValid, cId, cQos, cAddr) arrive at the second buffer after a fixed link latency.

[0133] The difference lies in the fact that the second buffer identifies two sets of data read requests corresponding to cAddr=A+0x80 and cAddr=B, respectively, for the same transmission identifier cId=0. The first request, cAddr=A+0x80, is determined to be invalid, and the data read and fragmentation process for cAddr=A+0x80 is terminated directly. Since the data read request corresponding to cAddr=A+0x100 arrives at the second buffer before the data read request corresponding to cAddr=B, the second buffer still considers it valid. The relevant signals (dValid, dId, dAddr, dData) of the data packet corresponding to dAddr=A+0x100-A+0x1e0 and the data packet corresponding to dAddr=B-B+0xe arrive at the first buffer after a fixed link latency.

[0134] Upon receiving a data packet corresponding to dAddr=A+0x100-A+0x1e0, the first buffer discards it because the data read request has already been invalidated. Upon receiving a data packet corresponding to dAddr=B-B+0x0e0, it verifies the data packet's validity through double verification of dId and dAddr, and writes the corresponding data fragment to storage. Compared to the traditional AXI bidirectional handshake bus architecture, this solution eliminates the need to wait for the old data read request to complete its full transmission path before issuing a new request. It can directly truncate the data transmission path of the old data read request at the second buffer, reducing the unnecessary use of bus bandwidth.

[0135] like Figure 25 The diagram shows a timing illustration of a low-power sleep mode for a first cache, and... Figures 26 to 29 The diagrams shown are one through four, illustrating the timing details of a low-power sleep mode for the first cache. They demonstrate that when the AI ​​kernel determines there are no instruction fetch operations, it outputs a sleep trigger signal, the first cache switches to an IDLE low-power state, and its own clock is turned off, while the second cache clock remains running normally. See also... Figure 25 The L1 cache (first cache) clock is turned off when the L1 cache sleep signal IDLE goes high (waveform straightening), while the L2 cache (second cache) clock cycle Clk runs normally. Figure 26 for Figure 25 Detailed diagram of section 251, Figure 27 for Figure 25 Detailed diagram of section 252. Figure 28 for Figure 25 Detailed diagram of section 253. Figure 29 for Figure 25 Detailed diagram of section 254.

[0136] The first buffer had previously sent three sets of data read requests with transmission identifiers cId=0, cId=1, and cId=2 in sequence. These three sets of request signals were continuously delivered to the second buffer after a fixed link latency. Afterward, the first buffer's sleep signal IDLE went high, and the L1 buffer clock turned off. At this time, the second buffer continued to send back the data packets corresponding to dId=0, dId=1, and dId=2 in an ordered sequence. While the first buffer was in the IDLE clock-off phase, all the continuously output dId, dAddr, dData, and dValid signals from the second buffer were not checked or stored; all transmitted data packets were directly ignored. This transmission architecture does not configure a read data channel ready acknowledgment signal, and the first buffer's behavior of discarding data packets during sleep will not cause a blocking deadlock between the second buffer and the transmission bus. After the AI ​​kernel sends a wake-up signal, the first cache resumes its working clock and re-outputs valid cAddr, cId, and cValid signals to initiate a new data read request. Historical old data packets that are stuck on the transmission link due to fixed link latency at the wake-up time can be filtered out through a dual verification mechanism of dId matching and dAddr address comparison.

[0137] The following is combined Figure 30 The aforementioned execution diagram illustrates the overall execution flow, state transition logic, and complete working timing of the state machine corresponding to the four parallel transmission paths of this application. The state machine includes the IDLE idle state, the CCH address transmission state, and the DCH data reception state. Wherein: During normal system operation, the first cache remains in the IDLE state by default, continuously waiting for instruction fetch or prefetch requests from the AI ​​kernel. When an instruction read request occurs, the first cache allocates the transmission task according to the hardware scheduling rules of idle priority and fixed order, triggering the internal state machine of the corresponding transmission path to jump from the IDLE state to the CCH address transmission state.

[0138] After entering the CCH address transmission state, the first buffer completes the address channel signal completion, initializes the data receive counter, and completes the bus transmission of the address channel signal according to the bus arbitration rules. After that, the state machine jumps to the DCH data receive state.

[0139] After entering the DCH data reception state, the first buffer continuously listens for the feedback signal from the transmission bus read data channel. Through transmission identifier matching and address dual verification mechanisms, it completes the filtering, validity verification, and data writing of valid fragmented data (messages). Simultaneously, it updates the internal receive counter value. When the accumulated value of the receive counter reaches the total number of fragments corresponding to a single buffer line, it determines that the current single instruction read task has been completed, and the state machine automatically resets to the IDLE idle state, waiting to receive the next data read request.

[0140] at the same time, Figure 30 The abnormal reset logic of this state machine is further illustrated. Regardless of whether the state machine is in the CCH address sending state or the DCH data receiving state, once a cancellation and retransmission signal triggered by the AI ​​kernel branch jump is detected, the first cache immediately terminates the currently executing address sending process or data receiving process and returns to the IDLE idle state. This state transition mechanism requires no additional timing overhead and can realize the immediate cancellation (invalidation) and rapid retransmission of data read requests. It provides underlying state logic support for the out-of-order interleaved transmission, instruction cancellation and retransmission, and the independent low-power sleep function of the first cache mentioned above in this application, effectively ensuring the operational efficiency and operational flexibility of the two-level cache data transmission architecture.

[0141] Furthermore, this embodiment provides a data transmission device, such as... Figure 31 The diagram shows a data transmission device 3100, which includes: a first transmitting module 3110, a first receiving module 3120, and a second transmitting module 3130; wherein: The first sending module 3110 is configured to send multiple data read requests from the first cache to the second cache, and the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache.

[0142] The first receiving module 3120 is configured to receive the target data packet sent by the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests.

[0143] The second sending module 3130 is configured to send a target data packet to the first buffer. The read address is used to filter valid data packets from the target data packet. The target data packet does not wait for the handshake signal to be sent.

[0144] Furthermore, this embodiment provides another data transmission device, such as... Figure 32 The schematic diagram of another data transmission device shown shows that device 3200 includes a second transmitting module 3210, a second receiving module 3220, and an address verification module 3230; wherein: The second sending module 3210 is configured to send multiple data read requests, which do not wait for the handshake signal to be sent between the first buffer and the second buffer.

[0145] The second receiving module 3220 is configured to receive the target data packet in the second buffer. The target data packet includes the read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on the target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests. The target data packet does not wait for the handshake signal to be sent.

[0146] The address verification module 3230 is configured to filter valid data packets from target data packets based on the read address.

[0147] Furthermore, this embodiment provides yet another data transmission device, such as... Figure 33 The diagram shows another data transmission device. Device 3300 includes a third receiving module 3310, a request filtering module 3320, a data acquisition module 3330, and a third sending module 3340; wherein: The third receiving module 3310 is configured to receive multiple data read requests, which do not wait for the handshake signal to be sent between the first buffer and the second buffer.

[0148] The request filtering module 3320 is configured to filter multiple data read requests for invalid requests to obtain the target read request.

[0149] The data acquisition module 3330 is configured to read data according to the target read request to obtain the target data packet. The target data packet includes the read address corresponding to the target data packet in the second cache. The read address is used to filter valid data packets from the target data packet.

[0150] The third sending module 3340 is configured to send target data packets without waiting for a handshake signal.

[0151] It should be noted that other corresponding descriptions of the functional units involved in the data transmission device provided in this embodiment can be found in the description of the data transmission method in the above embodiments, and will not be repeated here.

[0152] Based on the data transmission method shown in the above embodiments, this embodiment also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method shown in the above embodiments.

[0153] Based on the methods shown in the above embodiments, this embodiment also provides a computer program product on which a computer program is stored, and when the computer program product is executed by a processor, it implements the methods shown in the above embodiments.

[0154] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0155] Based on the method shown in the above embodiments, and Figure 31 , Figure 32 , Figure 33 To achieve the above objectives, the present application also provides an electronic device, such as a terminal device, in the virtual device embodiment shown. The electronic device includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to implement the method shown in the above embodiment.

[0156] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0157] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0158] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the aforementioned physical device, supporting the operation of information processing programs and other software and / or programs. The network communication module is used to enable communication between the various components within the storage medium, as well as communication with other hardware and software in the information processing physical device.

[0159] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. Compared with the current related technologies, this solution can realize uninterrupted transmission of data read requests, effectively improve the data interaction efficiency between caches, and improve the utilization of bus bandwidth and resources. Especially in the working scenario of high-latency transmission between the first and second caches and the existence of cancellation and retransmission actions, relying on the design of continuous transmission of data read requests, invalid request filtering, and address verification and identification of messages, new requests can be continuously sent without waiting for all invalid request data packets generated during the cancellation and retransmission process to return, avoiding the problem of invalid requests occupying the transmission process and bus resources, and effectively solving the defects of transmission blocking, low efficiency, and poor resource utilization in high-latency scenarios.

[0160] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0161] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A data transmission method, characterized in that, include: Send multiple data read requests from the first cache to the second cache, wherein the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache; Receive a target data packet sent by the second cache, wherein the target data packet includes a read address corresponding to the target data packet in the second cache, and the target data packet is obtained by reading data based on a target data read request, wherein the target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests; The target data packet is sent to the first buffer, and the read address is used to filter valid data packets from the target data packet. The target data packet does not wait for the handshake signal to be sent.

2. The method according to claim 1, characterized in that, Sending multiple data read requests from the first cache to the second cache includes: Using a one-way streaming method, each data read request from the first cache is sent sequentially to the second cache.

3. The method according to claim 1 or 2, characterized in that, Each of the data read requests includes a first transmission enable signal in the first cache, the first transmission enable signal being used to identify the data read request as an acceptable data read request.

4. The method according to claim 1 or 2, characterized in that, Each of the data read requests contains a transmission identifier from the first cache; multiple data read requests may contain the same transmission identifier, or each read request may contain a different transmission identifier.

5. The method according to claim 1 or 2, characterized in that, The step of receiving the target data packet sent by the second buffer includes: The target data packets sent by the second buffer are received sequentially using a one-way streaming transmission method.

6. The method according to claim 1 or 2, characterized in that, The target data packet includes a second transmission enable signal in the second buffer, which is used to identify the target data packet as an receivable data packet.

7. The method according to claim 1 or 2, characterized in that, The target data packet contains the same transport identifier as the target data read request.

8. The method according to claim 1 or 2, characterized in that, The target data message includes the target data block from among multiple data blocks corresponding to the cache line in the target data read request, and the offset address of the target data block, wherein the offset address of the target data block indicates the position of the target data block in the cache line.

9. A data transmission method, characterized in that, include: Send multiple data read requests, and the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache; Receive the target data packet in the second cache, the target data packet includes the read address corresponding to the target data packet in the second cache, the target data packet is obtained by reading data based on the target data read request, the target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests, the target data packet does not wait for the handshake signal to be sent; Based on the read address, valid data packets are filtered from the target data packets.

10. The method according to claim 9, characterized in that, Sending multiple data read requests includes: Upon receiving the first signal, a target data read request is sent, wherein the target data read request shares the same transmission identifier with at least one of the plurality of data read requests, and the first signal is used to invalidate the data read requests other than the target data read request.

11. The method according to claim 10, characterized in that, The step of filtering valid data packets from the target data packets based on the read address includes: The read address carried in the target data packet is compared with the request address corresponding to the target data read request. If they match, the target data packet is determined to be a valid data packet.

12. The method according to any one of claims 9-11, characterized in that, The method further includes: Upon receiving a second signal, the target data packet is discarded, and the second signal is used to trigger the first buffer to enter a sleep mode.

13. A data transmission method, characterized in that, include: Receive multiple data read requests, and the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache; The multiple data read requests are filtered for invalid requests to obtain the target read request; Based on the target read request, data is read to obtain a target data packet. The target data packet includes a read address corresponding to the target data packet in the second cache. The read address is used to filter valid data packets from the target data packet. The target data packet is sent without waiting for the handshake signal to be sent.

14. The method according to claim 13, characterized in that, The step of filtering invalid data read requests from multiple requests to obtain the target read request includes: In the case where multiple data read requests include data read requests with the same transmission identifier, the latest data read request received based on the data read requests with the same transmission identifier shall be the target read request.

15. A data transmission system, characterized in that, include: First buffer, second buffer, and transmission bus; The first buffer is used to send multiple data read requests through the transmission bus, and the multiple data read requests do not wait for the handshake signal to be sent between the first buffer and the second buffer; Receive the target data packet in the second buffer; Based on the read address corresponding to the target data packet, select valid data packets from the target data packet; The second buffer is used to receive multiple data read requests via the transmission bus; The multiple data read requests are filtered for invalid requests to obtain the target read request; The target data packet is obtained by reading data according to the target read request; The target data packet is sent without waiting for the handshake signal to be sent. The transmission bus is used to send multiple data read requests from the first cache to the second cache; Receive the target data packet sent by the second buffer; Send the target data packet to the first cache.

16. A data transmission device, characterized in that, The device includes a first transmitting module, a first receiving module, and a second transmitting module; wherein: The first sending module is configured to send multiple data read requests from the first cache to the second cache, wherein the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache; The first receiving module is configured to receive a target data packet sent by the second cache. The target data packet includes a read address corresponding to the target data packet in the second cache. The target data packet is obtained by reading data based on a target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests. The second sending module is configured to send the target data packet to the first buffer, and the read address is used to filter valid data packets from the target data packet. The target data packet does not wait for the handshake signal to be sent.

17. A data transmission device, characterized in that, The device includes a second transmitting module, a second receiving module, and an address verification module; wherein: The second sending module is configured to send multiple data read requests, wherein the multiple data read requests do not wait for the handshake signal to be sent between the first cache and the second cache; The second receiving module is configured to receive a target data packet in the second buffer. The target data packet includes a read address corresponding to the target data packet in the second buffer. The target data packet is obtained by reading data based on a target data read request. The target data read request is the remaining data read request obtained after filtering invalid requests from multiple data read requests. The target data packet does not wait for the handshake signal to be sent. The address verification module is configured to filter valid data packets from the target data packets based on the read address.

18. A data transmission device, characterized in that, The device includes a third receiving module, a request filtering module, a data acquisition module, and a third sending module; wherein: The third receiving module is configured to receive multiple data read requests, and the multiple data read requests do not wait for the handshake signal to be sent between the first buffer and the second buffer; The request filtering module is configured to filter multiple data read requests for invalid requests to obtain the target read request; The data acquisition module is configured to read data according to the target read request to obtain a target data packet. The target data packet includes a read address corresponding to the target data packet in the second cache. The read address is used to filter valid data packets from the target data packet. The third sending module is configured to send the target data packet, which does not wait for the handshake signal to be sent.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 8, or the method of claims 9 to 12, or the method of claim 13 or 14.

20. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 8, or the method of claims 9 to 12, or the method of claim 13 or 14.

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