Method for establishing communication and electronic device

Abstract

The application discloses a communication establishing method and an electronic device, and relates to the computer field, and comprises the following steps: determining N channels included in a target link when a first instruction is received; and issuing a first on instruction to each logical control unit according to the level of each logical control unit included in a multi-level logical control unit. The first on instruction issued according to the level of each logical control unit ensures that the on of the target link is carried out from top to bottom, step by step and in order, and each level of logical control unit only controls the on of the channel used for connecting the logical control unit of the adjacent level, can quickly switch to the channel corresponding to the target module according to the actual demand, solves the technical problem that it is difficult to effectively establish the communication between the controller and the module under the multi-module architecture in the related art, and achieves the technical effects of flexibly turning on the channel and effectively establishing the communication between the controller and the module.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method for establishing communication channels and an electronic device. Background Technology

[0002] In related technologies, when multiple modules exist in a system, serial port signal switching is typically achieved using hardware switches. The core approach involves a controller selecting between several local serial port sources. However, when the number of modules is sufficiently large, this method becomes problematic due to physical wiring limitations and a rapid increase in the number of channels. This necessitates manual configuration, which is prone to timing errors and signal conflicts leading to data mistransmission, and unstable communication between the controller and modules. Currently, no effective solution exists in these technologies to address the technical challenges of effectively implementing communication between the controller and modules in multi-module architectures. Summary of the Invention

[0003] This application provides a communication establishment method and an electronic device to at least solve the technical problem of difficulty in effectively establishing communication between the controller and modules in a multi-module architecture in the related art.

[0004] This application provides a communication establishment method executed by a target controller, comprising: upon receiving a first instruction, determining N channels included on a target link, wherein the target link is used to connect the target controller and a target module, the first instruction is used to instruct the establishment of communication between the target controller and the target module, each of the N channels is used to connect adjacent levels of logic control units included in a multi-level logic control unit, the highest level logic control unit included in the multi-level logic control unit is the logic control unit of the target controller, the lowest level logic control unit included in the multi-level logic control unit is the logic control unit of the target module, and N is an integer greater than 1; and issuing a first activation instruction to each logic control unit according to the level of each logic control unit included in the multi-level logic control unit, wherein the first activation instruction is used to instruct each logic control unit to activate the channel included in the N channels used to connect each logic control unit with the next level logic control unit, so as to establish communication between the target controller and the target module.

[0005] This application also provides a communication establishment apparatus, comprising: a determining module, configured to determine N channels included on a target link upon receiving a first instruction, wherein the target link is used to connect a target controller and a target module, the first instruction is used to instruct the establishment of communication between the target controller and the target module, each of the N channels is used to connect adjacent levels of logic control units included in a multi-level logic control unit, the highest level logic control unit included in the multi-level logic control unit is the logic control unit of the target controller, the lowest level logic control unit included in the multi-level logic control unit is the logic control unit of the target module, and N is an integer greater than 1; and a sending module, configured to send a first activation instruction to each logic control unit according to the level of each logic control unit included in the multi-level logic control unit, wherein the first activation instruction is used to instruct each logic control unit to activate the channel included in the N channels used to connect each logic control unit with the next level logic control unit, so as to establish communication between the target controller and the target module.

[0006] This application also provides a task execution system, including a target controller, a target module, and a multi-level logic control unit. The target controller and the target module are connected via a target link, which includes N channels. Each of the N channels is used to connect to adjacent levels of logic control units within the multi-level logic control unit. The highest level logic control unit in the multi-level logic control unit is the logic control unit of the target controller, and the lowest level logic control unit is the logic control unit of the target module. N is an integer greater than 1. The target controller performs the following operations: upon receiving a first instruction, it determines the N channels on the target link; according to the level of each logic control unit in the multi-level logic control unit, it issues a first activation instruction to each logic control unit, wherein the first activation instruction instructs each logic control unit to activate the channel among the N channels used to connect each logic control unit to the next level logic control unit, thereby establishing communication between the target controller and the target module.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the steps of the above-described method when executing the computer program.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0010] This application, upon receiving the first instruction, determines the N channels included in the target link and clarifies which levels of logic control units each channel connects to. The entire target link is then subdivided into multiple independently controllable channels. Each level of logic control unit only controls the conduction of the channel used to connect to the adjacent level of logic control unit. Subsequently, conduction instructions are issued according to the hierarchy of logic control units, ensuring that the conduction of the target link proceeds top-down, step-by-step, and orderly. Each level of logic control unit can quickly switch to the channel corresponding to the target module according to actual needs, thereby establishing communication with the target controller. This solves the technical problem of effectively establishing communication between the controller and modules in multi-module architectures in related technologies, achieving the technical effect of flexible channel conduction and effective communication between the controller and modules. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram illustrating an application scenario of a communication establishment method according to an embodiment of this application;

[0013] Figure 2 This is a flowchart illustrating a method for establishing communication according to an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of the instruction stream transmission of an artificial intelligence server according to an embodiment of this application;

[0015] Figure 4 This is a flowchart illustrating a method for sending a first activation command according to an embodiment of this application;

[0016] Figure 5 This is a schematic diagram of instruction transmission within a server according to an embodiment of this application;

[0017] Figure 6 This is a schematic diagram of the internal structure of a motherboard according to an embodiment of this application;

[0018] Figure 7 This is a flowchart illustrating a method for establishing communication with a target module according to an embodiment of this application;

[0019] Figure 8 This is a structural block diagram of a communication establishment apparatus according to an embodiment of this application;

[0020] Figure 9 This is a computer system architecture block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application. Furthermore, in the absence of conflict, the various embodiments and features in the embodiments of this application can be arbitrarily combined with each other in principle.

[0022] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] According to one aspect of the embodiments of this application, a method for establishing communication is provided. Optionally, in this embodiment, the above method may be applied, but is not limited to, to applications such as... Figure 1 The hardware environment shown includes terminal device 102 and server 104. Server 104 can be connected to terminal device 102 via a network and can be used to provide services (e.g., application services, etc.) to terminal device 102 or clients installed on terminal device 102. A database can be set up on server 104 or independently of server 104 to provide data storage services for server 104.

[0025] The aforementioned network may include, but is not limited to, at least one of the following: wired network and wireless network. The aforementioned wired network may include, but is not limited to, at least one of the following: wide area network (WAN), metropolitan area network (MAN), and local area network (LAN). The aforementioned wireless network may include, but is not limited to, at least one of the following: Wireless Fidelity (WIFI) and Bluetooth. Terminal device 102 may be, but is not limited to, a personal computer (PC), mobile phone, tablet computer, etc. Server 104 may be, but is not limited to, a cloud server, server cluster, or other server types.

[0026] The communication establishment method in this application embodiment can be executed by server 104 or terminal device 102. It should be noted that both the server and terminal device executing the communication establishment method in this application embodiment include a target controller, a target module, and a multi-level logic control unit. When the controller in terminal device 102 executes the communication establishment method provided in this application embodiment, it includes, but is not limited to, debugging a specific device in terminal device 102 to determine whether the specific device can work normally or the cause of a malfunction; when the controller in server 104 executes the communication establishment method provided in this application embodiment, it includes, but is not limited to, receiving log data transmitted by the target module in server 104 and debugging the target module to determine whether the target module can work normally or the cause of a malfunction.

[0027] In related technologies, when communication needs to be established within the server 104, the Baseboard Management Controller (BMC) can act as the target controller to establish the communication link. As the management core of the server, the BMC can undertake the monitoring and management functions of the entire server system, including but not limited to power management, sensor monitoring, and remote control. Since the BMC itself can also run an independent embedded system, it may also require a debugging interface to maintain its firmware or operating system. Furthermore, the BMC typically does not have a connected display or other human-machine interface. Therefore, debugging the BMC system requires relying on a Universal Asynchronous Receiver / Transmitter (UART) serial port as a console input / output method.

[0028] Therefore, in related technologies, the following methods are commonly used to establish communication links in server systems: Method 1: Reserve independent physical connectors, such as pin headers / connectors, for each interface requiring debugging. Debuggers need to manually change connections between different debugging targets, plugging and unplugging debugging cables to different serial port connectors. Method 2: Select the route of serial port signals using hardware switches or jumpers. For example, add a Dual In-line Package (DIP) DIP switch to the UART switching circuit, using different switch combinations to control the Complex Programmable Logic Device (CPLD) to switch different UART signals to a shared port. In this case, designers need to predefine which serial port path corresponds to which switch combination, and change the signal path inside the CPLD by switching the position of the DIP switch when switching is required. Method 3: Serial port switching based on BMC and single-level CPLD. In other words, a CPLD is placed on the motherboard, and the BMC issues commands to it via the Inter-Integrated Circuit (I2C) or General-Purpose Input / Output (GPIO) to control the multiplexer inside the CPLD to connect the required UART signal. For example, the BMC's web interface provides options, allowing the administrator to remotely select the target serial port path, and the BMC sends the command to the CPLD to open the corresponding serial port channel. The BMC software handles the switching of serial ports between multiple chips, allowing multiple chips (such as the BMC itself, and the UART on a PCIe expansion card) to share the same physical serial port interface.

[0029] However, the above methods have the following problems: Method 1 requires one port to correspond to one debugging interface, necessitating the deployment of multiple debugging connectors on the same server motherboard. Switching between multiple serial ports requires manual disassembly and assembly (for example, for each UART signal on the motherboard, manual plugging and unplugging is necessary to select the desired debugging target). This design, with multiple serial ports each having its own independent connector, occupies board space, increases wiring complexity, and reduces switching efficiency. Furthermore, long-distance, multi-point UART signal wiring introduces signal integrity issues, leading to unstable serial communication. Method 2 requires manual opening of the chassis to operate the switch. For deployed servers, this method of stopping the system, opening the chassis, and adjusting the switch is inconvenient and can result in the loss of incomplete data or the accidental transmission of data to the wrong target device. Method 3, when the server system includes a large number of modules, also results in extremely complex internal wiring.

[0030] In other words, with the evolution of server architecture, a single server chassis may contain multiple modules with independent serial ports (for example, high-density servers or acceleration systems may install multiple OAM acceleration modules, each of which may have a management controller or UART interface for status monitoring and debugging). In the methods described above, the UART signals of all modules (such as multiple OAM modules) must be directly wired to the motherboard, and it is impossible to access all modules through a single entry point. When the motherboard needs to directly connect the UART signal lines of multiple modules, these signal lines are very dense and will cross each other, causing signals sent by unselected modules to interfere with the signals sent by the currently selected module that the controller needs to receive. These related technologies are constantly increasing the complexity of motherboard design, making it difficult for the controller to reliably establish end-to-end communication with the modules, resulting in the technical problem of difficulty in effectively establishing communication between the controller and modules in a multi-module architecture.

[0031] To address the aforementioned issues, this application provides a communication establishment method and an electronic device. The controller centrally controls communication between the controller and various modules, and employs a multi-level logic control unit to flexibly establish channels between the controller and modules. This effectively establishes communication between the controller and modules without increasing the complexity of the motherboard design or wiring.

[0032] Taking the communication establishment method in this embodiment as an example, which is executed by the target controller included in server 104, Figure 2 This is a flowchart illustrating a communication establishment method according to an embodiment of this application, as shown below. Figure 2 As shown, the process of this method may include the following steps:

[0033] Step S202: Upon receiving the first instruction, determine the N channels included on the target link, wherein the target link is used to connect the target controller and the target module, the first instruction is used to instruct the establishment of communication between the target controller and the target module, each of the N channels is used to connect the logic control units of adjacent levels included in the multi-level logic control unit, the logic control unit of the highest level included in the multi-level logic control unit is the logic control unit of the target controller, the logic control unit of the lowest level included in the multi-level logic control unit is the logic control unit of the target module, and N is an integer greater than 1;

[0034] Optionally, the application scenarios of the communication establishment method in this embodiment include, but are not limited to, scenarios such as: high-speed computing acceleration systems, blade server backplane management, and multi-node shared debugging terminals. For example, in industrial control systems, it establishes a serial debugging link between the main control unit and the input / output (I / O) expansion modules; initializes serial communication between the flight management computer and distributed avionics modules (such as radar and navigation units) in avionics systems; diagnoses the serial routing between the central gateway and multiple electronic control units (ECU) sub-modules in intelligent connected vehicles; and upgrades the firmware channel between the main control board and multi-level RF / baseband expansion cards in communication base stations.

[0035] Optionally, the target controller in this embodiment has command issuance capability and topology awareness capability. The target controller presents a unified serial port access point, allowing administrators to access the serial port of any target device through a single interface. When the target controller is a controller included in a server or data center, it includes, but is not limited to, a BMC, a System on Chip (SOC), or a Microcontroller Unit (MCU). When the target controller is a controller included in a terminal device, it includes, but is not limited to, an MCU, a System Management Unit (SMU), or a communication gateway.

[0036] Optionally, the target module in this embodiment includes, but is not limited to, functional modules in the server system that require access to a serial communication interface, such as an Open Compute Accelerator Module (OCP Accelerator Module, or OAM), a PCIe expansion card, a smart network card, or a debug port of the Central Processing Unit (CPU) on the motherboard. The target module may have a built-in UART interface for firmware debugging, log output, or firmware updates, but it does not have independent network management capabilities. For example, in server maintenance and fault diagnosis, system logs (such as Basic Input / Output System (BIOS) logs, BMC logs, and hardware status information) can be obtained through the target module's serial port, and serial port redirection and management of remote modules can be performed.

[0037] Optionally, the target module in this embodiment includes, but is not limited to, an embedded functional sub-module that is internal or external to the terminal device and has an independent debugging serial port but no independent network management capability. For example, a communication coprocessor as a target module in an industrial control terminal, a sensor fusion chip as a domain controller for an Advanced Driver Assistance System (ADAS) in an intelligent connected vehicle, and a control MCU as an X-ray generating module in medical imaging equipment.

[0038] Optionally, in this embodiment, the target link refers to the end-to-end serial communication physical channel constructed between the target controller and the target module to establish communication. This link is not a single physical cable, but consists of N serial logical channels, each channel connecting to the logical control unit of the adjacent level. The establishment of the target link is dynamic and on-demand, activated only upon receiving the first instruction, and immediately disconnected after communication ends.

[0039] Optionally, the N channels in this embodiment are N serially connected logical signal paths constituting the target link, where N is an integer greater than 1. Each channel corresponds to the physical connection interface between two levels of logic control units. For example, in a three-level architecture, N=2, and these two channels correspond to the channel between the motherboard CPLD and the PCIe switch board CPLD, and the channel between the PCIe switch board CPLD and the OAM CPLD, respectively. Each channel is electrically selected by a multiplexer or tri-state buffer inside the CPLD, and is only turned on when activated by an instruction, remaining in a high-impedance state at other times to achieve electrical isolation.

[0040] Optionally, the multi-level logic control unit in this embodiment is a programmable logic device deployed on different levels of hardware boards, including but not limited to CPLDs, Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). Each level of logic control unit is responsible for connecting its upper-level and lower-level units and controlling the conduction or disconnection of its own channels according to the instructions issued by the target controller. For example, the motherboard CPLD is the first level, managing the motherboard's local serial ports and channels to the expansion board; the PCIe switch board CPLD is the second level, aggregating serial port signals from multiple OAMs.

[0041] Optionally, in this embodiment, the highest-level logic control unit is the one closest to the target controller, typically the motherboard CPLD, which communicates directly with the target controller (such as the BMC) via a bus. As the first hop in the entire multi-level link, it is responsible for receiving instructions from the target controller and forwarding them to the next level, or directly connecting to the local serial port (such as the CPU debug port). The highest level refers to the logic control unit in the target link that is closest to the target controller and has the highest level number, relative to the N channels. The highest-level logic control unit includes, but is not limited to, logic control units located on the same motherboard as the target controller.

[0042] Optionally, in this embodiment, the lowest-level logic control unit is the logic control unit closest to the target module, typically an OAM CPLD or a terminal CPLD on an expansion card. It is directly connected to the UART signal line of the target module. Upon receiving instructions from the higher level, it connects the module's internal serial port to the uplink, performing auxiliary functions including but not limited to level conversion, signal buffering, and status feedback. The lowest level refers to the logic control unit furthest from the target controller and with the lowest level number in the target link; it is the endpoint of the communication link. The lowest-level logic control unit includes, but is not limited to, the logic control units included in the target module.

[0043] Step S204: According to the hierarchy of each logic control unit included in the multi-level logic control unit, a first conduction command is issued to each logic control unit. The first conduction command is used to instruct each logic control unit to conduct the channel included in the N channels for connecting each logic control unit with the next level logic control unit, so as to establish communication between the target controller and the target module.

[0044] Optionally, in this embodiment, the first activation command is issued by the target controller to instruct the activation of the channel connecting the current logic control unit and the next-level logic control unit. Upon receiving the first command, the current logic control unit configures a multiplexer through its internal logic circuitry to activate the specified TX / RX signal path, while simultaneously placing other non-target channels in a high-impedance state. The first activation command includes, but is not limited to, fields such as channel number, action type (activation), target module identifier, and logic control unit identifier.

[0045] The above method will be illustrated with an example below. Figure 3 This is a schematic diagram of the instruction flow transmission of an artificial intelligence (AI) server according to an embodiment of this application, as shown below. Figure 3As shown, in this AI server, the Baseboard Management Controller (BMC) 321 on the motherboard 32 can receive instructions (such as the first instruction mentioned above) sent from the remote maintenance terminal 30 through the network management interface on the motherboard 32. The BMC 321 can send instructions to the complex programmable logic device (i.e., the motherboard CPLD) 323 on the motherboard via the bus. There is a bidirectional data path between the BMC 321 and the universal asynchronous transceiver (i.e., BMCUART) 322 of the Baseboard Management Controller: one path is that the BMC 321 outputs to the BMC UART 322, and the BMC 321 sends its own logs, debugging information, etc. to the BMC UART 322 through the unified universal asynchronous transceiver port (i.e., the unified UART port) (it should be noted that the unified UART port used here is multiplexed, that is, it undertakes both input and output functions at the same time), and the other path is that the BMC UART 322 forwards local or remote management serial port data to the BMC 321. The BMC 321 and the local serial port source 324 included in the motherboard 32 serve as two independent UART candidate sources. Both can be connected to the motherboard CPLD 323 via motherboard traces, driving the CPLD 323 to select and activate the corresponding channel. The motherboard CPLD 323 can send the target data received from the next-level CPLD or module back to the BMC UART 322, which then sends the target data to the BMC 321. Upon receiving an instruction (such as the first activation instruction mentioned above), the motherboard CPLD 323 selects the corresponding Universal Asynchronous Receiver / Transmitter link (i.e., the aforementioned channel) and activates that link to achieve inter-board connection between the motherboard 32 and the switching board 34. In other words, the motherboard CPLD 323 is used for first-level selection and activation. It should be noted that, in practice, the motherboard CPLD 323 is connected to the complex programmable logic device (i.e., the switching board CPLD 341) included in the switching board 34 via the Universal Asynchronous Receiver / Transmitter link (i.e., the UART link). After receiving the first activation command, the switching board CPLD 341 performs secondary gating and activation, that is, it selects and activates the corresponding UART link connected to the Open Computing Acceleration Module Carrier (i.e., OAM carrier board) 36 to achieve inter-board connection between the switching board 34 and the OAM carrier board 36. It should be noted that, in practice, the switching board CPLD 341 is connected to the complex programmable logic device (i.e., OAM carrier board CPLD 361) included in the OAM carrier board 36 via the UART link. The OAM carrier board CPLD 361, acting as a tertiary gating mechanism, is connected to the complex programmable logic devices of each Open Computing Acceleration Module via the UART link.After receiving the first conduction command, the OAM carrier board CPLD 361 selects and activates the UART link for connection with the target module, thereby establishing the connection between the OAM carrier board 36 and the Complex Programmable Logic Device (OAM CPLD) of the Open Compute Acceleration Module. It should be noted that each OAM CPLD is responsible for bridging the UART serial port channel of the Graphics Processing Unit (GPU).

[0046] Additionally, it should be noted that, Figure 3 This is merely an example. In actual use, a server would include multiple switching boards, multiple OAM carrier boards, and multiple OAMs. That is, the motherboard CPLD would connect to the CPLDs of multiple switching boards; each switching board CPLD would further connect to its corresponding OAM carrier board, and each OAM carrier board would connect to its corresponding OAM. The BMC in the server, acting as the target controller, can dynamically establish an end-to-end communication link with the AI ​​chip debugging serial port inside the target OAM by executing the method provided in this embodiment based on the first instruction sent by the remote maintenance terminal. This is achieved through multiple levels of logic control units, including the motherboard CPLD, PCIe switching board CPLD, and OAM CPLD, based on the first instruction received. This allows maintenance personnel to remotely access, diagnose, and configure the underlying hardware firmware without physically touching the equipment.

[0047] exist Figure 3In this system, the BMC 321, located on the server motherboard, serves as the central control hub for the centralized management of the entire serial port. The BMC 321 has at least one UART interface (which can be multiplexed for multiple targets), allowing communication with maintenance personnel via network or physical serial ports. The BMC 321 communicates with the motherboard's CPLD 323 via I2C, the Serial Peripheral Interface (SPI), or a specific GPIO bus, sending control commands to configure the serial port path. The motherboard CPLD 323, located on the motherboard, connects to the local serial port signals that require centralized management and connects to the CPLDs of next-level boards (such as PCIe switch boards) via dedicated interfaces. The motherboard CPLD 323 incorporates a multiplexer switch logic to select one of multiple serial port signal sources to connect to the BMC's UART, handling the first-level serial port selection. This ensures that only the selected channel is activated at the motherboard level, while other unselected serial port signals are controlled by the motherboard CPLD 323 to remain in a high-impedance state or at a fixed level, without affecting the bus. The switching board CPLD 341 is a second-level CPLD, including but not limited to those deployed on a PCIe switching board (in which case the server connects to multiple OAM carrier boards 36 via a single PCIe expansion / switching board). The switching board CPLD 341 communicates upstream with the motherboard CPLD 323 via an inter-board connection, and downstream with the CPLDs of several OAM carrier boards 36. When the switching board CPLD 341 receives the first conduction command from the motherboard CPLD 323 or BMC 321, it selects the corresponding OAM carrier board from the multiple downstream OAM carrier boards 36. OAM carrier boards are also equipped with CPLDs; these OAM carrier board CPLDs are third-level CPLDs and can be selected to connect to different modules' UARTs. The OAM CPLD is the lowest-level logic control unit. The OAM CPLD connects to the internal serial port of the module on one hand, and to the higher-level logic control unit (i.e., the OAM carrier board CPLD) on the other. OAM's CPLD can be used for module-specific function control (such as power timing and status monitoring). When the upstream logic control unit does not select the module, OAM's CPLD sets the module's UART transmit signal to a high-impedance / disabled state to prevent bus interference. When the module is selected, it connects the module's UART to the upstream path and can provide buffering, baud rate matching, and other functions. Figure 3The multi-level structure shown forms a link starting from the BMC, sequentially passing through the motherboard CPLD, the switching board CPLD, the OAM carrier board CPLD, and finally reaching the OAM CPLD. This link corresponds to the serial port channel of the selected module. Compared to the single-level switch in related technologies, the above structure has the advantages of hierarchical control and proximity selection. Each CPLD only manages a few channels related to the next level, reducing the number of channels that a single chip needs to directly handle, thus reducing complexity and wiring burden. Utilizing the programmable switching logic of the CPLD and the software control of the BMC, dynamic and flexible switching of the serial port channel is achieved. Administrators do not need to stop or disassemble the device, nor do they need to manually flip jumpers or DIP switches; they only need to remotely send commands to complete the serial port switching and establish communication between the BMC and the corresponding module. A single BMC and distributed CPLDs replace the multiple independent debugging ports and multiple cables used in the aforementioned related technologies. The shared unified serial port entry avoids the need to lay out independent connectors for each device, saving space and interface material costs. At the same time, since it is not necessary to configure a complete BMC for each module, only a lower-cost CPLD is used as a slave node, reducing the overall hardware cost. At the BMC chip level, the time-division multiplexing capability of a single-channel UART can also be utilized to achieve serial communication with multiple devices and modules, reducing chip design and usage costs.

[0048] It should be noted that, Figure 3 The connections between the various devices included are only drawn to illustrate the flow of instructions and do not represent the actual deployment and connection relationships of the various devices in the server. Figure 3 The server architecture shown is for illustrative purposes only. The method provided in this embodiment is not limited to the three-tier architecture described above. It can be applied to more layered architectures, such as four-tier or five-tier architectures, depending on actual needs. For example, when Figure 3 When adding a new OAM to the server shown, simply connect the new OAM to the CPLD interface on the switch board and register its path in the BMC software to integrate it into the centralized management system; no disruptive changes to the overall architecture are required. Furthermore, if the server needs to add a sufficient number of OAMs, it can also... Figure 3 Based on the structure shown, an additional switching board CPLD is added for management. Each level is connected in series to form a deeper coverage area, extending to multi-board scenarios. Conversely, for structures with only a motherboard and a few OAMs, the intermediate switching board can be omitted, and the motherboard CPLD can directly connect to the OAM CPLD. Figure 3In the example shown, the UART electrical standard is used to achieve inter-board transmission of data or instructions. However, in some situations with high anti-interference requirements or long distances, other transmission technologies can be introduced, and this embodiment does not limit this. For example, a high-speed serial transceiver (SERDES) or a module in Ethernet can be used between the motherboard and the expansion board to encapsulate the UART signal and transmit it at high speed, and then decapsulate and restore the UART on the target board.

[0049] In this embodiment, upon receiving the first instruction, the target link is divided into multiple independently controllable channels by identifying the N channels on the target link and determining which levels of logic control units each channel connects to. Each level of logic control unit only controls the conduction of the channel used to connect to the adjacent level of logic control unit. Then, conduction instructions are issued according to the hierarchy of logic control units, ensuring that the conduction of the target link is top-down, step-by-step, and orderly. Each level of logic control unit can quickly switch to the channel corresponding to the target module according to actual needs, thereby establishing communication with the target controller. The target controller can access the module through the highest-level logic control unit. For the target controller, this means accessing all modules through a single entry point. Furthermore, establishing communication between the target controller and the target module is fully automatic and requires no manual intervention. This solves the technical problem of effectively establishing communication between the controller and modules in multi-module architectures in related technologies, achieving the technical effect of flexible channel conduction and effective establishment of communication between the controller and modules.

[0050] In one exemplary embodiment, after issuing a first conduction command to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit, the method further includes: receiving a second command; and, if it is determined based on the second command that the target link needs to be disconnected, issuing a disconnection command to each logic control unit according to the hierarchy of each logic control unit, so as to instruct each logic control unit to disconnect the channel included in the N channels for connecting each logic control unit with the next level logic control unit.

[0051] Optionally, in this embodiment, the second instruction is a control command sent from a remote maintenance terminal or local management interface to the target controller (such as the BMC) to terminate the current communication link or switch to another target module. The second instruction includes, but is not limited to, Intelligent Platform Management Interface (IPMI) commands, Secure Shell (SSH) command lines, web interface click operations, or Application Programming Interface (API) calls. For example, when a maintenance personnel sends an "exit" command to indicate exiting the current serial port session, the BMC closes the channel between the BMC and OAM 2: the BMC first instructs the OAM 2 CPLD to disconnect the UART, then instructs the switchboard CPLD to close the channel with the OAM 2 CPLD, and finally instructs the motherboard CPLD to close the channel with the switchboard CPLD (restoring to idle or default mode).

[0052] Optionally, the disconnect command in this embodiment refers to the reverse control command issued by the target controller to the multi-level logic control units (such as the motherboard CPLD, PCIe switching board CPLD, and OAM CPLD) after receiving the second command. Its function is to instruct each logic control unit to close the currently active channel, set the corresponding UART transmit (TX) signal to a high impedance state, cancel the drive at the receive (RX) end, and restore the electrical isolation state.

[0053] Optionally, the target link in this embodiment, the established end-to-end serial communication path from the target controller to the target module, consists of N serially connected channels. During the disconnection phase, disconnecting the target link is not simply closing a port, but rather disconnecting all intermediate connections from top to bottom step by step, ensuring that each logical control unit in the path returns to its default isolation state.

[0054] Optionally, each logic control unit in this embodiment specifically refers to each level of logic control unit constituting the target link (such as motherboard CPLD, PCIe switch board CPLD, OAM CPLD, etc.). During the disconnection phase, each logic control unit needs to respond to the disconnection command independently, including but not limited to performing the following operations: disabling its own output driver, making the UART TX line high-impedance to avoid interfering with other unselected modules; disconnecting the channel with the next level logic control unit; and clearing the internal status register to ensure that it is in the initialization state when it is turned on again.

[0055] Optionally, in this embodiment, the step-by-step delivery means that the disconnect command is transmitted in the exact opposite hierarchical order to the connect command, that is, it is executed in reverse order from the lowest level (end CPLD) to the highest level (BMC). For example, in actual use, the disconnect command first notifies the OAM CPLD to disconnect the local connection, then notifies the PCIe switch board CPLD to cut off the path, and finally the motherboard CPLD disconnects the connection with the BMC.

[0056] In this embodiment, when it is necessary to disconnect the target link, a disconnect command is issued to each logic control unit according to the hierarchy of each logic control unit. This ensures that the target module at the end disconnects the channel first during the disconnection process, avoiding the continued transmission of high-level signals and preventing damage to related devices caused by timing reversal. It also facilitates the target controller to dynamically switch to other modules after disconnecting from the target module, thus achieving seamless migration of serial port resources.

[0057] In one exemplary embodiment, the second instruction is used to instruct at least one of the following: establishing communication between the target controller and a first module other than the target module, wherein the target controller and the first module are connected via a first link, the first link including a channel partially located on the target link; and disconnecting communication between the target controller and the target module.

[0058] Optionally, in this embodiment, the first module other than the target module refers to another server module to be debugged that the maintenance personnel want to immediately connect to, provided that the current communication link (target link) has been established. For example, if the maintenance personnel are currently accessing the debugging serial port of OAM 3 through BMC and issue an instruction to "switch to the main CPU" or "switch to OAM 1", then in this case, the first module is the main CPU or OAM 1. The first module and the target module may share some communication paths (such as sharing a channel between the motherboard CPLD and the PCIe switch board CPLD), but the modules they ultimately need to connect to are different.

[0059] Optionally, in this embodiment, the first link is a new end-to-end serial communication path to be established between the target controller and the first module. The first link and the target link may have partially overlapping channels. For example, when the target module is OAM 3, the target link includes channels 1 between the motherboard CPLD and the first PCIe switchboard CPLD, channel 5 between the first PCIe switchboard CPLD and the second PCIe switchboard CPLD, and channel 6 between the second PCIe switchboard CPLD and the CPLD of OAM 3; when the first module is OAM 1, the target link includes channels 1 between the motherboard CPLD and the first PCIe switchboard CPLD, channel 4 between the first PCIe switchboard CPLD and the third PCIe switchboard CPLD, and channel 7 between the third PCIe switchboard CPLD and the CPLD of OAM 1. The overlapping channel between the target link and the first link is channel 1 between the motherboard CPLD and the first PCIe switchboard CPLD.

[0060] It should be noted that when the target controller only supports opening one independent session, after receiving the first instruction, the target controller needs to determine whether other communications have been established before. If so, it needs to disconnect the previous link before starting the connection of N channels to avoid resource conflicts. In other words, in this case, it is necessary to ensure that only one link is active output at any given time. Before switching the connected link, the target controller can perform a series of safety measures, including but not limited to: notifying the current channel to pause transmission or wait for transmission to complete, or marking the boundary in the buffer to prevent incomplete log fragments from being mixed. In practical use, if the target controller can support opening a second independent session, after receiving the first instruction, if it is determined that only one unrelated link is currently active, then there is no need to disconnect this unrelated link, and N channels can be directly connected. However, if after receiving the first instruction, it is found that the multiple channels on which the previously established communication link is based include the channels included in the communication between the target controller and the first module to be established this time, then in order to avoid resource usage conflicts, the previous link should be disconnected before connecting the N channels this time (if there is a corresponding resource usage policy in the system policy that can ensure that even if the first link includes some channels located on the target link, resource conflicts can be avoided and normal communication can be carried out, then the target link can be disconnected).

[0061] In related technologies, under a server architecture, communication between the target controller and the target module is achieved through centralized collection and redirection of serial port information. For example, the BMC continuously collects data from multiple physical serial ports (each physical serial port corresponds to one module), caches the logs in the BMC, and outputs them through an external serial port or network interface when needed. When a remote client sends a command to select a target serial port, the BMC outputs the data from that serial port to both the server panel's serial port (such as the local debug port) and simultaneously sends it to the remote client, achieving parallel local and remote debugging. This method requires the BMC to have multiple UART hardware interfaces to collect serial port information in parallel. However, in actual use, the UART resources of the BMC chip are limited, making it impossible to truly monitor the serial port information of multiple devices (i.e., the aforementioned multiple modules). If a UART repeater is added outside the BMC to collect serial port data, it increases hardware complexity, and in reality, it only checks one by one, failing to achieve a truly centralized and unified entry point. This embodiment, however, allows the target controller to establish communication with multiple devices when the target controller supports opening a second independent session, truly achieving the function of monitoring the serial port information of multiple devices.

[0062] In one exemplary embodiment, issuing a first activation command to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit includes at least one of the following: issuing the first activation command to each logic control unit level by level in descending order of the hierarchy of each logic control unit included in the multi-level logic control unit; or sending the first activation command to each logic control unit level by level at a preset time interval.

[0063] Optionally, in this embodiment, the hierarchical structure from largest to smallest means starting from the upper-level logic control unit closest to the target controller (i.e., the highest-level logic control unit) and sequentially downwards (towards the lowest-level logic control unit) to issue instructions. For example, in Figure 3 In the server structure shown, the first activation command is issued to each logic control unit in descending order of hierarchy within the multi-level logic control unit. Specifically, this means that the BMC first issues a command to the motherboard CPLD, which is then forwarded by the motherboard CPLD or directly issued by the BMC to the PCIe switchboard CPLD. The command is then forwarded by the switchboard CPLD or directly issued by the BMC to the OAM carrier board CPLD. Finally, the command is issued to the target OAM CPLD or forwarded via the motherboard CPLD, PCIe switchboard CPLD, and OAM carrier board CPLD.

[0064] Optionally, in this embodiment, "issuing the first conduction command to each logic control unit in descending order of the hierarchy of each logic control unit included in the multi-level logic control unit" requires that the target controller continues to send the first conduction command to the next level only after the logic control unit of the current level has completed channel conduction and confirmed that the state is stable. In other words, the logic control unit of the current level forwards the first conduction command to the next level.

[0065] Optionally, the preset time interval in this embodiment is a fixed delay time (such as 5ms, 10ms, etc.) set to ensure that each logic control unit has sufficient time to complete internal logic configuration, signal stabilization, and level establishment during the first turn-on command issuance process. This interval is pre-configured by the target controller based on parameters such as the response characteristics of the logic control unit, signal propagation delay, and UART clock jitter, and does not depend on hardware feedback.

[0066] Optionally, in this embodiment, the step-by-step transmission means that the first activation command is sent sequentially to each level of logic control unit. After each command is sent, a preset time interval is waited before sending the next command. Even if the logic control unit at the current level does not provide a confirmation signal, the transmission continues as planned.

[0067] It should be noted that in actual use, the target controller may send the first activation command to each logic control unit step by step, or the target controller may send a first activation command to the highest-level logic control unit, and then the highest-level logic control unit forwards the first activation command to the next-level logic control unit, and the next-level logic control unit forwards the first activation command to its corresponding next-level logic control unit, and so on, until the lowest-level logic control unit receives the first activation command. This embodiment does not impose any restrictions on this.

[0068] This embodiment supports issuing the first activation command in descending order of hierarchy or at preset time intervals, providing a flexible communication establishment strategy: In scenarios where real-time requirements are not high but the order and security of establishing the target link must be guaranteed, the communication between the target controller and the target module can be established by issuing the first activation command at preset time intervals; in scenarios with high real-time requirements, the first activation command can be issued in descending order of hierarchy to ensure timely detection of whether the communication between the target controller and the target module can be established normally.

[0069] In an exemplary embodiment, issuing a first activation command to each logic control unit in descending order of hierarchy in the multi-level logic control unit includes: repeatedly performing the following operations in descending order of hierarchy of each logic control unit until the (i+1)th level logic control unit is the smallest level logic control unit, where i is an integer greater than 0 and i is less than or equal to N: sending a first activation command to the i-th level logic control unit; and, if it is determined that the i-th level logic control unit has successfully activated the channel for connecting the i-th level logic control unit and the (i+1)th level logic control unit, determining the (i+1)th level logic control unit as the i-th level logic control unit for the new round.

[0070] Optionally, in this embodiment, N is the total number of channels constituting the target link (i.e., the number of layers minus one), and i represents the logic control unit sent by the current first conduction command.

[0071] Optionally, in this embodiment, successful conduction means that after receiving the first conduction command, the i-th level logic control unit has correctly configured its internal multiplexer or tri-state buffer to make the uplink port and downlink port electrically connected, and confirms through the status feedback mechanism (such as reading the status bits of the CPLD register, receiving the ACK response, and detecting whether there is a handshake signal in the downlink) that the channel has been stably activated, the driver has been enabled, there is no line conflict, and the level is stable.

[0072] The following example illustrates this embodiment. In a server with a three-tier architecture consisting of a motherboard, a switching board, and an OAM, N=2, i≤2, there are three levels of logical control units. Figure 4 This is a flowchart illustrating a method for sending a first conduction command according to an embodiment of this application. The BMC in the server motherboard is used to perform the following steps:

[0073] Step S402: Send a first turn-on command to the motherboard logic control unit, where the motherboard logic control unit is the first-level logic control unit and the highest-level logic control unit, and i=1 at this time;

[0074] Step S404: If it is determined that the motherboard logic control unit has successfully turned on the channel for connecting the motherboard logic control unit and the switch board logic control unit, and the i+1 level logic control unit is not the lowest level logic control unit (i+1=2 at this time), a first turn-on command is sent to the switch board logic control unit, wherein the switch board logic control unit is the aforementioned second level logic control unit.

[0075] In step S406, if it is determined that the switching board logic control unit has successfully connected the channel between the switching board logic control unit and the OAM logic control unit, since i+1=3 at this time and the third-level logic control unit is the lowest level logic control unit, the first connection command is no longer issued.

[0076] In this embodiment, a tree-like, layer-by-layer connection mechanism is adopted to ensure that the channel between the current level logic control unit and the next level logic control unit is connected before sending the first connection command to the next level logic control unit. This achieves the construction of a highly reliable target link and avoids cascading conflicts.

[0077] In one exemplary embodiment, after sending a first conduction command to the i-th level logic control unit, the method further includes: if a target signal is detected, determining that the i-th level logic control unit has not successfully conducted the channel for connecting the i-th level logic control unit and the (i+1)-th level logic control unit, wherein the target signal is a signal fed back by the i-th level logic control unit when the channel for connecting the i-th level logic control unit and the (i+1)-th level logic control unit has not been conducted; if the target signal is not detected, determining that the i-th level logic control unit has successfully conducted the channel for connecting the i-th level logic control unit and the (i+1)-th level logic control unit.

[0078] Optionally, in this embodiment, the target signal refers to a status indication signal actively fed back to the target controller by the i-th level logic control unit (such as the motherboard CPLD or PCIe switch board CPLD) when it fails to successfully establish a channel with the (i+1)-th level logic control unit. The target signal includes, but is not limited to, signals read via buses such as I2C, SPI, or GPIO. For example, in practical use, the i-th level logic control unit configures the GPIO to be detected as an input mode and connects a pull-down resistor (e.g., 10kΩ) between the pin and ground, so that the GPIO is fixed at a low level when the channel is not conducting. When conduction is required, the pin is extended to the peer board (or module) through an inter-board connector or cable. The peer board directly connects the signal line to its power supply VCC (or continuously outputs a high level through the GPIO of the peer controller / MCU). When the channel is conducting, the high level of the peer drives the GPIO of the board where the i-th level logic control unit is located to pull high through the conducting channel. The target controller can determine the connection status by periodically reading the GPIO level. If the reading value is low, it means that the channel has not been successfully conducted. If it is high, it confirms that the conduction is successful. It should be noted that in practical use, it is also acceptable for the GPIO to be fixed at a high level when the channel is not conducting; the high level output from the other end must meet the input threshold requirement of the GPIO of the i-th level logic control unit (e.g., a 3.3V system typically requires >2.0V); the resistance value of the pull-down resistor should not be too large (otherwise the anti-interference capability will be poor), nor should it be too small (otherwise it will form a voltage divide with the pull-up resistor at the other end, resulting in insufficient high level). The above is only an example for illustration. In actual use, the corresponding devices can be designed according to the circuit structure to implement the method provided in this embodiment. This embodiment does not impose any restrictions on this.

[0079] In this embodiment, the conduction status of the channel is determined by monitoring the target signal fed back by the i-th level logic control unit. This enables real-time perception of whether the channel is successfully conducted. Without relying on external monitoring tools, the failure of channel conduction can be automatically identified at the software level, thereby timely troubleshooting and facilitating subsequent channel conduction and the establishment of communication between the target controller and the target module.

[0080] In one exemplary embodiment, after sending a first conduction command to the i-th level logic control unit, the method further includes: reading a first value stored in a target register, wherein the first value is a value filled into the target register by the i-th level logic control unit to indicate the actual conduction state of the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit; if the first value is not completely consistent with the target value, determining that the i-th level logic control unit has not successfully conducted the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit, wherein the target value is a pre-configured value indicating that the channel is in a conduction state; if the first value is completely consistent with the target value, determining that the i-th level logic control unit has successfully conducted the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit.

[0081] Optionally, the target register in this embodiment includes, but is not limited to, a readable hardware register located inside the i-th level logic control unit (such as the motherboard CPLD or PCIe switch board CPLD), or a register located on the same board as the i-th level logic control unit. In actual use, the target register includes, but is not limited to, 8-bit or 16-bit wide, consisting of multiple status bits; where a certain bit (such as bit 0) indicates the conduction state of channel 1.

[0082] Optionally, in this embodiment, the first value is a value representing the actual conduction state of the channel, written into the target register by the i-th level logic control unit after responding to the first conduction command. This value is dynamically generated by the internal logic of the i-th level logic control unit based on the actual connection result of the physical channel, reflecting the true conduction state. Assuming the motherboard CPLD receives the first conduction command sent by the BMC to open channel 2 to the PCIe switchboard, the internal logic of the motherboard CPLD drives the multiplexer switch to switch the motherboard UART TX / RX to the PCIe board interface; at the same time, the motherboard CPLD detects whether the PCIe board CPLD returns a handshake signal (such as an acknowledgment signal); if a valid response is detected, the motherboard CPLD writes 1 to the first bit in the target register; if there is no response (possibly because the PCIe board is not powered on), the motherboard CPLD writes 0 to the first bit in the target register, and the BMC then reads the target register to determine whether the channel is successfully conducted.

[0083] Optionally, the target value in this embodiment is a desired state value pre-configured in the target controller to indicate that the channel has been successfully turned on. The target value includes, but is not limited to, values ​​set according to the specifications defined in the target register.

[0084] In one exemplary embodiment, before issuing a first activation instruction to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit, the method further includes: sending a third instruction to each logic control unit to instruct each logic control unit to configure its own communication resources, wherein the communication resources are the resources required by each logic control unit when activating the channels included in the N channels for connecting each logic control unit with the next level logic control unit.

[0085] Optionally, in this embodiment, the third instruction refers to the initialization configuration instruction sent by the target controller (such as BMC) to each level of logic control unit (motherboard CPLD, PCIe switchboard CPLD, OAMCPLD, etc.) before executing the first conduction instruction. The purpose of sending the third instruction is to allocate communication resources for each level of logic control unit in advance or to instruct each level of logic control unit to prepare the communication resources required after the conduction channel is established, so as to ensure that the subsequent channel conduction operation has a physical and logical basis.

[0086] Optionally, the third instruction in this embodiment may include, but is not limited to, baud rate setting, pin multiplexing configuration, power timing enable, clock synchronization, buffer allocation, interrupt enable, and communication protocol mode (such as UART mode).

[0087] Optionally, the communication resources in this embodiment refer to the set of hardware and logic configuration parameters necessary for each logic control unit to perform channel connection operation. They are the basic resources required for each level of logic control unit to realize functions such as serial port signal routing, level matching, timing synchronization, and electrical isolation.

[0088] Figure 5 This is a schematic diagram of instruction transmission within a server according to an embodiment of this application. Figure 5The connections between the various devices included are only illustrated to illustrate the instruction flow and do not represent the actual deployment and connection relationships of the devices in the server. The server internally includes a motherboard complex programmable logic device (CPLD) 52, a switching board complex programmable logic device (CPLD) 54, and multiple open computing acceleration module complex programmable logic devices (OAMCPLDs) 56. The local universal asynchronous transceiver source (UART source) and the BMC, as two independent UART signal sources, can both be connected to the motherboard universal asynchronous transceiver selector / switch matrix. The motherboard CPLD 52 is connected to the switching board CPLD 54 via a downlink port, and the switching board CPLD 54 is connected to different OAM CPLDs via different OAM ports. The following example illustrates the above method. After receiving the control command for configuring the motherboard CPLD to select the downlink, the motherboard's universal asynchronous transceiver selector / switch matrix determines the downlink related to the target module that needs to establish communication with the controller and prepares the necessary communication resources. After receiving the control command for configuring the switch board CPLD to select the OAM 2 port, the switch board's universal asynchronous transceiver selector / switch matrix prepares the selected port and the necessary communication resources. After receiving the control command for instructing the OAM2 CPLD to connect to the universal asynchronous transceiver, the OAM2 CPLD 56 prepares the necessary communication resources and selects the corresponding UART for the graphics processing unit (GPU) based on its internal tri-state gating, thereby achieving log acquisition. It should be noted that if other modules have not received the command to establish communication with the controller, the channels between the switch board CPLD 54 and other OAM CPLDs 56 are not connected; these channels are either open or in a high-impedance state, hence they are represented by dashed lines in the diagram. Figure 5 The motherboard CPLD can be represented by MB_CPLD, and the switching board CPLD can be represented by SW_CPLD.

[0089] Figure 5The Baseboard Management Controller (BMC) Universal Asynchronous Receiver Transceiver (UART) in a multi-level architecture includes a pair of transmit (TX) and receive (RX) signals. In a multi-level architecture, this pair of signals is typically connected to the mainboard CPLD when the line is idle, but does not further connect to any downstream devices. Each CPLD has an internal controllable switch (such as a multiplexer or tri-state buffer array) to switch the connection between its downstream ports and upstream ports. When a path is not activated, the corresponding TX / RX does not form a closed loop, thus electrically isolating the serial ports from each other. Only after receiving a command to select a path does the CPLD at that level open the corresponding switch, allowing the upstream port to be directly connected to the selected downstream port. In other words, signal isolation is achieved through the CPLD's internal tri-state driver or an external analog switch: for the UART transmit TX signal, in the unselected state, the CPLD disables its driver, placing the line at high impedance to avoid interfering with the actually selected TX signal. For UART receiving RX signals, the next higher level typically only accepts line inputs from the selected module. To prevent the TX signals from unselected modules from affecting the line inputs of the selected modules, pull-up / pull-down resistors can be used to ensure that unconducted channels remain at a logic idle level. Furthermore, in practical applications, to prevent transient impacts, multi-level CPLDs can insert a short delay before switching the channel to be activated, ensuring that the status signal of the previously activated channel dissipates or the controller notifies the other end to pause transmission before switching to the activated channel.

[0090] In this embodiment, a third command is issued before the communication channel is established. The target controller can then use its control over the logic control units at each level to determine whether each channel is ready. This ensures that each logic control unit completes the preparation of communication resources in advance, and the subsequent actual channel connection is only performed when the conditions are met. This avoids communication failures or data loss due to incomplete communication resources, further improving the success rate of the first communication.

[0091] In an exemplary embodiment, the method further includes: upon receiving a fourth instruction, sending a second conduction instruction to the highest-level logic control unit, wherein the second conduction instruction is used to instruct the highest-level logic control unit to maintain only the conduction of the second link, wherein the second link is used to sequentially connect the target controller, the highest-level logic control unit, and the hardware module, and the fourth instruction is used to instruct the hardware module to be controlled, wherein the target controller, the highest-level logic control unit, and the hardware module are all located on the same motherboard.

[0092] Optionally, in this embodiment, the fourth instruction refers to a high-level control command sent by a remote maintenance terminal (such as maintenance personnel via IPMI, SSH, or a web interface) or a local management program to the target controller, used to trigger direct control operations on local hardware modules. The fourth instruction is only used to instruct the debugging, configuration, or status query of the motherboard's local modules. For example, upon receiving a fourth instruction instructing the debugging UART of the motherboard CPU or the BMC's own UART, the highest-level logic control unit does not need to forward the instruction to the next-level logic control unit; instead, the highest-level logic control unit directly switches the relevant switches internally, connecting the corresponding signals to the BMC UART.

[0093] Optionally, the fourth instruction in this embodiment may include, but is not limited to: "read CPU serialnumber" (read the motherboard CPU serial number); "enter BIOS setup via UART" (enter BIOS configuration via serial port); "reset local FPGA" (reset the Field-Programmable Gate Array (FPGA) module on the motherboard); and "dump BMC firmware log" (export the BMC's own log).

[0094] Optionally, in this embodiment, the second conduction command is a command specifically sent by the target controller to the highest-level logic control unit after receiving the fourth command, used to keep the second link in the conduction state while forcibly disconnecting all other unrelated channels.

[0095] Optionally, in this embodiment, the second link refers to a dedicated serial communication path on the same motherboard, consisting of the target controller, the highest-level logic control unit, and hardware modules.

[0096] Optionally, in this embodiment, the hardware module refers to an onboard functional unit located on the same motherboard, equipped with a communication interface, and requiring debugging or control via a target controller. In practical use, the hardware module includes, but is not limited to, the CPU's debug serial port, a smart network card, an onboard FPGA, and a power management chip.

[0097] Figure 6 This is a schematic diagram of the internal structure of a motherboard according to an embodiment of this application, such as... Figure 6As shown, the motherboard internally includes a local serial port source 62, a complex programmable logic device (CPLD) 64, and a baseboard management controller (BMC) 66. The local serial port source 62 serves as a multi-channel debugging signal source, connected to the CPLD 64 as a UART candidate source. Upon receiving the fourth instruction, the BMC 66 sends a command to the CPLD 64 via the bus, controlling the CPLD 64 to select and switch between multiple local signal sources. The selected serial port signal can be transmitted back to the BMC UART 662 via the CPLD, and then the BMC 66 forwards the data to the local debugging interrupt or remote management platform via the serial data forwarding function. Once the second link is established, the BMC can output the data received from its UART port in two directions: either back to the administrator's remote terminal via a LAN-based serial communication (SOL) session or an SSH session, or to the front panel debugging serial port on the server for simultaneous viewing by on-site personnel. The BMC can also process the received data, such as writing it to the log buffer. When switching to another link or establishing communication between the BMC and other modules, the BMC can save the log generated when the previous communication was established for later analysis, thus achieving centralized collection and management of serial port output. Then, it clears the buffer to prepare for receiving data transmitted by the newly established communication.

[0098] This embodiment enables the forced activation of the second link when debugging local hardware modules on the motherboard (such as the CPU or BMC itself) is required, thus allowing switching between local debugging mode and remote module debugging mode.

[0099] In one exemplary embodiment, the second activation instruction is used to instruct the highest-level logic control unit to perform at least one of the following operations: if it is determined that communication between the target controller and the second module is currently established, disconnect the third link between the target controller and the second module and then activate the second link; if it is determined that communication between the target controller and the second module is not currently established, directly activate the second link.

[0100] Optionally, the second module in this embodiment is a module located outside the motherboard in the system that needs to establish communication with the target controller through a multi-level logic control unit, including but not limited to acceleration cards (such as GPUs, FPGAs) and OAMs on the PCIe switching board.

[0101] Optionally, in this embodiment, the third link refers to the complete serial communication path established between the target controller and the second module through multiple levels of logic control units. Disconnecting the third link requires the target controller to issue a disconnect command to each logic control unit according to the hierarchy of each logic control unit involved, instructing each logic control unit to disconnect the channel used to connect it with the next level logic control unit.

[0102] This embodiment avoids conflicts caused by miscommunication of internal motherboard channels due to failure to disconnect old links, and achieves automatic isolation and switching between local debugging and remote module debugging. It can intelligently determine whether other links need to be disconnected first.

[0103] In one exemplary embodiment, after determining the (i+1)th level logic control unit as the i-th level logic control unit of the new round, the method further includes at least one of the following: forwarding the first turn-on instruction to the i-th level logic control unit of the new round through the i-th level logic control unit of the previous round in a serial or parallel manner; if the level of the i-th level logic control unit of the previous round is lower than the level of the highest level logic control unit, sending the first turn-on instruction to the i-th level logic control unit of the new round through the highest level logic control unit in a serial or parallel manner.

[0104] Optionally, in this embodiment, the i-th level logic control unit in the previous round refers to the logic control unit located at the i-th level in the hierarchical sequence that is being operated in the previous iteration step of the current multi-level serial gating process. The i-th level in the new round refers to the logic control unit that is currently receiving the first conduction command, that is, the next level after the i-th level logic control unit in the previous round, which is the (i+1)-th level logic control unit.

[0105] Optionally, in this embodiment, serial transmission refers to the i-th level logic control unit of the previous round sending a first activation command to the i-th level logic control unit of the new round in a serial manner through an established uplink channel (i.e., a channel connected to the target controller). Serial transmission in this embodiment includes, but is not limited to, implementation through an already activated UART / serial link or a dedicated serial control bus (such as a control protocol based on SPI or UART encapsulation).

[0106] Optionally, in this embodiment, parallel transmission means that the i-th level logic control unit of the previous round simultaneously sends the first turn-on command to the i-th level logic control unit of the new round through multiple parallel signal lines (such as GPIO, address bus, and encoding line).

[0107] For example, after the motherboard CPLD opens the channel to the PCIe switch board CPLD according to the first conduction command sent by the BMC, it simultaneously informs the next-level CPLD of the target module number in some way. This notification method includes, but is not limited to: the motherboard CPLD encoding the target number and sending it to the next-level CPLD via a serial link, or directly using multiple GPIO lines / encoding lines to transmit the selection value in parallel. If a cascaded I2C structure is used, the motherboard CPLD can also act as an I2C bridge, forwarding BMC commands to the next-level CPLD at a specific address.

[0108] Optionally, if the level of the i-th level logic control unit in the previous round is lower than the level of the highest level logic control unit, the first activation command is sent to the i-th level logic control unit in the new round through the highest level logic control unit using serial or parallel transmission. That is, the target controller needs to send multiple first activation commands during the process of establishing communication with the target module.

[0109] In this embodiment, the first activation command can be forwarded by the logic control unit at the next higher level or broadcast directly by the target controller, providing a flexible command propagation path to adapt to different topologies and communication bandwidth requirements.

[0110] In an exemplary embodiment, after receiving the first activation command, the lowest-level logic control unit detects the operating state of the target module. If the target module is in a normal operating state, the lowest-level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module. If the target module is in an abnormal operating state, the lowest-level logic control unit sends a first signal to the target controller, wherein the first signal is used to instruct the target controller to send the first activation command again after a preset time period.

[0111] Optionally, in practical use, the lowest-level logic control unit can detect the working status of the target module after detecting that the channel between the lowest-level logic control unit and the logic control unit above it is connected.

[0112] Optionally, in this embodiment, the normal state refers to the target module being powered on, firmware startup completed, UART interface initialized, and able to respond to communication requests (such as returning a handshake signal, or a stable idle level). An abnormal state refers to the target module not being powered on, power supply malfunction, firmware not loaded, UART pins floating, no communication response, or abnormal signal levels (such as a continuous low level or high-impedance drift).

[0113] Optionally, the detection basis for the working state of the target module in this embodiment includes, but is not limited to: level detection (detecting whether the UART RX pin maintains the level indicating an idle state); response detection (whether the expected response is received after sending a probe character); status register reading (if the target module has a management register, its "ready" bit can be read by the CPLD to determine whether it can work normally); timing detection (if there is no data transmission within a specified time, it is considered as no response, unable to work normally, and in an abnormal state).

[0114] Optionally, in this embodiment, the port of the target processor refers to the original UART output pin inside the target module used for debugging or communication, such as the debug serial port of an FPGA; the external communication port of the target module refers to the physical output interface provided by the logic control unit of the target module and connected to the upper-level logic control unit.

[0115] Optionally, in this embodiment, the first signal is a feedback signal actively sent by the lowest-level logic control unit to the target controller when it detects that the target module is in an abnormal state. This signal is used to notify the target controller that communication with the target module cannot be established due to a problem with the target module itself, and it is not recommended to retry immediately.

[0116] Optionally, when the target module is in a normal operating state, under the instruction of the lowest-level logic control unit, the UART pins (TX / RX) of the target module's local processor (such as an MCU, monitoring chip, or coprocessor), which were originally in an isolated or floating state, are physically connected to the target module's own external communication port (such as a serial bus interface connected to the next-level logic control unit). This ensures that subsequent internal operation and maintenance data of the target module (such as temperature, fan speed, and port status) can be transmitted externally through this serial port channel.

[0117] It should be noted that the step of connecting the port of the target processor included in the target module of this embodiment with the external communication port of the target module can also be implemented when preparing communication resources.

[0118] In this embodiment, the lowest level logic control unit has the ability to detect the working status of the target module, ensuring that communication with the target controller is established only when the target module is normal, thus avoiding invalid connections and misoperations to faulty modules.

[0119] In an exemplary embodiment, when the target module is in a normal operating state, after the lowest-level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module, the method further includes at least one of the following: the target controller receives target data sent by the target module; the target controller sends a fifth instruction to the target module, wherein the fifth instruction is used to instruct the target module to configure the parameters of the target module.

[0120] Optionally, the target data in this embodiment refers to the original data stream that is actively sent by the target module through the interface, forwarded by multiple logic control units, and finally arrives at the target controller. This includes, but is not limited to, the target module's startup log, system operating status (such as temperature, power consumption, and error codes), debugging information, firmware version number, and serial number.

[0121] Optionally, in this embodiment, the fifth instruction is a control command sent by the target controller to the target module through the established target link, used to configure the internal parameters of the target module.

[0122] Optionally, the fifth instruction in this embodiment includes, but is not limited to, instructions for instructing access to the debug interface (such as switching the debug UART channel, enabling / disabling I2C / SPI access rights), modifying the configuration parameters of the target module (such as adjusting the power management strategy, power consumption mode, clock parameters, etc.), remotely restarting the module, resetting, enabling / disabling certain sensors or functional modules, and instructing for module upgrades.

[0123] In an exemplary embodiment, before determining the N channels included on the target link, the method further includes: determining whether the target object sending the first instruction has permission to access the target module; determining the N channels included on the target link includes: if it is determined that the target object has permission to access the target module, determining the N channels included on the target link.

[0124] Optionally, in this embodiment, the target object is the entity that initiates the first instruction, i.e., the user or system process requesting access to the target module. The target object includes, but is not limited to, operations and maintenance engineers who log in via SSH, a web interface, or a client; and automated operations and maintenance platforms. The target object is an entity with an identity identifier.

[0125] Optionally, the access permission to the target module in this embodiment refers to whether the target object is authorized by the system to establish communication with the target module through the target link. In actual use, the target controller can restrict access to the serial port of certain sensitive modules to only authorized objects, and arbitrate when multiple objects attempt to operate (for example, restricting only one corresponding object to occupy the serial port channel at the same time to communicate with the target module, avoiding conflicts caused by multiple objects switching to communicate with the target module at the same time).

[0126] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0127] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory (ROM) / random access memory (RAM), magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0129] The above method is described below through a specific embodiment. In a scenario of remotely debugging the OAM acceleration module in an AI training server cluster, maintenance personnel need to establish a serial communication link with the OAM 3 located on the PCIe expansion backplane remotely through the BMC unified management platform to obtain its startup logs and perform fault diagnosis. The server includes a three-tier architecture consisting of a motherboard, multiple switch boards, and multiple OAM modules. The motherboard CPLD on the motherboard can connect to multiple switch board CPLDs, and each switch board CPLD can connect to its corresponding multiple OAM modules. The internal structure of the motherboard is as follows... Figure 6 As shown, each OAM has a debug UART interface for outputting the operation logs of the AI ​​chip within the module. In the initial state, the motherboard CPLD is in an unselected state by default, maintaining only the connection with the BMC UART but not connecting to any downstream devices; the serial port switches of the switch board CPLD and each OAM CPLD are all off. Figure 7This is a flowchart illustrating a method for establishing communication with a target module according to an embodiment of this application. The BMC on the server motherboard is used to perform the following steps:

[0130] In step S702, the target controller receives a first instruction, which includes, but is not limited to, an instruction sent by the operation and maintenance personnel to the BMC (i.e., the aforementioned target controller) after clicking a button on the remote web management interface of the operation and maintenance management platform. The first instruction is used to instruct the establishment of communication between the BMC and OAM 2 (i.e., the aforementioned target module).

[0131] In step S704, the target controller determines whether the target object that sent the first instruction has permission to access the target module. If the target controller determines that the target object has permission to access the target module, it executes step S706. If the target controller determines that the target object does not have permission to access the target module, it executes step S708.

[0132] Step S706: Determine the N channels included in the target link, where the target link is used to connect the target controller and the target module, and N is an integer greater than 1. The target link corresponding to OAM 2 is the BMC connecting to the motherboard CPLD. The motherboard CPLD is connected to the PCIe switch board CPLD through channel 2. Then the PCIe switch board CPLD is connected to the CPLD of OAM 2 through channel 4. Thus, the target link is determined to consist of N=2 channels, where each channel is connected to the logic control unit of the adjacent level.

[0133] Step S708: Send a rejection request to the target object (i.e., send a rejection request to the above-mentioned operation and maintenance management platform), wherein the rejection request includes, but is not limited to, a rejection reason;

[0134] In step S710, the target controller determines whether other communications have been established previously. If the target controller determines that other communications have been established previously, it executes step S712, and then executes step S714. If the target controller determines that other communications have been disconnected, it executes step S714. Other communications refer to the communication established between the BMC and the first module other than OAM 2 (such as OAM 1). The target controller and the first module are connected through the first link, which includes a channel located on the target link.

[0135] Step S712: According to the hierarchy of each logical control unit in the multiple logical control units (i.e., CPLDs) required to establish other communications, a disconnect command is issued to each logical control unit to instruct each logical control unit to disconnect the channel used to connect each logical control unit with the next level logical control unit.

[0136] Step S714: Send a third instruction to each logic control unit in the multi-level logic control unit included in the N channels to instruct each logic control unit to configure its own communication resources, wherein the communication resources are the resources required by each logic control unit to connect the channels included in the N channels to connect each logic control unit with the next level logic control unit.

[0137] In step S716, the target controller sends a first conduction command to the first-level logic control unit (i.e., the BMC sends a first conduction command to the motherboard CPLD to instruct the motherboard CPLD to conduct channel 2 used to connect the motherboard CPLD and the PCIe switchboard CPLD). The first-level logic control unit is the logic control unit of the highest level mentioned above, which is the motherboard CPLD included in the motherboard and is the logic control unit of the BMC. The first conduction command is used to instruct each logic control unit to conduct the channel included in the N channels used to connect each logic control unit with the next level logic control unit to establish communication between the target controller and the target module. At this time, i=1.

[0138] In step S718, the target controller sends a first conduction command to the second-level logic control unit (i.e., sends a first conduction command to the PCIe switchboard CPLD to instruct the PCIe switchboard CPLD to conduct channel 4 for connecting the PCIe switchboard CPLD and the CPLD of OAM 2), where the second-level logic control unit is the switchboard CPLD included in the switchboard, and i=2 at this time;

[0139] Step S720: When the third-level logic control unit is the lowest-level logic control unit, after the lowest-level logic control unit detects that the channel between the lowest-level logic control unit and the previous-level logic control unit is connected, the lowest-level logic control unit detects the working state of the target module and determines whether the working state of the target module is normal.

[0140] Step S722: When the target module is in a normal working state, the lowest level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module.

[0141] Step S724: When the working state of the target module is abnormal, the lowest level logic control unit sends a first signal to the target controller, wherein the first signal is used to instruct the target controller to send the first conduction command again after a preset time period.

[0142] Step S726: The target controller determines whether each of the N channels is successfully turned on. If the target controller determines that each of the N channels is successfully turned on, it executes step S728. If the target controller determines that the N channels include channels that are not successfully turned on, it executes step S708. The methods for determining whether a channel is successfully turned on include, but are not limited to: determining by monitoring the target signal, or determining by reading the value in the target register corresponding to each logic control unit.

[0143] Step S728: Confirm that communication between the target controller and the target module has been successfully established.

[0144] It should be noted that, since the BMC in this embodiment only supports opening one independent session, after receiving the first instruction, the target controller needs to execute step S710 to determine whether other communications have been established previously. If so, the previous link needs to be disconnected before enabling the connection of N channels to avoid resource conflicts. In actual use, if the BMC has spare UART resources, it can support opening a second independent session. After receiving the first instruction, if it is determined that only one unrelated link is currently connected, there is no need to disconnect this unrelated link, and the connection of N channels can be directly enabled.

[0145] In the above embodiments, upon receiving the first instruction, the target controller first determines whether the target object sending the first instruction has the corresponding permissions. Only after the permissions are verified is communication between the target controller and the target module dynamically established. Then, it determines whether communication between the target controller and other modules has been established previously. If so, the previous link needs to be disconnected before the current connection of N channels is initiated to avoid resource conflicts. By determining the N channels included in the target link and clarifying which levels of logic control units each channel connects to, the entire target link is subdivided into multiple independently controllable channels. Each level of logic control unit only controls the connection of the channel used to connect with the logic control unit at the adjacent level. Then, connection instructions are issued according to the hierarchy of the logic control units, ensuring that the connection of the target link is top-down, step-by-step, and orderly. Each level of logic control unit can quickly switch to the channel corresponding to the target module according to actual needs, thereby achieving the purpose of establishing communication with the target controller. This solves the technical problem of difficulty in effectively establishing communication between the controller and modules in multi-module architectures in related technologies, achieving the technical effect of flexible channel connection and effective establishment of communication between the controller and modules.

[0146] According to another aspect of the embodiments of this application, a communication establishment apparatus is also provided. This apparatus can be used to implement the communication establishment method provided in the above embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0147] Figure 8 This is a structural block diagram of a communication establishment apparatus according to an embodiment of this application, such as... Figure 8 As shown, the device includes:

[0148] The determination module 82 is used to determine N channels included in the target link upon receiving the first instruction. The target link is used to connect the target controller and the target module. The first instruction is used to instruct the establishment of communication between the target controller and the target module. Each of the N channels is used to connect the logic control units of adjacent levels included in the multi-level logic control unit. The logic control unit of the highest level included in the multi-level logic control unit is the logic control unit of the target controller. The logic control unit of the lowest level included in the multi-level logic control unit is the logic control unit of the target module. N is an integer greater than 1.

[0149] The sending module 84 is used to send a first activation command to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit. The first activation command is used to instruct each logic control unit to activate the channel included in N channels for connecting each logic control unit with the next level logic control unit, so as to establish communication between the target controller and the target module.

[0150] It should be noted that the determining module 82 in this embodiment can be used to execute the above-described step S202, and the sending module 84 in this embodiment can be used to execute the above-described step S204. For a description of the features corresponding to the communication establishment device in the embodiment, please refer to the relevant descriptions of the communication establishment method in the embodiment, which will not be repeated here.

[0151] Through the embodiments provided in this application, after receiving the first instruction, the target link is subdivided into multiple independently controllable channels by determining the N channels included on the target link and identifying which levels of logic control units in the multi-level logic control units each channel connects to. Each level of logic control unit only controls the conduction of the channel used to connect with the logic control unit at the adjacent level. Then, conduction instructions are issued according to the hierarchy of the logic control units, ensuring that the conduction of the target link is top-down, step-by-step, and orderly. Each level of logic control unit can quickly switch to the channel corresponding to the target module according to actual needs, thereby achieving the purpose of establishing communication with the target controller. The target controller can access the module through the highest-level logic control unit. For the target controller, this means accessing all modules through a single entry point. Furthermore, establishing communication between the target controller and the target module is fully automatic and requires no manual intervention. This solves the technical problem of effectively establishing communication between the controller and modules in multi-module architectures in related technologies, achieving the technical effect of flexible channel conduction and effective establishment of communication between the controller and modules.

[0152] In an exemplary embodiment, the sending module 84 is further configured to, after sending a first conduction instruction to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit, receive a second instruction; and, if it is determined based on the second instruction that the target link needs to be disconnected, send a disconnection instruction to each logic control unit according to the hierarchy of each logic control unit to instruct each logic control unit to disconnect the channel included in the N channels for connecting each logic control unit with the next level logic control unit, wherein the second instruction is used to instruct at least one of the following: establishing communication between the target controller and a first module other than the target module, wherein the target controller and the first module are connected through a first link, the first link including a channel partially located on the target link; and disconnecting communication between the target controller and the target module.

[0153] In an exemplary embodiment, the above-mentioned sending module 84 is further configured to implement the operation of sending a first conduction instruction to each logic control unit in accordance with the hierarchy of each logic control unit included in the multi-level logic control unit in at least one of the following ways: sending the first conduction instruction to each logic control unit in descending order of the hierarchy of each logic control unit included in the multi-level logic control unit; sending the first conduction instruction to each logic control unit in descending order according to a preset time interval.

[0154] In an exemplary embodiment, the aforementioned sending module 84 is further configured to repeatedly perform the following operations in descending order of the hierarchy of each logic control unit until the (i+1)th level logic control unit is the lowest level logic control unit, where i is an integer greater than 0 and i is less than or equal to N: sending a first conduction command to the i-th level logic control unit; and, if it is determined that the i-th level logic control unit has successfully conducted the channel for connecting the i-th level logic control unit and the (i+1)th level logic control unit, determining the (i+1)th level logic control unit as the i-th level logic control unit for the new round.

[0155] In an exemplary embodiment, the sending module 84 is further configured to, after sending the first conduction command to the i-th level logic control unit, determine, if a target signal is detected, that the i-th level logic control unit has not successfully conducted the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit, wherein the target signal is a signal fed back by the i-th level logic control unit when the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit has not been conducted; and determine, if no target signal is detected, that the i-th level logic control unit has successfully conducted the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit.

[0156] In an exemplary embodiment, the sending module 84 is further configured to, after sending the first conduction command to the i-th level logic control unit, read a first value stored in the target register, wherein the first value is a value filled into the target register by the i-th level logic control unit to indicate the actual conduction state of the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit; if it is determined that the first value is not completely consistent with the target value, it is determined that the i-th level logic control unit has not successfully conducted the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit, wherein the target value is a pre-configured value used to indicate that the channel is in a conduction state; if it is determined that the first value is completely consistent with the target value, it is determined that the i-th level logic control unit has successfully conducted the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit.

[0157] In an exemplary embodiment, the aforementioned sending module 84 is further configured to send a third instruction to each logical control unit before sending a first activation instruction to each logical control unit according to the hierarchy of each logical control unit included in the multi-level logical control unit, to instruct each logical control unit to configure its own communication resources, wherein the communication resources are the resources required by each logical control unit when activating the channels included in the N channels for connecting each logical control unit with the next level logical control unit.

[0158] In an exemplary embodiment, the above-described apparatus is further configured to send a second activation instruction to the highest-level logic control unit upon receiving a fourth instruction. The second activation instruction instructs the highest-level logic control unit to maintain only the activation of the second link. The second link sequentially connects the target controller, the highest-level logic control unit, and the hardware module. The fourth instruction instructs the hardware module to be controlled. The target controller, the highest-level logic control unit, and the hardware module are all located on the same motherboard. The second activation instruction instructs the highest-level logic control unit to perform at least one of the following operations: if communication between the target controller and the second module is established, disconnecting the third link between the target controller and the second module and then activating the second link; if communication between the target controller and the second module is not established, directly activating the second link.

[0159] In an exemplary embodiment, the sending module 84 is further configured to perform at least one of the following steps after determining the (i+1)th level logic control unit as the i-th level logic control unit of the new round: forwarding the first turn-on instruction to the i-th level logic control unit of the new round through the i-th level logic control unit in the previous round in a serial or parallel manner; if the level of the i-th level logic control unit in the previous round is lower than the level of the highest level logic control unit, sending the first turn-on instruction to the i-th level logic control unit of the new round through the highest level logic control unit in a serial or parallel manner.

[0160] In an exemplary embodiment, the above-described apparatus is further configured such that, after receiving the first conduction command, the lowest-level logic control unit detects the operating state of the target module; if the operating state of the target module is normal, the lowest-level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module; if the operating state of the target module is abnormal, the lowest-level logic control unit sends a first signal to the target controller, wherein the first signal is used to instruct the target controller to send the first conduction command again after a preset time period.

[0161] In an exemplary embodiment, the above-described apparatus is further configured to, when the target module is in a normal operating state, after the lowest-level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module, execute at least one of the following methods: the target controller receives target data sent by the target module; the target controller sends a fifth instruction to the target module, wherein the fifth instruction is used to instruct the target module to configure the parameters of the target module.

[0162] In an exemplary embodiment, the determining module 82 is further configured to determine whether the target object sending the first instruction has permission to access the target module before determining the N channels included on the target link; determining the N channels included on the target link includes: determining the N channels included on the target link if it is determined that the target object has permission to access the target module.

[0163] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0164] According to another aspect of the embodiments of this application, a task execution system is provided, the system comprising: a target controller, a target module, and a multi-level logic control unit, wherein the target controller and the target module are connected via a target link, the target link comprising N channels, each of the N channels being used to connect adjacent levels of logic control units included in the multi-level logic control unit, the highest level logic control unit included in the multi-level logic control unit being the logic control unit of the target controller, and the lowest level logic control unit included in the multi-level logic control unit being the logic control unit of the target module, where N is an integer greater than 1, the target controller being configured to perform the following operations: upon receiving a first instruction, determining the N channels included in the target link; and issuing a first conduction instruction to each logic control unit according to the level of each logic control unit included in the multi-level logic control unit, wherein the first conduction instruction is used to instruct each logic control unit to conduct the channel included in the N channels for connecting each logic control unit with the next level logic control unit, thereby establishing communication between the target controller and the target module.

[0165] It should be noted that in actual use, the task execution system described above can include one or more target controllers. The multi-level logic control units connected to different target controllers may be the same or different, and the target modules connected to different target controllers may be the same or different. For example, when the system includes multiple servers, each server internally employs... Figure 3 The structure shown in the figure includes multiple target controllers. After receiving an external instruction (i.e., the first instruction mentioned above), the system first determines which internal server the instruction corresponds to, and then transmits the instruction to the target controller included in the corresponding server to establish communication between the target controller and the target module.

[0166] According to another aspect of the embodiments of this application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor is configured to perform the steps of any of the communication establishment method embodiments described above via the computer program. In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0167] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the communication establishment method embodiments described above when running.

[0168] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, ROMs, RAMs, portable hard drives, magnetic disks, or optical disks.

[0169] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the communication establishment method embodiments described above.

[0170] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the communication establishment method embodiments described above.

[0171] According to another aspect of the embodiments of this application, a computer program product is also provided, which includes a computer program / instructions containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit, it performs various functions provided in the embodiments of this application. The sequence numbers of the embodiments of this application above are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0172] Figure 9 This is a computer system architecture block diagram of an electronic device according to an embodiment of this application. For example... Figure 9 As shown, the computer system includes a CPU (corresponding to...) Figure 9 The central processing unit (CPU) 901, which can be based on the data stored in ROM (corresponding to...) Figure 9 The program is stored in the read-only memory 902 or loaded from the storage section 908 into the RAM (corresponding to the read-only memory 902). Figure 9The system executes various appropriate actions and processes by storing programs in the random access memory (RAM) 903. The RAM 903 also stores various programs and data required for system operation. The central processing unit 901, the read-only memory 902, and the RAM 903 are interconnected via a bus 904. The I / O interface 905 is also connected to the bus 904.

[0173] The following components are connected to the I / O interface (corresponding to...) Figure 9 The input / output interface 905 includes an input section 906 such as a keyboard and mouse; an output section 907 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 908 including a hard disk; and a communication section 909 including network interface cards such as LAN cards and modems. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the input / output interface 905 as needed. A removable medium 911, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 910 as needed so that computer programs read from it can be installed into the storage section 908 as needed.

[0174] Specifically, according to embodiments of this application, the processes described in the various method flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 909, and / or installed from removable medium 911. When the computer program is executed by central processing unit 901, it performs various functions defined in the system of this application.

[0175] It should be noted that, Figure 9 The computer system of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0176] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, CPUs, FPGAs, Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), System-on-Chips (SoCs), CPLDs, MCUs, etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, application program, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0177] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0178] The foregoing has provided a detailed description of a communication establishment method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for establishing communication, characterized in that, Executed by the target controller, including: Upon receiving a first instruction, N channels are determined on the target link, wherein the target link is used to connect the target controller and the target module, the first instruction is used to instruct the establishment of communication between the target controller and the target module, each of the N channels is used to connect adjacent levels of logic control units in the multi-level logic control unit, the highest level logic control unit in the multi-level logic control unit is the logic control unit of the target controller, the lowest level logic control unit in the multi-level logic control unit is the logic control unit of the target module, and N is an integer greater than 1; According to the hierarchy of each logic control unit included in the multi-level logic control unit, a first activation command is issued to each logic control unit, wherein the first activation command is used to instruct each logic control unit to activate the channel included in the N channels for connecting each logic control unit with the next level logic control unit, so as to establish communication between the target controller and the target module.

2. The method according to claim 1, characterized in that, After issuing a first activation command to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit, the method further includes: Receive the second instruction; If it is determined based on the second instruction that the target link needs to be disconnected, a disconnection instruction is issued to each logical control unit according to the hierarchy of each logical control unit, so as to instruct each logical control unit to disconnect the channel included in the N channels for connecting each logical control unit with the next level logical control unit.

3. The method according to claim 2, characterized in that, The second instruction is used to indicate at least one of the following: Establish communication between the target controller and a first module other than the target module, wherein the target controller and the first module are connected via a first link, and the first link includes a channel located on the target link; Disconnect the communication between the target controller and the target module.

4. The method according to claim 1, characterized in that, According to the hierarchy of each logic control unit included in the multi-level logic control unit, a first activation command is issued to each logic control unit, including at least one of the following: The first activation command is issued to each logic control unit in descending order of hierarchy within the multi-level logic control unit. The first activation command is sent to each logic control unit in turn according to a preset time interval.

5. The method according to claim 4, characterized in that, The first activation command is issued to each logic control unit in descending order of hierarchy within the multi-level logic control unit, including: According to the order of the hierarchy of each logic control unit from largest to smallest, repeat the following operations until the (i+1)th level logic control unit is the logic control unit of the smallest level, where i is an integer greater than 0 and i is less than or equal to N: send the first conduction command to the i-th level logic control unit; if it is determined that the i-th level logic control unit has successfully conducted the channel for connecting the i-th level logic control unit and the (i+1)th level logic control unit, determine the (i+1)th level logic control unit as the i-th level logic control unit of the new round.

6. The method according to claim 5, characterized in that, After sending the first turn-on command to the i-th level logic control unit, the method further includes: If a target signal is detected, it is determined that the i-th level logic control unit has failed to successfully open the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit. The target signal is the signal fed back by the i-th level logic control unit when it has failed to open the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit. If the target signal is not detected, it is determined that the i-th level logic control unit has successfully opened the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit.

7. The method according to claim 5, characterized in that, After sending the first turn-on command to the i-th level logic control unit, the method further includes: Read the first value stored in the target register, wherein the first value is a value filled into the target register by the i-th level logic control unit to indicate the actual conduction state of the channel connecting the i-th level logic control unit and the (i+1)-th level logic control unit; If it is determined that the first value is not completely consistent with the target value, it is determined that the i-th level logic control unit has not successfully connected the channel used to connect the i-th level logic control unit and the i+1-th level logic control unit, wherein the target value is a pre-configured value used to indicate that the channel is in a connected state; If the first value is completely consistent with the target value, it is determined that the i-th level logic control unit has successfully opened the channel for connecting the i-th level logic control unit and the (i+1)-th level logic control unit.

8. The method according to claim 1, characterized in that, Before issuing a first activation command to each logic control unit according to the hierarchy of each logic control unit included in the multi-level logic control unit, the method further includes: A third instruction is sent to each of the logic control units to instruct each logic control unit to configure its own communication resources, wherein the communication resources are the resources required by each logic control unit to connect the channels included in the N channels to the next level logic control unit.

9. The method according to claim 1, characterized in that, The method further includes: Upon receiving the fourth instruction, a second conduction instruction is sent to the highest-level logic control unit. The second conduction instruction is used to instruct the highest-level logic control unit to maintain only the conduction of the second link. The second link is used to sequentially connect the target controller, the highest-level logic control unit, and the hardware module. The fourth instruction is used to instruct the hardware module to be controlled. The target controller, the highest-level logic control unit, and the hardware module are all located on the same motherboard.

10. The method according to claim 9, characterized in that, The second activation command is used to instruct the logic control unit of the highest level to perform at least one of the following operations: If it is determined that communication is currently established between the target controller and the second module, the third link between the target controller and the second module is disconnected, and then the second link is connected. If it is determined that communication between the target controller and the second module is not currently established, the second link is directly connected.

11. The method according to claim 5, characterized in that, After determining the (i+1)th level logic control unit as the i-th level logic control unit for the new round, the method further includes at least one of the following: The first turn-on command is forwarded to the i-th level logic control unit of the new round by means of serial or parallel transmission from the i-th level logic control unit in the previous round. If the level of the i-th level logic control unit in the previous round is lower than the level of the maximum level logic control unit, the first turn-on command is sent to the i-th level logic control unit in the new round through the maximum level logic control unit using serial or parallel transmission.

12. The method according to claim 1, characterized in that, After receiving the first activation command, the lowest-level logic control unit detects the working status of the target module. When the target module is in a normal working state, the lowest level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module. When the target module is in an abnormal operating state, the lowest level logic control unit sends a first signal to the target controller, wherein the first signal is used to instruct the target controller to send the first turn-on command again after a preset time period.

13. The method according to claim 12, characterized in that, When the target module is in a normal operating state, after the lowest-level logic control unit instructs the port of the target processor included in the target module to connect with the external communication port of the target module, the method further includes at least one of the following: The target controller receives the target data sent by the target module; The target controller sends a fifth instruction to the target module, wherein the fifth instruction is used to instruct the target module to configure the parameters of the target module.

14. The method according to claim 1, characterized in that, Before determining the N channels included on the target link, the method further includes: Determine whether the target object sending the first instruction has permission to access the target module; Determining the N channels included on the target link includes: determining the N channels included on the target link when it is determined that the target object has the permission to access the target module.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the communication establishment method as described in any one of claims 1 to 14 when executing the computer program.

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