Gate driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. Each gate driving module comprises: a signal generation unit configured to generate a stage transmission signal corresponding to a current stage and an initial gate driving signal in response to a stage transmission signal output by a previous-stage gate driving module; and an overdrive compensation unit configured to output the initial gate driving signal to the scan line in a normal driving mode, and to generate a target gate driving signal by segment voltage modulation on the initial gate driving signal and output the target gate driving signal to the scan line in an overdrive compensation mode. The application improves the driving capability of the gate driving circuit under extreme temperature conditions by segment voltage modulation on the gate driving signal by the overdrive compensation unit, and ensures the driving reliability and display quality of the display panel under harsh environments.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] Display panels typically employ Gate Driver on Array (GOA) technology, integrating the gate driving circuitry onto the array substrate to reduce costs and achieve narrow bezels. In extreme environments such as high or low temperatures, the carrier mobility of thin-film transistors (TFTs) undergoes significant changes, leading to waveform distortion when the clock signal is transmitted to the gate output. This results in insufficient charging capability of the gate turn-on voltage, consequently affecting pixel charging rate and display quality.

[0003] Therefore, improving the driving capability of the gate drive circuit under extreme temperatures is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel. By using an overdrive compensation unit to modulate the segmented voltage of the gate driving signal, this application improves the driving capability of the gate driving circuit under extreme temperature conditions, ensuring the driving reliability and display quality of the display panel in harsh environments.

[0005] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules. Each gate driving module includes: a signal generation unit configured to: generate a cascade signal corresponding to the current stage and an initial gate driving signal in response to a cascade signal output by a previous gate driving module; and an overdrive compensation unit connected to the drive output terminal of the signal generation unit and a scan line, configured to: output the initial gate driving signal to the scan line in normal driving mode; and perform segmented voltage modulation on the initial gate driving signal in overdrive compensation mode to generate a target gate driving signal, and output the target gate driving signal to the scan line; wherein the target gate driving signal includes at least two high-voltage segments with different voltage values ​​within one pulse period.

[0006] Optionally, the target gate drive signal includes, within one pulse cycle: a first overdrive voltage segment at the rising edge, a first sustaining voltage segment after the first overdrive voltage segment, a second overdrive voltage segment at the falling edge, and a second sustaining voltage segment after the second overdrive voltage segment; wherein, the voltage value of the first overdrive voltage segment is greater than the voltage value of the first sustaining voltage segment, the voltage value of the second overdrive voltage segment is less than the voltage value of the second sustaining voltage segment, and the voltage values ​​of the first sustaining voltage segment and the second sustaining voltage segment are respectively matched with the voltage value of the initial gate drive signal; the first overdrive voltage segment and the first sustaining voltage segment serve as the two high-voltage segments.

[0007] Optionally, the overdrive compensation unit includes: a first pre-charge unit, connected to a pre-charge enable terminal, a first overdrive voltage terminal, and a first pre-charge node, configured to: charge the first pre-charge node according to a first overdrive voltage output from the first overdrive voltage terminal in response to a pre-charge enable signal output from the pre-charge enable terminal; and a second pre-charge unit, connected to the pre-charge enable terminal, a second overdrive voltage terminal, and a second pre-charge node, configured to: charge the second pre-charge node according to a second overdrive voltage output from the second overdrive voltage terminal in response to a pre-charge enable signal output from the pre-charge enable terminal; isolation. The control unit, connected to the drive output terminal of the signal generation unit and the scan line respectively, is configured to: in normal driving mode, conduct the electrical connection between the drive output terminal of the signal generation unit and the scan line; in overdrive compensation mode, disconnect the electrical connection between the signal generation unit and the scan line; the overdrive coupling unit, connected to the first precharge node, the second precharge node and the scan line respectively, is configured to: in overdrive compensation mode, time-division coupling the first overdrive voltage on the first precharge node and the second overdrive voltage on the second precharge node to the scan line.

[0008] Optionally, the first pre-charge unit includes: a first transistor, the control terminal of the first transistor being connected to the pre-charge enable terminal, the first terminal of the first transistor being connected to the first overdrive voltage terminal, and the second terminal of the first transistor being connected to the first pre-charge node; and a first pre-storage capacitor, the first terminal of the first pre-storage capacitor being connected to the first pre-charge node, and the second terminal of the first pre-storage capacitor being grounded.

[0009] Optionally, the second pre-charge unit includes: a second transistor, the control terminal of which is connected to the pre-charge enable terminal, the first terminal of which is connected to the second overdrive voltage terminal, and the second terminal of which is connected to the second pre-charge node; and a second pre-storage capacitor, the first terminal of which is connected to the second pre-charge node, and the second terminal of which is grounded.

[0010] Optionally, the isolation control unit includes: a third transistor, the control terminal of which is connected to a first overdrive clock signal terminal, and the first terminal of which is connected to a power supply terminal; a fourth transistor, the control terminal of which is connected to a second overdrive clock signal terminal, the first terminal of which is connected to the power supply terminal, and the second terminal of which is connected to the second terminal of the third transistor; and a fifth transistor, the control terminal of which is connected to the second terminal of the fourth transistor, the first terminal of which is connected to the drive output terminal of the signal generation unit, and the second terminal of which serves as the output terminal of the isolation control unit.

[0011] Optionally, the rising edge of the first overdrive clock signal corresponds to the rising edge of the reference clock signal corresponding to the current stage gate drive module; the rising edge of the second overdrive clock signal corresponds to the falling edge of the reference clock signal; and the high-level width of the first overdrive clock signal and the second overdrive clock signal is smaller than the high-level width of the reference clock signal.

[0012] Optionally, the overdrive coupling unit includes: a sixth transistor, the control terminal of which is connected to the first overdrive clock signal terminal, the first terminal of which is connected to the first precharge node, and the second terminal of which is connected to the scan line; and a seventh transistor, the control terminal of which is connected to the second overdrive clock signal terminal, the first terminal of which is connected to the second precharge node, and the second terminal of which is connected to the scan line.

[0013] Optionally, the third transistor has the opposite conduction type to the sixth transistor, and the fourth transistor has the opposite conduction type to the seventh transistor.

[0014] Secondly, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines. The non-display area includes a gate driving circuit, wherein the drive output terminal of the signal generation unit and the output terminal of the overdrive compensation unit in the same gate driving module are electrically connected to the same scan line.

[0015] The technical solutions provided in this application have at least the following beneficial effects:

[0016] This application incorporates an overdrive compensation unit in each gate drive module and performs segmented voltage modulation on the initial gate drive signal output by the signal generation unit in overdrive compensation mode. This ensures that the generated target gate drive signal includes at least two high-voltage segments with different voltage values ​​within one pulse cycle. The first overdrive voltage segment, located at the rising edge, provides a transient high voltage higher than the standard sustaining voltage at the moment the gate is turned on, thereby forcing rapid charging of the gate capacitor in harsh environments such as low temperatures, effectively overcoming the problem of insufficient charging caused by the decrease in thin-film transistor mobility. Simultaneously, the subsequent first sustaining voltage segment maintains the gate-on state with a standard high voltage, avoiding bias temperature stress degradation of the thin-film transistor caused by prolonged application of high voltage. Therefore, this application improves the driving capability of the gate drive circuit under extreme temperature conditions, ensuring the driving reliability and display quality of the display panel in harsh environments. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 The diagram shown is a structural schematic of a gate driving module provided in an embodiment of this application.

[0019] Figure 2 The diagram shown is a schematic diagram of a signal generation unit provided in an embodiment of this application.

[0020] Figure 3 The figure shown is a waveform diagram of a gate drive signal provided in an embodiment of this application.

[0021] Figure 4 The diagram shown is a circuit schematic of a gate driving module provided in an embodiment of this application.

[0022] Figure 5 The figure shown is a waveform diagram of a precharge enable signal provided in an embodiment of this application.

[0023] Figure 6 The diagram shown is a driving timing diagram in a normal driving mode provided by an embodiment of this application.

[0024] Figure 7 The diagram shown is a driving timing diagram under an overdrive compensation mode provided in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures: 100. Gate driving module; 110. Signal generation unit; 120. Overdrive compensation unit; 121. First precharge unit; 122. Second precharge unit; 123. Isolation control unit; 124. Overdrive coupling unit; 200. Scan line; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; C1, first pre-storage capacitor; C2, second pre-storage capacitor; A1, First precharge node; A2, Second precharge node; EN, Precharge enable terminal; VGH1, First overdrive voltage terminal; VGL1, Second overdrive voltage terminal; CLK_T1A, First overdrive clock signal terminal; CLK_T2A, Second overdrive clock signal terminal; VDD, Power supply terminal; G1, Drive output terminal of signal generation unit; G2, Output terminal of overdrive compensation unit. Detailed Implementation

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0027] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0028] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0029] This application provides a gate driving circuit, specifically including the following embodiments: Figure 1 The diagram shown is a schematic representation of a gate driving circuit according to an embodiment of this application; the gate driving circuit of this embodiment includes N cascaded gate driving modules 100; as shown... Figure 1As shown, each gate drive module 100 includes at least a signal generation unit 110 and an overdrive compensation unit 120.

[0030] In this embodiment, the signal generation unit 110 is configured to generate a stage transmission signal and an initial gate drive signal corresponding to the current stage in response to the stage transmission signal output by the previous stage gate drive module 100.

[0031] It should be noted that the input terminal of the signal generation unit 110 in this embodiment receives the stage transmission signal output by the front-stage gate driving module 100 and generates the stage transmission signal and the initial gate driving signal corresponding to the current stage. The stage transmission signal corresponding to the current stage is used to transmit the signal to the rear-stage gate driving module 100, and the initial gate driving signal is used to drive the scan line 200 of the current row. The signal generation unit 110 includes a stage transmission output terminal for outputting the stage transmission signal and a drive output terminal for outputting the initial gate driving signal.

[0032] like Figure 2 As shown, the signal generation unit 110 may include a pull-up subunit, a pull-down subunit, an output subunit, a reset subunit, and a noise reduction subunit. The pull-up and pull-down subunits generate a Q-point voltage. These subunits need to request multiple stage transmission signals from the upper and lower gate drive modules. The Q-point voltage is the turn-on voltage of the output subunit, enabling it to output a gate drive signal to provide the turn-on voltage for the display area. The reset subunit is used to avoid inter-frame interference, and the noise reduction subunit performs noise reduction processing on signals at various key nodes. Figure 2 In this diagram, Qn represents the drive control node of the nth-stage gate drive module 100, Gn represents the drive output terminal of the nth-stage gate drive module 100, Fn represents the stage transmission output terminal of the nth-stage gate drive module 100, CKn represents the clock signal terminal of the nth-stage gate drive module 100, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the drive output terminal of the (n-3)th-stage gate drive module 100, Fn-3 represents the stage transmission output terminal of the (n-3)th-stage gate drive module 100, and Fn+4 represents the stage transmission output terminal of the (n+4)th-stage gate drive module 100.

[0033] In this embodiment, the overdrive compensation unit 120 is connected to the drive output terminal G1 of the signal generation unit and the scan line 200, and is configured to: output the initial gate drive signal to the scan line 200 in normal drive mode; and perform segmented voltage modulation on the initial gate drive signal in overdrive compensation mode to generate the target gate drive signal, and output the target gate drive signal to the scan line 200.

[0034] It should be noted that in this embodiment, the input terminal of the overdrive compensation unit 120 is connected to the drive output terminal G1 of the signal generation unit, and the output terminal of the overdrive compensation unit 120 is connected to the scan line 200 of the current row. The overdrive compensation unit 120 has two operating modes: normal drive mode and overdrive compensation mode, which are switched by an enable signal from an external temperature sensor or TCON. Specifically: (1) Normal drive mode: When the system detects that the ambient temperature is within the normal range (e.g., -20℃ to +60℃), the enable signal is invalid, and the overdrive compensation unit 120 enters the normal drive mode. At this time, the overdrive compensation unit 120 directly outputs the initial gate drive signal output by the signal generation unit 110 to the scan line 200. At this time, the waveform on the scan line 200 is exactly the same as the initial gate drive signal.

[0035] (2) Overdrive compensation mode: When the system detects that the ambient temperature is too low (e.g., below -30℃) or too high (e.g., above +80℃), the enable signal is valid, and the overdrive compensation unit 120 enters the overdrive compensation mode. At this time, the overdrive compensation unit 120 performs segmented voltage modulation on the received initial gate drive signal to generate a target gate drive signal, and outputs the target gate drive signal to the scan line 200 so that the rising rate of the rising edge of the target gate drive signal is greater than that of the initial gate drive signal.

[0036] like Figure 3 As shown in 3a, the theoretical waveform of the initial gate drive signal in this embodiment is a standard square wave, with a high level of Vgh2 (e.g., +25V) and a low level of Vgl2 (e.g., -8V). However, under extreme environments such as high or low temperatures, the initial gate drive signal output by the signal generation unit 110 has waveform distortion, as shown in the actual waveform in 3a. This will cause insufficient charging of the pixel circuit.

[0037] like Figure 3 As shown in 3b, the target gate drive signal in this embodiment includes four voltage segments sequentially within one pulse cycle, specifically: (1) The first overdrive voltage segment Th1 located on the rising edge: The voltage value of this segment is Vgh1 (e.g. +30V), and the duration is from several hundred nanoseconds to several microseconds.

[0038] (2) The first sustaining voltage segment Th2 is located after the first overdrive voltage segment Th1: the voltage value of this segment is Vgh2 (e.g. +25V), and the duration is the remaining high level period.

[0039] (3) The second overdrive voltage segment Th3 located at the falling edge: the voltage value of this segment is Vgl1 (e.g. -12V), and the duration is from several hundred nanoseconds to several microseconds.

[0040] (4) The second sustaining voltage segment Th4 is located after the second overdrive voltage segment Th3: the voltage value of this segment is Vgl2 (e.g. -8V) and the duration is the remaining low level period.

[0041] Furthermore, the voltage value Vgh1 of the first overdrive voltage segment is greater than the voltage value Vgh2 of the first sustaining voltage segment; the voltage value Vgl1 of the second overdrive voltage segment is less than the voltage value Vgl2 of the second sustaining voltage segment; and the voltage value Vgh2 of the first sustaining voltage segment is the same as the high-level voltage value of the initial gate drive signal, while the voltage value Vgl2 of the second sustaining voltage segment is the same as the low-level voltage value of the initial gate drive signal. The first overdrive voltage segment Th1 and the first sustaining voltage segment Th2 thus constitute two high-voltage segments with different voltage values.

[0042] Therefore, the specific working principle of the gate driving module 100 in this embodiment is as follows: (1) In overdrive compensation mode, after receiving the initial gate drive signal, the overdrive compensation unit 120 first generates an instantaneous high voltage pulse and superimposes it onto the output terminal before its rising edge arrives, so that the voltage on the scan line 200 is quickly pulled up to the first overdrive voltage segment Vgh1. Since this voltage is higher than the standard high level Vgh2, the gate-source voltage of the gate drive transistor in the pixel circuit increases instantaneously, the channel on-resistance decreases sharply, and the pixel capacitor is charged quickly, thereby overcoming the problem of insufficient charging caused by the decrease in TFT mobility at low temperature.

[0043] (2) After a brief overdrive pulse, the overdrive compensation unit 120 reduces the output voltage to the first sustaining voltage segment Vgh2 and maintains it until the end of the scan cycle. This standard high voltage is sufficient to maintain the gate transistor in the on state, while avoiding the TFT from undergoing bias temperature (BT) stress degradation due to prolonged application of high voltage.

[0044] (3) Before the falling edge arrives, the overdrive compensation unit 120 also generates a momentary low voltage pulse Vgl1, which quickly pulls down the voltage of the scan line 200 to below the standard low level Vgl2, quickly removes the charge in the gate capacitor, and accelerates the transistor turn-off; then the voltage rises back to Vgl2 and is maintained until the next cycle.

[0045] In summary, this application, by setting an overdrive compensation unit 120 in each gate drive module 100 and performing segmented voltage modulation on the initial gate drive signal output by the signal generation unit 110 in overdrive compensation mode, ensures that the generated target gate drive signal includes at least two high-voltage segments with different voltage values ​​within one pulse cycle. The first overdrive voltage segment, located at the rising edge, provides a transient high voltage higher than the standard sustaining voltage at the moment the gate is turned on, thereby forcing rapid charging of the gate capacitor in harsh environments such as low temperatures, effectively overcoming the problem of insufficient charging caused by the decrease in thin-film transistor mobility. Simultaneously, the subsequent first sustaining voltage segment maintains the gate-on state with a standard high voltage, avoiding bias temperature stress degradation of the thin-film transistor caused by prolonged application of high voltage. Therefore, this application improves the driving capability of the gate drive circuit under extreme temperature conditions, ensuring the driving reliability and display quality of the display panel in harsh environments.

[0046] In one embodiment, such as Figure 1 As shown, the overdrive compensation unit 120 in this embodiment includes a first pre-charge unit 121, a second pre-charge unit 122, an isolation control unit 123, and an overdrive coupling unit 124. Specifically: (1) First pre-charge unit 121: connected to the pre-charge enable terminal EN, the first overdrive voltage terminal VGH1 and the first pre-charge node A1 respectively. Its function is: when the pre-charge enable signal output by the pre-charge enable terminal EN is in an effective state (e.g., high level), the first pre-charge unit 121 responds to the pre-charge enable signal, obtains the first overdrive voltage from the first overdrive voltage terminal VGH1, and charges the first pre-charge node A1, so that the voltage of the first pre-charge node A1 is raised and stabilized near the first overdrive voltage; wherein, the first overdrive voltage is usually a positive high voltage, used to improve the driving capability when the gate is turned on.

[0047] (2) Second precharge unit 122: It is connected to the same precharge enable terminal EN, the second overdrive voltage terminal VGL1 and the second precharge node A2 respectively. Its function is similar to that of the first precharge unit 121: When the precharge enable signal is valid, the second precharge unit 122 responds to the precharge enable signal, obtains the second overdrive voltage from the second overdrive voltage terminal VGL1, and charges the second precharge node A2, so that the voltage of the second precharge node A2 is pulled down and stabilized near the second overdrive voltage; wherein, the second overdrive voltage is usually a negative low voltage, used to accelerate the gate turn-off.

[0048] (3) Isolation control unit 123: Connected to the drive output terminal G1 of the signal generation unit and the scan line 200 respectively. Its function is to selectively turn on or off the electrical connection between the signal generation unit 110 and the scan line 200 according to the working mode: ① In the normal driving mode, the isolation control unit 123 turns on the electrical connection, so that the initial gate drive signal output by the signal generation unit 110 can be directly transmitted to the scan line 200. ② In the overdrive compensation mode, the isolation control unit 123 disconnects the electrical connection. At this time, the signal generation unit 110 and the scan line 200 are isolated, and the initial gate drive signal output by the signal generation unit 110 no longer directly drives the scan line 200, thereby providing conditions for the overdrive coupling unit 124 to intervene.

[0049] (4) Overdrive coupling unit 124: connected to the first precharge node A1, the second precharge node A2 and the scan line 200 respectively. Its function is: in the overdrive compensation mode, the overdrive coupling unit 124 couples the first overdrive voltage on the first precharge node A1 and the second overdrive voltage on the second precharge node A2 to the scan line 200 in a time-division manner; wherein, in this embodiment, time-division coupling means that within the same gate drive pulse period, the first overdrive voltage is coupled first to form a rising edge instantaneous high voltage segment, and then the second overdrive voltage is coupled to form a falling edge instantaneous low voltage segment, so that the two are staggered in time and do not overlap.

[0050] Therefore, this embodiment divides the overdrive compensation unit 120 into a first pre-charge unit 121, a second pre-charge unit 122, an isolation control unit 123, and an overdrive coupling unit 124, achieving local pre-storage and instantaneous time-division coupling of the overdrive voltage. On one hand, the overdrive voltage does not need to be continuously transmitted on a long-distance clock line, but is released through coupling only at the output moment, significantly reducing dynamic power consumption and electromagnetic interference. On the other hand, the isolation control unit 123 disconnects the signal generation unit 110 from the scan line 200 during overdrive, avoiding damage to the preceding shift register circuit by high / low voltage pulses and improving circuit reliability. In addition, each gate drive module 100 independently has a pre-charge unit and a coupling unit, which can independently control the overdrive intensity according to the temperature difference of each module's location, achieving more precise compensation. Therefore, this embodiment improves the gate drive capability under extreme temperatures while also achieving low power consumption, high reliability, and high compensation accuracy.

[0051] Figure 4 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application; as follows: Figure 4As shown, the first pre-charge unit 121 includes a first transistor T1 and a first pre-storage capacitor C1; the control terminal of the first transistor T1 is connected to the pre-charge enable terminal EN, the first terminal of the first transistor T1 is connected to the first overdrive voltage terminal VGH1, and the second terminal of the first transistor T1 is connected to the first pre-charge node A1; the first terminal of the first pre-storage capacitor C1 is connected to the first pre-charge node A1, and the second terminal of the first pre-storage capacitor C1 is grounded.

[0052] like Figure 4 As shown, the second pre-charge unit 122 in this embodiment includes a second transistor T2 and a second pre-storage capacitor C2; the control terminal of the second transistor T2 is connected to the pre-charge enable terminal EN, the first terminal of the second transistor T2 is connected to the second overdrive voltage terminal VGL1, and the second terminal of the second transistor T2 is connected to the second pre-charge node A2; the first terminal of the second pre-storage capacitor C2 is connected to the second pre-charge node A2, and the second terminal of the second pre-storage capacitor C2 is grounded.

[0053] like Figure 4 As shown, the isolation control unit 123 in this embodiment includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The control terminal of the third transistor T3 is connected to the first overdrive clock signal terminal CLK_T1A, and the first terminal of the third transistor T3 is connected to the power supply terminal VDD. The control terminal of the fourth transistor T4 is connected to the second overdrive clock signal terminal CLK_T2A, the first terminal of the fourth transistor T4 is connected to the power supply terminal VDD, and the second terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3. The control terminal of the fifth transistor T5 is connected to the second terminal of the fourth transistor T4, the first terminal of the fifth transistor T5 is connected to the drive output terminal G1 of the signal generation unit, and the second terminal of the fifth transistor T5 serves as the output terminal of the isolation control unit 123, which is connected to the scan line 200.

[0054] In this embodiment, the rising edge of the first overdrive clock signal corresponds to the rising edge of the reference clock signal corresponding to the current stage gate drive module 100; the rising edge of the second overdrive clock signal corresponds to the falling edge of the reference clock signal; and the high-level width of the first overdrive clock signal and the second overdrive clock signal is smaller than the high-level width of the reference clock signal.

[0055] like Figure 4As shown, the overdrive coupling unit 124 in this embodiment includes a sixth transistor T6 and a seventh transistor T7; the control terminal of the sixth transistor T6 is connected to the first overdrive clock signal terminal CLK_T1A, the first terminal of the sixth transistor T6 is connected to the first precharge node A1, and the second terminal of the sixth transistor T6 is connected to the scan line 200; the control terminal of the seventh transistor T7 is connected to the second overdrive clock signal terminal CLK_T2A, the first terminal of the seventh transistor T7 is connected to the second precharge node A2, and the second terminal of the seventh transistor T7 is connected to the scan line 200.

[0056] In this embodiment, the conduction type of the third transistor T3 is opposite to that of the sixth transistor T6, and the conduction type of the fourth transistor T4 is opposite to that of the seventh transistor T7.

[0057] Here, combined with Figure 5 , Figure 6 and Figure 7 The timing diagram shown, with the third transistor T3 and the fourth transistor T4 being P-type MOSFETs (conducting at low level), and the remaining first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, and seventh transistor T7 being N-type MOSFETs (conducting at high level), illustrates the working principle of the gate drive module 100 circuit structure in this embodiment as follows: (1) Precharge phase (occurs during the blanking period of each frame) like Figure 5 As shown, during the blanking period of each frame, the precharge enable signal is high; at this time, the first transistor T1 and the second transistor T2 are turned on. The first overdrive voltage (Vgh1, for example +30V) output from the first overdrive voltage terminal VGH1 charges the first pre-storage capacitor C1 through the first transistor T1, and the voltage of the first precharge node A1 is raised to Vgh1; the second overdrive voltage (Vgl1, for example -12V) output from the second overdrive voltage terminal VGL1 charges the second pre-storage capacitor C2 through the second transistor T2, and the voltage of the second precharge node A2 is pulled down to Vgl1. During this period, both the first and second overdrive clock signals are low, therefore the sixth transistor T6 and the seventh transistor T7 are turned off, isolating the scan line 200 from the precharge node. Simultaneously, the third transistor T3 is turned on because the first overdrive clock signal is low, and the fourth transistor T4 is also turned on because the second overdrive clock signal is low. The power supply voltage output from the power supply terminal VDD is applied to the control terminal of the fifth transistor T5 through the third transistor T3 and the fourth transistor T4, thus turning on the fifth transistor T5 and connecting the drive output terminal G1 of the signal generation unit to the scan line 200. However, during the blanking period, the signal generation unit 110 has no initial gate drive signal output, and the scan line 200 has no output requirement; this state does not affect the display. After precharging is complete, the first precharge node A1 and the second precharge node A2 stably store Vgh1 and Vgl1, respectively.

[0058] (2) Normal driving mode (without overdrive compensation) When the system determines that overdrive is not required (e.g., in a normal temperature environment), the precharge enable signal goes low and remains low, the first transistor T1 and the second transistor T2 are turned off, and the charge stored in the first pre-storage capacitor C1 and the second pre-storage capacitor C2 during the blanking period of the previous frame slowly leaks out but is not used. Figure 6 As shown, the first and second overdrive clock signals remain low throughout the scan, the third transistor T3 and the fourth transistor T4 are both turned on, the power supply voltage is applied to the control terminal of the fifth transistor T5, the fifth transistor T5 is turned on, and the initial gate drive signal (standard high level Vgh2, standard low level Vgl2) output by the signal generation unit 110 is directly transmitted to the scan line 200. The sixth transistor T6 and the seventh transistor T7 are turned off, the overdrive voltage does not participate in the output, thus enabling the scan line 200 to obtain a standard gate scan waveform; wherein, in Figure 6 In the diagram, CLK_T1 represents the basic clock signal waveform corresponding to the first-stage gate drive module 100, CLK_T3 represents the basic clock signal waveform corresponding to the third-stage gate drive module 100, CLK_T1A represents the output waveform of the first overdrive clock signal terminal corresponding to the first-stage gate drive module 100, CLK_T2A represents the output waveform of the second overdrive clock signal terminal corresponding to the first-stage gate drive module 100, G1 represents the output waveform of the drive output terminal G1 of the signal generation unit corresponding to the first-stage gate drive module 100, and G2 represents the output waveform of the output terminal of the overdrive compensation unit 120 corresponding to the first-stage gate drive module 100.

[0059] (3) Overdrive compensation mode (taking low temperature environment as an example) When the system determines that overdrive is required, the precharge enable signal completes precharge during the blanking period of the previous frame, and is low during the scan period of the current frame, thus stopping charging the precharge node. Based on the reference clock signal corresponding to each gate drive module 100, the first overdrive clock signal and the second overdrive clock signal each generate a high-level pulse, specifically as follows: Figure 6 and Figure 7 As shown: the rising edge of the first overdrive clock signal is aligned with the rising edge of the reference clock signal, and the rising edge of the second overdrive clock signal is aligned with the falling edge of the reference clock signal. Furthermore, the high-level width of both pulses is much smaller than the high-level width of the reference clock signal. The overdrive compensation mode in this embodiment specifically includes the following working stages: ① Rising Edge Overdrive Stage: When the rising edge of the reference clock signal arrives, the first overdrive clock signal is high and the second overdrive clock signal is low. At this time: the third transistor T3 is off, the fourth transistor T4 is on, and the power supply voltage output from the power supply terminal VDD is applied to the control terminal of the fifth transistor T5 through the fourth transistor T4. The fifth transistor T5 is on, sending the high level Vgh2 of the initial gate drive signal to the scan line 200. At the same time, the sixth transistor T6 is on, and the seventh transistor T7 is off, coupling the first overdrive voltage Vgh1 (+30V) on the first precharge node A1 to the scan line 200. The scan line 200 simultaneously receives Vgh2 from the fifth transistor T5 and Vgh1 from the sixth transistor T6. Since Vgh1 is higher than Vgh2, the voltage of the scan line 200 is quickly pulled up to near Vgh1, realizing rising edge overdrive.

[0060] ② High-level maintenance phase: After the first overdrive clock pulse ends and before the second overdrive clock pulse arrives, both the first and second overdrive clock signals are low. At this time: the third transistor T3 and the fourth transistor T4 are both turned on, the sixth transistor T6 and the seventh transistor T7 are both turned off, the power supply voltage is continuously applied to the control terminal of the fifth transistor T5, the fifth transistor T5 remains on, and the voltage of scan line 200 is maintained at Vgh2 of the initial gate drive signal.

[0061] ③ Falling Edge Overdrive Stage: When the falling edge of the reference clock arrives, the second overdrive clock signal is high and the first overdrive clock signal is low. At this time: the fourth transistor T4 is off, the third transistor T3 is on, and the power supply voltage output from the power supply terminal VDD is applied to the control terminal of the fifth transistor T5 through the third transistor T3. The fifth transistor T5 remains on, sending the low level Vgl2 of the initial gate drive signal to the scan line 200. At the same time, the sixth transistor T6 is off, and the seventh transistor T7 is on, coupling the second overdrive voltage Vgl1 (-12V) on the second precharge node A2 to the scan line 200. At this time, the scan line 200 receives both Vgl2 and Vgl1. Since Vgl1 is lower than Vgl2, the voltage of the scan line 200 is quickly pulled down to near Vgl1, realizing the falling edge overdrive. After the second overdrive clock pulse ends, the second overdrive clock signal goes low, the seventh transistor T7 is off, the fifth transistor T5 remains on, and the voltage of the scan line 200 is maintained by the initial gate drive signal Vgl2.

[0062] In summary, this embodiment, by pre-charging during the blanking period of the previous frame and time-division coupling the overdrive voltage during the scanning period of the current frame, enables the scan line to obtain an instantaneous high voltage Vgh1 at the rising edge and an instantaneous low voltage Vgl1 at the falling edge. This significantly improves the gate turn-on and turn-off speeds and overcomes the problem of insufficient charging caused by TFT mobility variations under extreme temperatures. Simultaneously, the overdrive voltage is locally stored and instantaneously released, eliminating the need for long-distance high-voltage transmission and reducing dynamic power consumption and electromagnetic interference. The opposite conduction types of the third and fourth transistors compared to the sixth and seventh transistors ensure logical complementarity between the clock signal and the isolation control unit and the overdrive coupling unit, avoiding signal conflicts and improving circuit reliability.

[0063] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes the gate driving circuit shown in the above embodiment, wherein the drive output terminal of the signal generation unit and the output terminal of the overdrive compensation unit in the same gate driving module are electrically connected to the same scan line.

[0064] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0065] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0066] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, comprising N cascaded gate driving modules, characterized in that, Each gate drive module includes: The signal generation unit is configured to generate the stage transmission signal and the initial gate drive signal corresponding to the current stage in response to the stage transmission signal output by the previous stage gate drive module. The overdrive compensation unit, connected to the drive output terminal and the scan line of the signal generation unit, is configured to: output the initial gate drive signal to the scan line in normal drive mode; and perform segmented voltage modulation on the initial gate drive signal in overdrive compensation mode to generate a target gate drive signal, and output the target gate drive signal to the scan line. The target gate drive signal includes at least two high-voltage segments with different voltage values ​​within one pulse period; the target gate drive signal includes, within one pulse period: a first overdrive voltage segment at the rising edge, a first sustaining voltage segment after the first overdrive voltage segment, a second overdrive voltage segment at the falling edge, and a second sustaining voltage segment after the second overdrive voltage segment; the voltage value of the first overdrive voltage segment is greater than the voltage value of the first sustaining voltage segment, and the voltage value of the second overdrive voltage segment is less than the voltage value of the second sustaining voltage segment.

2. The gate driving circuit according to claim 1, characterized in that, The voltage values ​​of the first sustaining voltage segment and the second sustaining voltage segment are respectively matched with the voltage value of the initial gate drive signal; the first overdrive voltage segment and the first sustaining voltage segment serve as the two high voltage segments.

3. The gate driving circuit according to claim 1, characterized in that, The overdrive compensation unit includes: The first pre-charge unit is connected to the pre-charge enable terminal, the first overdrive voltage terminal and the first pre-charge node respectively, and is configured to: charge the first pre-charge node according to the first overdrive voltage output by the first overdrive voltage terminal in response to the pre-charge enable signal output by the pre-charge enable terminal. The second pre-charge unit is connected to the pre-charge enable terminal, the second overdrive voltage terminal, and the second pre-charge node, respectively, and is configured to: charge the second pre-charge node according to the second overdrive voltage output by the second overdrive voltage terminal in response to the pre-charge enable signal output by the pre-charge enable terminal. An isolation control unit, connected to the drive output terminal of the signal generation unit and the scan line respectively, is configured to: in normal driving mode, conduct the electrical connection between the drive output terminal of the signal generation unit and the scan line; in overdrive compensation mode, disconnect the electrical connection between the signal generation unit and the scan line. An overdrive coupling unit, connected to the first precharge node, the second precharge node, and the scan line respectively, is configured to: in overdrive compensation mode, time-division coupling the first overdrive voltage on the first precharge node and the second overdrive voltage on the second precharge node to the scan line.

4. The gate driving circuit according to claim 3, characterized in that, The first pre-charge unit includes: The first transistor has a control terminal connected to the precharge enable terminal, a first terminal connected to the first overdrive voltage terminal, and a second terminal connected to the first precharge node. A first pre-storage capacitor, the first end of which is connected to the first pre-charge node, and the second end of which is grounded.

5. The gate driving circuit according to claim 3, characterized in that, The second pre-charge unit includes: The second transistor has a control terminal connected to the precharge enable terminal, a first terminal connected to the second overdrive voltage terminal, and a second terminal connected to the second precharge node. The second pre-storage capacitor has its first terminal connected to the second pre-charge node and its second terminal grounded.

6. The gate driving circuit according to claim 3, characterized in that, The isolation control unit includes: The third transistor has its control terminal connected to the first overdrive clock signal terminal and its first terminal connected to the power supply terminal. The fourth transistor has its control terminal connected to the second overdrive clock signal terminal, its first terminal connected to the power supply terminal, and its second terminal connected to the second terminal of the third transistor. The fifth transistor has its control terminal connected to the second terminal of the fourth transistor, its first terminal connected to the drive output terminal of the signal generation unit, and its second terminal serving as the output terminal of the isolation control unit.

7. The gate driving circuit according to claim 6, characterized in that, The rising edge of the first overdrive clock signal corresponds to the rising edge of the reference clock signal corresponding to the current stage gate drive module; the rising edge of the second overdrive clock signal corresponds to the falling edge of the reference clock signal; and the high-level width of the first overdrive clock signal and the second overdrive clock signal is less than the high-level width of the reference clock signal.

8. The gate driving circuit according to claim 7, characterized in that, The overdrive coupling unit includes: The sixth transistor has its control terminal connected to the first overdrive clock signal terminal, its first terminal connected to the first precharge node, and its second terminal connected to the scan line. The seventh transistor has its control terminal connected to the second overdrive clock signal terminal, its first terminal connected to the second precharge node, and its second terminal connected to the scan line.

9. The gate driving circuit according to claim 8, characterized in that, The third transistor has the opposite conduction type to the sixth transistor, and the fourth transistor has the opposite conduction type to the seventh transistor.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the drive output terminal of the signal generation unit and the output terminal of the overdrive compensation unit in the same gate driving module are electrically connected to the same scan line.

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