Display device, driving method thereof, and electronic device including the same

Abstract

The present application relates to a display device, a driving method thereof, and an electronic device including the same. A display device is provided, which can include an i-th pixel receiving a data voltage and a reference voltage in response to an i-th scan signal during a display period, and an i+1-th pixel receiving a data voltage and a reference voltage in response to an i+1-th scan signal during the display period. The i-th scan signal can be applied to the i-th pixel during a first to third period of an blanking period, the i+1-th scan signal can be applied to the i+1-th pixel during the first period, the i-th pixel can receive the data voltage and the reference voltage for sensing during the first period, and a level of the reference voltage can be changed by the i+1-th pixel.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2025-0011272, filed on January 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, a method for driving a display device, and an electronic device including a display device. Background Technology

[0004] Electronic devices that provide images to users (such as smartphones, digital cameras, laptops, navigation devices, and smart TVs) include display devices for displaying images. The display device generates images and provides the generated images to the user via a screen.

[0005] The display device includes a display panel, a scan driver, and a data driver. The display panel includes a plurality of pixels for generating an image. The scan driver applies a scan signal to the pixels, and the data driver applies a data voltage to the pixels. The pixels receive the data voltage in response to the scan signal and generate an image using the data voltage.

[0006] When some pixels are defective, the defect may affect neighboring pixels, causing them to emit light with a brightness higher than normal and potentially be perceived as bright spots. Therefore, it is desirable to develop techniques for detecting the amount of brightness variation in bright pixels that may be perceived as bright spots and for compensating for the brightness of these bright pixels. Summary of the Invention

[0007] This disclosure provides a display device, a driving method for the display device, and an electronic device including the display device, capable of detecting brightness changes in bright pixels around defective pixels and compensating for the brightness of the bright pixels.

[0008] An embodiment of the present invention provides a display device comprising: an i-th pixel disposed in an i-th row, which receives a data voltage and a reference voltage in response to an i-th scan signal during a display period; and an (i+1)-th pixel disposed in an (i+1)-th row, which also receives a data voltage and a reference voltage in response to an (i+1)-th scan signal during a display period, wherein a blanking period following the display period includes a first time period, a second time period, and a third time period, wherein the first time period, the second time period, and the third time period are consecutive, the i-th scan signal is applied to the i-th pixel during the first time period to the third time period, the (i+1)-th scan signal is applied to the (i+1)-th pixel during the first time period, and during the first time period, the i-th pixel receives a data voltage and a reference voltage for sensing, and the level of the reference voltage is changed by the (i+1)-th pixel, where i is a natural number greater than 0.

[0009] During the display cycle, the i-th scan signal and the (i+1)-th scan signal can be sequentially applied to the i-th pixel and the (i+1)-th pixel, respectively, and the (i+1)-th scan signal can at least partially overlap with the i-th scan signal. The level of the reference voltage can be reduced by the (i+1)-th pixel during the first time period.

[0010] The i-th scan signal may include an i-th write scan signal and an i-th sample scan signal. The i+1-th scan signal may also include an i+1-th write scan signal and an i+1-th sample scan signal. The i-th write scan signal may be activated and applied to the i-th pixel during a first time period and a third time period. The i-th sample scan signal may be activated and applied to the i-th pixel during both the first and third time periods. The i+1-th sample scan signal may be activated and applied to the i+1-th pixel during the first time period. During the first time period, the i-th pixel may receive a data voltage for sensing in response to the i-th write scan signal and may also receive a reference voltage in response to the i-th sample scan signal. The i+1-th pixel may be connected to a reference line receiving the reference voltage during the first time period in response to the i+1-th sample scan signal. The i+1-th pixel may include: a light-emitting element including an anode and a cathode, wherein the anode and cathode are short-circuited; and a short-circuit resistor formed at the short-circuited portion of the display device and connected to the reference line during the first time period. During the second time period, the i-th write scan signal can be deactivated, and during the second time period, the sensed voltage sensed in the i-th pixel based on the data voltage, reference voltage, and short-circuit resistance used for sensing can be output through the reference line.

[0011] In one implementation, the (i+1)th write scan signal can be deactivated during the first to third time periods, and the (i+1)th sample scan signal is deactivated during the second and third time periods. In another implementation, during the display cycle, the (i)th write scan signal and the (i)th sample scan signal can be applied to the (i)th pixel in the same timing sequence. The (i)th pixel can receive a data voltage in response to the (i)th write scan signal and can receive a reference voltage in response to the (i)th sample scan signal. During the display cycle, the (i+1)th write scan signal and the (i+1)th sample scan signal can be applied to the (i+1)th pixel in the same timing sequence, and the (i+1)th pixel can receive a data voltage in response to the (i+1)th write scan signal and can receive a reference voltage in response to the (i+1)th sample scan signal.

[0012] In an embodiment, the display device may further include: a data line that can be connected to the i-th pixel and the (i+1)-th pixel, capable of receiving a data voltage during a display cycle, receiving a data voltage for sensing during a first time period, and receiving a recovery data voltage during a third time period; a reference line that can be connected to the i-th pixel and the (i+1)-th pixel, and capable of receiving a reference voltage during the display cycle, the first time period, and the third time period; an i-th write scan line that can be connected to the i-th pixel and can receive an i-th write scan signal; an i-th sampling scan line that can be connected to the i-th pixel and can receive an i-th sampling scan signal; an (i+1)-th write scan line that can be connected to the (i+1)-th pixel and can receive an (i+1)-th write scan signal; and an (i+1)-th sampling scan line that can be connected to the (i+1)-th pixel and can receive an (i+1)-th sampling scan signal. The i-th pixel may include: a first transistor, which may include a first electrode connected to a first power line, a control electrode connected to a first node, and a second electrode connected to a second node; a second transistor, which may include a first electrode connected to a data line, a second electrode connected to the first node, and a control electrode connected to the i-th write scan line; a third transistor, which may include a first electrode connected to a reference line, a second electrode connected to the second node, and a control electrode connected to the i-th sampling scan line; an i-th capacitor, which may include a first electrode connected to the first node and a second electrode connected to the second node; and an i-th light-emitting element, which may include an anode connected to the second node and a cathode connected to the second power line. The (i+1)th pixel may include: a first-1 transistor, which may include a first electrode connected to a first power line, a control electrode connected to a first-1 node, and a second electrode connected to a second-1 node; a second-1 transistor, which may include a first electrode connected to a data line, a second electrode connected to a first-1 node, and a control electrode connected to the (i+1)th write scan line; a third-1 transistor, which may include a first electrode connected to a reference line, a second electrode connected to a second-1 node, and a control electrode connected to the (i+1)th sampling scan line; an (i+1)th capacitor, which may include a first electrode connected to a first-1 node and a second electrode connected to a second-1 node; an (i+1)th light-emitting element, which may include an anode connected to a second-1 node and a cathode connected to a second power line; and a short-circuit resistor, which may be formed due to a short circuit in a portion of the anode and a portion of the cathode. In an implementation, the display device may further include: a timing controller, which may be configured to compensate the data voltage applied to the i-th pixel based on a sensed voltage output through a reference line connected to the i-th pixel during a second time period.

[0013] In the implementation, a display on period and a display off period preceding the display on period are defined. The display on period may include a display period and a blanking period. The display off period may include a first sensing period and a second sensing period. During the first sensing period, the i-th scan signal and the i+1-th scan signal may be sequentially applied to the i-th pixel and the i+1-th pixel, respectively. The i-th pixel may receive a voltage and a reference voltage for sensing in response to the i-th scan signal, and the i+1-th pixel may receive a voltage and a reference voltage for sensing in response to the i+1-th scan signal. The second sensing period may include a fourth period, a fifth period, a sixth period, a seventh period, an eighth period, and a ninth period, wherein the fourth, fifth, sixth, seventh, eighth, and ninth periods are consecutive. The i-th write scan signal may be activated and applied to the i-th pixel during the fourth and sixth periods of the second sensing period, and the i-th sampling scan signal may be activated and applied to the i-th pixel during the fourth to sixth periods of the second sensing period. The (i+1)-th write scan signal may be activated and applied to the (i+1)-th pixel during the seventh and ninth periods of the second sensing period, and the (i+1)-th sampling scan signal may be activated and applied to the (i+1)-th pixel during the fourth period and the seventh to ninth periods of the second sensing period. The i-th pixel may receive a data voltage and a reference voltage for sensing during the fourth period of the second sensing period, and the (i+1)-th pixel may receive a data voltage and a reference voltage for sensing during the seventh period of the second sensing period. The level of the reference voltage may be reduced by the (i+1)-th pixel during the fourth period of the second sensing period.

[0014] In an embodiment of the present invention, a driving method for a display device includes: during a display cycle, applying a data voltage and a reference voltage to an i-th pixel disposed in an i-th row in sync with an i-th scan signal; during the display cycle, applying a data voltage and a reference voltage to an i+1-th pixel disposed in an i+1-th row in sync with an i+1-th scan signal; during a first time period of a blanking cycle following the display cycle, applying a sensing data voltage to the i-th pixel in sync with an i-th write scan signal of the i-th scan signal; during the first time period, applying a reference voltage to the i-th pixel in sync with an i-th sampling scan signal of the i-th scan signal; during the first time period, connecting the i+1-th pixel to a reference line receiving the reference voltage in sync with an i+1-th sampling scan signal of the i+1-th scan signal; and during a second time period following the first time period, outputting a sensing voltage sensed in the i-th pixel based on the sensing data voltage, the reference voltage, and a short-circuit resistance via the reference line, wherein the short-circuit resistance is formed due to a short circuit between the anode and cathode of the i+1-th pixel, where i is a natural number greater than 0.

[0015] In one embodiment, the driving method may further include compensating the data voltage applied to the i-th pixel based on a sense voltage output through a reference line. In another embodiment, the driving method may further include: during a first time period, reducing the level of the reference voltage by the (i+1)-th pixel, wherein the (i+1)-th pixel may include: a light-emitting element including an anode and a cathode, wherein the anode and cathode are short-circuited; and a short-circuit resistor, which may be formed at the location of the short circuit and connected to the reference line during the first time period. In yet another embodiment, the driving method may further include: during a third time period following a second time period, applying a recovery data voltage to the i-th pixel in synchronization with the i-th write scan signal; and during the third time period, applying a reference voltage to the i-th pixel in synchronization with the i-th sampling scan signal.

[0016] In an embodiment of the present invention, the electronic device includes: a display device for providing an image to a user; and a processor configured to process an image signal and provide the image signal to the display device, wherein the display device includes: an i-th pixel disposed in an i-th row and receiving a data voltage and a reference voltage in response to an i-th scan signal during a display period; and an i+1-th pixel disposed in an i+1-th row and receiving a data voltage and a reference voltage in response to an i+1-th scan signal during a display period, wherein a blanking period following the display period includes a first time period, a second time period, and a third time period, and the first time period, the second time period, and the third time period are consecutive, the i-th scan signal is applied to the i-th pixel during the first time period to the third time period, the i+1-th scan signal is applied to the i+1-th pixel during the first time period, the i-th pixel receives a data voltage and a reference voltage for sensing during the first time period, and the level of the reference voltage is reduced by the i+1-th pixel during the first time period, and the sensed voltage sensed in the i-th pixel is output through a reference line during the second time period following the first time period, wherein i is a natural number greater than 0. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept.

[0018] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present invention.

[0019] Figure 2 These are schematic diagrams of electronic devices according to various embodiments.

[0020] Figure 3 This is a perspective view of a display device according to an embodiment of the present invention.

[0021] Figure 4This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0022] Figure 5 yes Figure 3 Block diagram of the display device shown.

[0023] Figure 6 It is shown Figure 5 The diagram shows the equivalent circuits of the first, second, and third pixels among the pixels shown.

[0024] Figure 7 yes Figure 6 The equivalent circuit diagram of the first pixel is shown.

[0025] Figure 8 It is shown Figure 5 The cross-section of any one pixel shown is used as an example diagram.

[0026] Figure 9 It shows the setting Figure 8 The cross-section of the light conversion portion on the pixel layer shown is presented as an example.

[0027] Figure 10 Is applied to Figure 5 The timing diagram of the scan signal for the scan line shown is shown.

[0028] Figure 11 It is used to describe pixels in Figure 10 The diagram shown illustrates the operations within the display cycle.

[0029] Figures 12A to 12C It is used to describe pixels in Figure 10 The diagram shows the operations in the first, second, and third time periods.

[0030] Figure 13 This is a diagram illustrating, as an example, the configuration of a cross-section of a defective pixel in which a defect occurs.

[0031] Figure 14 It is a circuit diagram used to describe the operation of the i-th pixel set in the i-th row and the i+1-th pixel set in the i+1-th row during the display cycle.

[0032] Figure 15 Is applied to Figure 14 The timing diagrams of the i-th and i+1-th scan signals of the i-th and i+1-th pixels are shown.

[0033] Figure 16 This is a timing diagram of the i-th scan signal applied to the i-th pixel and the sense voltage output through the h-th reference line during the blanking period, assuming the (i+1)-th pixel is a normal pixel.

[0034] Figure 17A and Figure 17B It is a diagram used to describe the operation of the i-th pixel and the i+1-th pixel in the first and second time periods when the i+1-th pixel is a defective pixel.

[0035] Figure 18 This is a timing diagram of the i-th scan signal applied to the i-th pixel, the i+1-th scan signal applied to the i+1-th pixel, and the sensing voltage during the blanking period, when the i+1-th pixel is a defective pixel.

[0036] Figure 19 Is Figure 10 The diagram shows the timing of signals in the display off cycle prior to the display on cycle.

[0037] Figure 20 It is used to describe the i-th pixel and the (i+1)-th pixel in Figure 19 The diagram shows the operation during the first sensing period.

[0038] Figure 21 It is used to describe the i-th pixel and the (i+1)-th pixel in Figure 19 The diagram shows the operation during the second sensing period.

[0039] Figure 22 This is a graph showing the test results obtained by testing the brightness changes in the defective pixel and the previous pixel while changing the short-circuit resistance of the defective pixel.

[0040] Figure 23 This is a flowchart describing a driving method for a display device according to an embodiment of the present invention. Detailed Implementation

[0041] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "attached to" another element, it may be directly disposed on, directly connected to, or directly attached to the other element, or there may be other elements disposed between the element and the other element.

[0042] The same reference numerals or symbols always denote the same elements. In the drawings, the thickness, ratios, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0043] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. For example, without departing from the scope of the inventive concept, the first element, first component, first region, first layer, or first segment discussed below may be referred to as a second element, second component, second region, second layer, or second segment. Similarly, a second element, second component, second region, second layer, or second segment may be referred to as a first element, first component, first region, first layer, or first segment. In this specification, unless the context clearly indicates otherwise, the singular expressions “a,” “an,” and “the” are intended to also include the plural forms.

[0044] Furthermore, the terms "below," "under," "on the lower side," "above," "on top," "on the upper side," etc., can be used to describe the relationships between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the accompanying drawings.

[0045] It will also be understood that the terms “comprising,” “including,” “having,” and / or “including, containing,” as used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formalized sense unless expressly stated herein.

[0047] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0048] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present invention.

[0049] refer to Figure 1 The electronic device ED according to an embodiment may include a display device DD for providing images to a user, and may also include another module or device with additional functions in addition to the display device DD. The electronic device ED according to an embodiment may include a display module DM, one or more processors PRS, a memory MEM, and a power module PSM, and the display device DD may include the display module DM.

[0050] One or more processors (PRS) may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The one or more processors (PRS) may perform operations as a single unit, as a whole, or as a mixture of processors performing other operations and other operations. For example, if two processors are present, each processor may perform different steps in the operation, or one processor may perform all the operation steps. The one or more processors (PRS) may process image signals and provide image signals to a display device (DD), and the display device (DD) may generate an image corresponding to the image signals.

[0051] In implementation, from a functional or structural perspective, one or more processors (PRS) can be divided and configured as two or more. For example, one or more processors (PRS) may include a main processor and an auxiliary processor, wherein the main processor is in the form of a first driver chip including a central processing unit, and the auxiliary processor is in the form of a second driver chip including a controller that receives image signals from the main processor and processes the image signals to conform to the interface specifications of the display module (DM).

[0052] Data used to operate one or more processors (PRS) or display modules (DM) can be stored in memory (MEM). When one or more processors (PRS) execute the application program stored in memory (MEM), image data signals and / or input control signals can be sent to display modules (DM), and display modules (DM) can process the provided signals and output image information through the display screen.

[0053] The power supply module (PSM) may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module and generates power for operating the electronic device (ED). The power supply module (PSM) can supply power to the display module (DM) and the processor (PRS).

[0054] At least one of the components of the electronic device ED described above may be included in the display device DD according to the embodiments described above. Furthermore, several independent modules that include functions in one module may be included in the display device DD, and other modules may be provided separately from the display device DD. For example, the display device DD may include a display module DM, and one or more processors PRS, memory MEM, and power modules PSM may be provided in the electronic device ED in the form of devices different from the display device DD.

[0055] Figure 2 These are schematic diagrams of electronic devices according to various embodiments.

[0056] refer to Figure 2 The display device DD according to the embodiments of the present invention can be applied to various electronic devices. For example, various electronic devices may include electronic devices for displaying images, such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions 10_1d, or desktop monitors 10_1e.

[0057] Furthermore, according to the embodiments, the display device DD can be applied to various electronic devices, including wearable electronic devices such as smart glasses 10_2a, head-mounted displays 10_2b, or smartwatches 10_2c. Additionally, the various electronic devices can include automotive electronic devices 10_3, such as central information displays (CIDs) or interior mirror displays installed on the dashboard, center console, and instrument panel of a vehicle.

[0058] Figure 3 This is a perspective view of a display device according to an embodiment of the present invention.

[0059] refer to Figure 3 The display device DD may have a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. The corners of the display device DD may have a rounded shape.

[0060] In the following text, the direction that substantially intersects the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, as used herein, the phrase "in a plan view" can be defined as the state as observed from the third direction DR3.

[0061] The upper surface of the display device DD can be defined as a display surface DS, and has a plane defined by a first direction DR1 and a second direction DR2. An image generated in the display device DD can be provided to the user through the display surface DS.

[0062] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. An image may be displayed in the display area DA, or it may not be displayed in the non-display area NDA. The non-display area NDA may surround the display area DA and define the edge of the display device DD.

[0063] Figure 4 This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0064] refer to Figure 4The electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and a housing CAS. The display device DD may include a display module DM and a window WIN disposed on the display module DM.

[0065] The electronic module EM and the power module PSM can be positioned below the display device DD. Although not shown, the electronic module EM and the power module PSM can be connected to each other via separate flexible circuit boards.

[0066] The electronic module EM can control the operation of the display device DD. The electronic module EM may include one or more processors PRS as described above. The power module PSM can supply power to the electronic module EM and the display module DM.

[0067] The housing CAS can be installed beneath the electronic module EM and the power module PSM. The housing CAS can accommodate the display device DD, the electronic module EM, and the power module PSM. The housing CAS can protect the display device DD, the electronic module EM, and the power module PSM.

[0068] The display module DM may have a long side extending in the first direction DR1 and a short side extending in the second direction DR2. The corners of the display module DM may have a rounded shape.

[0069] The display module DM may include a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA may surround the display area DA. The display area DA and the non-display area NDA of the display module DM may be respectively connected to... Figure 3 The display area DA and the non-display area NDA shown correspond to each other. An image can be generated in the display area DA, or it is not necessary to generate an image in the non-display area NDA.

[0070] The display module DM may include a display panel DP and a light conversion component LCP disposed on the display panel DP. The display panel DP, like the display module DM, may include a display area DA and a non-display area NDA disposed around and surrounding the display area DA. An image can be generated in the display area DA of the display panel DP.

[0071] The display panel DP according to embodiments of the present invention can be an emissive display panel. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The emissive layer of an organic light-emitting display panel may include organic light-emitting materials. The emissive layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP may be described as an organic light-emitting display panel.

[0072] The light conversion component (LCP) can supply light generated in the display panel (DP) and convert the color of the supplied light. Furthermore, the LCP can reduce the reflectivity of external light. This component will be described in detail below.

[0073] The window (WIN) can be optically transparent. For example, the window (WIN) can include glass, transparent plastic, etc. The window (WIN) can protect the display module (DM) from external impacts and scratches. The front surface of the window (WIN) can correspond to the display surface (DS) of the display device (DD) described above.

[0074] The front surface of window WIN may include a transmissive region TA and a border region BA surrounding the transmissive region TA. The transmissive region TA can transmit light. The border region BA may surround the transmissive region TA, may be printed in a predetermined color, and blocks light. In a plan view, the transmissive region TA may overlap with the display region DA, and the border region BA may overlap with the non-display region NDA.

[0075] The image generated in the display area DA can be provided to an external user through the transmission area TA. The non-display area NDA can remain unexposed to the outside due to the border area BA.

[0076] Although not shown, the display device DD may also include an input sensing section disposed between the display panel DP and the light conversion section LCP. The input sensing section may include multiple sensing elements (not shown) for sensing external inputs. The sensing elements may sense the external inputs capacitively.

[0077] When manufacturing the display panel DP, the input sensing portion can be directly manufactured on the display panel DP. However, embodiments of the present invention are not limited to this, and the input sensing portion can be manufactured as a panel separate from the display panel DP and attached to the display panel DP by an adhesive.

[0078] Figure 5 yes Figure 3 Block diagram of the display device shown.

[0079] refer to Figure 5 The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, and a timing controller T-CON. The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, and multiple reference lines RL1 to RLk. k, m, and n are natural numbers greater than 1.

[0080] Scan lines SL1 to SLm can extend along the first direction DR1 and can be connected to the pixel PX and the scan driver SDV. Data lines DL1 to DLn and reference lines RL1 to RLk can extend along the second direction DR2 and can be connected to the pixel PX and the data driver DDV.

[0081] A first voltage ELVDD and a second voltage ELVSS can be supplied to the display panel DP. The first voltage ELVDD can have a higher level than the second voltage ELVSS. The first voltage ELVDD and the second voltage ELVSS can be applied to the pixel PX.

[0082] The timing controller T-CON can receive image signals RGB and control signals CS from one or more processors PRS as described above. The timing controller T-CON can convert the data format of the image signals RGB to conform to the specification of the data driver DDV and generate image data DATA. The timing controller T-CON can provide the converted image data DATA to the data driver DDV.

[0083] The timing controller T-CON can generate and output scan control signal CS1 and data control signal CS2 in response to an externally provided control signal CS. Scan control signal CS1 can be provided to scan driver SDV, and data control signal CS2 can be provided to data driver DDV.

[0084] The scan driver SDV can generate multiple scan signals in response to the scan control signal CS1. The scan signals can be applied to the pixel PX through scan lines SL1 to SLm.

[0085] The data driver DDV can generate multiple data voltages corresponding to the image data DATA in response to the data control signal CS2. These data voltages can be applied to the pixel PX via data lines DL1 to DLn.

[0086] A pixel (PX) can be supplied with a data voltage in response to a scan signal. A pixel (PX) can display an image by emitting light with a brightness corresponding to the data voltage.

[0087] The data driver DDV can apply a data voltage and a reference voltage to pixel PX for sensing. The data voltage for sensing can be applied to pixel PX through data lines DL1 to DLn. The reference voltage can be applied to pixel PX through reference lines RL1 to RLk.

[0088] The sensed voltage Vsn, sensed in pixel PX based on the data voltage and reference voltage used for sensing, can be provided to the data driver DDV via reference lines RL1 to RLk. The timing controller T-CON can compensate for the data voltage applied to bright pixels adjacent to defective pixels based on the sensed voltage Vsn. This operation will be described in detail below.

[0089] Figure 6 It is shown Figure 5 The diagram shows the equivalent circuits of the first, second, and third pixels among the pixels shown.

[0090] refer to Figure 6 Pixel PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in a first direction DR1. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit light of different colors from each other. For example, the first pixel PX1 may emit red light, the second pixel PX2 may emit blue light, and the third pixel PX3 may emit green light.

[0091] The first direction DR1 can correspond to a row, and the second direction DR2 can correspond to a column. As an example, Figure 6 The diagram shows a first pixel PX1 in the i-th row and j-th column, a second pixel PX2 in the i-th row and (j+1)-th column, and a third pixel PX3 in the i-th row and (j+2)-th column. i and j are natural numbers greater than 0. Although not shown, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be provided to the display panel DP in multiples.

[0092] The first pixel PX1 can be connected to the j-th data line DLj, the i-th scan line SLi, the h-th reference line RLh, the first power line PL1, and the second power line PL2. The second pixel PX2 can be connected to the (j+1)-th data line DLj+1, the i-th scan line SLi, the h-th reference line RLh, the first power line PL1, and the second power line PL2. The third pixel PX3 can be connected to the (j+2)-th data line DLj+2, the i-th scan line SLi, the h-th reference line RLh, the first power line PL1, and the second power line PL2.

[0093] The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be connected to the j-th data line DLj, the (j+1)-th data line DLj+1, and the (j+2)-th data line DLj+2, respectively. The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be connected to the h-th reference line RLh.

[0094] Data lines j-th (DLj), j+1 (DLj+1), and j+2 (DLj+2) can each receive the data voltage Vd and data voltage Vs used for sensing. Reference line h (RLh) can receive the reference voltage Vr.

[0095] The i-th scan line SLi can receive the i-th scan signals SCi and SSi. The i-th scan line SLi can include the i-th write scan line SCLi and the i-th sample scan line SSLi. The i-th scan signals SCi and SSi can include the i-th write scan signal SCi and the i-th sample scan signal SSi. The i-th write scan line SCLi can receive the i-th write scan signal SCi. The i-th sample scan line SSLi can receive the i-th sample scan signal SSi.

[0096] The first power line PL1 can receive the first voltage ELVDD. The second power line PL2 can receive the second voltage ELVSS.

[0097] The first pixel PX1, the second pixel PX2, and the third pixel PX3 may each include multiple transistors T1, T2, and T3, a capacitor CST, and a light-emitting element OLED. Since the configurations of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are identical, they will be used as examples in the following text. Figure 7 This describes the circuit configuration of the first pixel, PX1.

[0098] Figure 7 yes Figure 6 The equivalent circuit diagram of the first pixel is shown.

[0099] In the following text, Figure 7 In this context, the first pixel PX1 is defined as the i-th pixel PXi located in the i-th row, the light-emitting element OLED is defined as the i-th light-emitting element OLEDi, and the capacitor CST is defined as the i-th capacitor CSTi.

[0100] refer to Figure 7 The i-th pixel PXi can be connected to the j-th data line DLj, the h-th reference line RLh, the i-th write scan line SCLi, and the i-th sampling scan line SSLi.

[0101] The i-th pixel PXi may include the i-th light-emitting element OLEDi, a plurality of transistors T1, T2 and T3, and the i-th capacitor CSTi. Transistors T1, T2 and T3 may include a first transistor T1, a second transistor T2 and a third transistor T3.

[0102] The first transistor T1, the second transistor T2, and the third transistor T3 can be NMOS transistors, but are not limited to them, and can also be PMOS transistors. Each of the first transistor T1, the second transistor T2, and the third transistor T3 may include a source electrode, a drain electrode, and a gate electrode. In the following description, for convenience, either the source electrode or the drain electrode is defined as the first electrode, and the other is defined as the second electrode. Furthermore, the gate electrode is defined as the control electrode.

[0103] The i-th light-emitting element OLEDi can be an organic light-emitting element including an anode and a cathode. The anode of the i-th light-emitting element OLEDi can receive a first voltage ELVDD through a first transistor T1, and the cathode of the i-th light-emitting element OLEDi can receive a second voltage ELVSS. The i-th light-emitting element OLEDi can emit light by receiving the first voltage ELVDD and the second voltage ELVSS.

[0104] The first transistor T1 may include a first electrode connected to a first power line PL1 and receiving a first voltage ELVDD, a control electrode connected to a first node N1, and a second electrode connected to a second node N2. The first transistor T1 can be switched on and off by the voltage of the first node N1.

[0105] The anode of the i-th light-emitting element OLEDi can be connected to the second node N2. The cathode of the i-th light-emitting element OLEDi can be connected to the second power line PL2 and receive the second voltage ELVSS.

[0106] The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1, and a control electrode connected to the i-th write scan line SCLi. The second transistor T2 can be switched on and off by the i-th write scan signal SCi received by the i-th write scan line SCLi. The second transistor T2 can receive data voltages Vd and Vs for sensing via the j-th data line DLj.

[0107] The third transistor T3 may include a first electrode connected to the h-th reference line RLh, a second electrode connected to the second node N2, and a control electrode connected to the i-th sampling scan line SSLi. The third transistor T3 can be switched on and off by the i-th sampling scan signal SSi received by the i-th sampling scan line SSLi. The third transistor T3 can receive a reference voltage Vr through the h-th reference line RLh.

[0108] The i-th capacitor CSTi may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2. The i-th capacitor CSTi can be connected to the control electrode of the first transistor T1 and the anode of the i-th light-emitting element OLEDi through the first node N1 and the second node N2.

[0109] Figure 8 It is shown Figure 5 The cross-section of any one pixel shown is used as an example diagram.

[0110] refer to Figure 8 A pixel (PX) can include a transistor (TR) and a light-emitting element (OLED). The transistor (TR) can be... Figure 7 The first transistor T1 is shown in the diagram. The light-emitting element OLED may include a first electrode AE ​​(e.g., anode), a second electrode CE (e.g., cathode), a hole control layer HCL, an electron control layer ECL, and an emitter layer EML. The transistor T1 and the light-emitting element OLED may be disposed on the first substrate SUB1.

[0111] Each of the pixels PX can include a planar region PA and a non-light-emitting region NPA surrounding the light-emitting region PA. The light-emitting element OLED can be disposed in the light-emitting region PA.

[0112] A buffer layer BFL can be disposed on the first substrate SUB1, and the buffer layer BFL can be an inorganic layer. A semiconductor pattern can be disposed on the buffer layer BFL. The semiconductor pattern can include polycrystalline silicon, amorphous silicon, or metal oxide.

[0113] Semiconductor patterns can be doped with N-type or P-type dopants. Semiconductor patterns can include heavily doped and lightly doped regions. Heavily doped regions can have higher conductivity than lightly doped regions and essentially serve as the source and drain electrodes of a transistor (TR). Lightly doped regions can essentially correspond to the active portion (or channel) of the transistor.

[0114] The source region S, channel region A, and drain region D of transistor TR can be formed from a semiconductor pattern. A first insulating layer INS1 can be disposed on the semiconductor pattern. The gate electrode G (or control electrode) of transistor TR can be disposed on the first insulating layer INS1. A second insulating layer INS2 can be disposed on the gate electrode G. A third insulating layer INS3 can be disposed on the second insulating layer INS2.

[0115] The connecting electrode CNE can be disposed between the transistor TR and the light-emitting element OLED, and connects the transistor TR and the light-emitting element OLED. The connecting electrode CNE can include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1. The first connecting electrode CNE1 can be disposed on the third insulating layer INS3 and connected to the drain region D through a first contact hole CH1 defined in the first insulating layer INS1 to the third insulating layer INS3.

[0116] A fourth insulating layer INS4 may be disposed on the first connecting electrode CNE1. A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. A second connecting electrode CNE2 may be disposed on the fifth insulating layer INS5. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4 and the fifth insulating layer INS5.

[0117] The sixth insulating layer INS6 can be disposed on the second connection electrode CNE2. The layer from the buffer layer BFL to the sixth insulating layer INS6 can be defined as the circuit element layer DP-CL. The first insulating layer INS1 to the sixth insulating layer INS6 can each be an inorganic layer or an organic layer.

[0118] The first electrode AE ​​can be disposed on the sixth insulating layer INS6. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the third contact hole CH3 defined in the sixth insulating layer INS6. The pixel defining film PDL, which defines the opening PX_OP for exposing a predetermined portion of the first electrode AE, can be disposed on the first electrode AE ​​and the sixth insulating layer INS6.

[0119] The hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel defining film (PDL). The HCL can be commonly disposed in the light-emitting region (PA) and the non-light-emitting region (NPA). The HCL may include a hole transport layer and a hole injection layer.

[0120] The emission layer (EML) can be disposed on the hole control layer (HCL). The emission layer (EML) can be commonly disposed within the emitting region (PA) and the non-emitting region (NPA). The emission layer (EML) can comprise organic and / or inorganic materials. The emission layer (EML) can generate blue light.

[0121] The electronic control layer (ECL) can be disposed on the emitter layer (EML). The ECL may include an electron transport layer and an electron injection layer. The ECL can be commonly disposed in the emitting region (PA) and the non-emitting region (NPA).

[0122] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can also be disposed in the pixel PX.

[0123] The portions of the first electrode AE ​​and the second electrode CE that overlap with the opening PX_OP, the portions of the emitter layer EML that overlap with the opening PX_OP, the portions of the hole control layer HCL that overlap with the opening PX_OP, and the portions of the electron control layer ECL that overlap with the opening PX_OP can be defined as light-emitting elements OLEDs.

[0124] The layer containing the light-emitting OLED element can be defined as the display element layer DP-OLED. The circuit element layer DP-CL and the display element layer DP-OLED can be defined as the pixel layer PXL.

[0125] A thin-film encapsulation layer (TFE) can be disposed on the second electrode (CE) and can cover the pixel (PX). The TFE can include two inorganic layers and an organic layer between the inorganic layers. The inorganic layer protects the pixel (PX) from moisture / oxygen. The organic layer protects the pixel (PX) from foreign matter such as dust particles.

[0126] A first voltage ELVDD can be applied to the first electrode AE ​​via transistor TR, and a second voltage ELVSS, having a lower level than the first voltage ELVDD, can be applied to the second electrode CE. Holes and electrons injected into the emitter layer EML can recombine to form excitons, and when the excitons transition to the ground state, the light-emitting element OLED can emit light.

[0127] Figure 9 It shows the setting Figure 8 The cross-section of the light conversion portion on the pixel layer shown is presented as an example.

[0128] As an example, Figure 9 The first light-emitting region PA1, the second light-emitting region PA2, and the third light-emitting region PA3 are shown. Figure 8 The luminescent region PA shown can be any one of the first luminescent region PA1, the second luminescent region PA2, and the third luminescent region PA3. The first luminescent region PA1, the second luminescent region PA2, and the third luminescent region PA3 can be respectively connected to… Figure 6 The first pixel PX1, the second pixel PX2, and the third pixel PX3 shown correspond to each other. For ease of description, in Figure 9 No information was provided. Figure 8 The cross-sectional structure of the transistor TR and the light-emitting element OLED is shown, and the pixel layer PXL is shown as a single layer.

[0129] refer to Figure 9 The display device DD may include a light conversion portion (LCP) disposed on a thin-film encapsulation layer (TFE). The light conversion portion (LCP) can be attached to the thin-film encapsulation layer (TFE) via an adhesive layer (ADH).

[0130] The area between the first luminescent region PA1, the second luminescent region PA2, and the third luminescent region PA3 can be defined as the non-luminescent region NPA. The first luminescent region PA1, the second luminescent region PA2, and the third luminescent region PA3 can generate a first light L1. As an example, the first light L1 can be blue light.

[0131] The light conversion section LCP may include a second substrate SUB2, a first quantum dot layer QDL1 and a second quantum dot layer QDL2, a light transmission layer LTL, a first color filter CF1, a second color filter CF2 and a third color filter CF3, a black matrix BM, a separator layer SW, and a first insulating layer LC-IL1 and a second insulating layer LC-IL2. The first quantum dot layer QDL1 and the second quantum dot layer QDL2, the light transmission layer LTL, the first color filter CF1, the second color filter CF2 and the third color filter CF3, the black matrix BM, and the separator layer SW may be disposed between the second substrate SUB2 and the thin film encapsulation layer TFE.

[0132] The first color filter CF1, the second color filter CF2, and the third color filter CF3, as well as the black matrix BM, can be disposed under the second substrate SUB2. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can overlap with the first light-emitting region PA1, the second light-emitting region PA2, and the third light-emitting region PA3, respectively. The black matrix BM can overlap with the non-light-emitting region NPA.

[0133] The first color filter CF1 may overlap with the first luminous region PA1, the second color filter CF2 may overlap with the second luminous region PA2, and the third color filter CF3 may overlap with the third luminous region PA3. The first color filter CF1 may include a red color filter. The second color filter CF2 may include a green color filter. The third color filter CF3 may include a blue color filter.

[0134] The first insulating layer LC-IL1 can be disposed below the first color filter CF1, the second color filter CF2, the third color filter CF3, and the black matrix BM. The separator wall layer SW can be disposed below the first insulating layer LC-IL1.

[0135] The opening OP of the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL can be confined within the separator layer SW. The opening OP can correspond to the first emitting region PA1, the second emitting region PA2, and the third emitting region PA3. The separator layer SW can overlap with the non-emitting region NPA. The separator layer SW can be black, but its color is not limited to this.

[0136] The first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL can be disposed below the first insulating layer LC-IL1. The first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL can be disposed in the opening OP.

[0137] The first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL can overlap with the first emitting region PA1, the second emitting region PA2, and the third emitting region PA3, respectively. The first quantum dot layer QDL1 can overlap with the first emitting region PA1, the second quantum dot layer QDL2 can overlap with the second emitting region PA2, and the light-transmitting layer LTL can overlap with the third emitting region PA3.

[0138] The first light L1 generated in the first emitting region PA1, the second emitting region PA2, and the third emitting region PA3 can be provided to the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL. The first light L1 generated in the first emitting region PA1 can be provided to the first quantum dot layer QDL1, and the first light L1 generated in the second emitting region PA2 can be provided to the second quantum dot layer QDL2. The first light L1 generated in the third emitting region PA3 can be provided to the light-transmitting layer LTL.

[0139] The first quantum dot layer QDL1 can convert a first light L1 into a second light L2. The second quantum dot layer QDL2 can convert the first light L1 into a third light L3. As an example, the second light L2 can be red light, and the third light L3 can be green light. The first quantum dot layer QDL1 may include a first quantum dot (not shown), and the second quantum dot layer QDL2 may include a second quantum dot (not shown). The light transmission layer LTL may include light scattering particles (not shown) for scattering light.

[0140] The first quantum dot can convert a first light L1 with a blue wavelength band into a second light L2 with a red wavelength band. The second quantum dot can convert the first light L1 with a blue wavelength band into a third light L3 with a green wavelength band. The first and second quantum dots can scatter the second light L2 and the third light L3. The light transmission layer LTL can transmit the first light L1 without performing the light conversion operation. The light transmission layer LTL can scatter the first light L1 through light scattering particles and output scattered light.

[0141] The first quantum dot layer QDL1 can output a second light L2, the second quantum dot layer QDL2 can output a third light L3, and the light transmission layer LTL can output a first light L1. Therefore, since the second light L2, the third light L3, and the first light L1 are displayed in red, green, and blue respectively, a predetermined image can be displayed.

[0142] A portion of the first light L1 can pass through the first quantum dot layer QDL1 without being converted by the first quantum dot light and can be provided to the first color filter CF1. That is, there may be a portion of the first light L1 that is not converted into the second light L2 because it does not come into contact with the first quantum dot. The first color filter CF1 can block light of different colors. The first light L1 that is not converted at the first quantum dot layer QDL1 can be blocked at the first color filter CF1 with a red color filter, and therefore may not be output upwards.

[0143] A portion of the first light L1 can pass through the second quantum dot layer QDL2 without being converted by the second quantum dot light and can be provided to the second color filter CF2. That is, there may be a portion of the first light L1 that is not converted into the third light L3 because it does not come into contact with the second quantum dots. The second color filter CF2 can block light of different colors. The first light L1 that is not converted at the second quantum dot layer QDL2 can be blocked at the second color filter CF2, which has a green color filter, and therefore may not be output upwards.

[0144] External light can be directed toward the display device DD. When the external light is reflected on the display panel DP and provided back to the external user, the user may see the external light as if it were light reflected from a mirror.

[0145] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent the reflection of external light. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can filter external light with red, green, and blue colors, respectively. That is, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can filter external light with the same color as the second light L2, the third light L3, and the first light L1, respectively. In this case, the external light can be hidden from the user's view.

[0146] The black matrix BM can block unwanted light in the non-emitting region NPA. The black-colored separator layer SW can also block unwanted light in the non-emitting region NPA, similar to the function of the black matrix BM.

[0147] Figure 10 Is applied to Figure 5 The timing diagram of the scan signal for the scan line shown is shown.

[0148] refer to Figure 10 Scan drive SDV (such as Figure 5(As shown) Multiple scan signals SC1 to SCm and SS1 to SSm can be generated, and these scan signals SC1 to SCm and SS1 to SSm can be applied to pixel PX through scan lines SL1 to SLm. The scan signals SC1 to SCm and SS1 to SSm can be output sequentially. Although not shown, Figure 5 The scan lines SL1 to SLm shown may each include, as follows: Figure 7 The i-th scan line SLi is shown as the write scan line and the sampling scan line.

[0149] The scan signals SC1 to SCm and SS1 to SSm may include multiple write scan signals SC1 to SCm and multiple sample scan signals SS1 to SSm. Figure 7 The i-th write scan signal SCi shown can be one of the write scan signals SC1 to SCm, and the i-th sample scan signal SSi can be one of the sample scan signals SS1 to SSm.

[0150] The display device DD can display an image during the display on cycle D-ON. The display on cycle D-ON can include the display cycle DSP and the blanking cycle BP that follows the display cycle DSP.

[0151] During the display cycle DSP, scan signals SC1 to SCm and SS1 to SSm can be output sequentially. During the display cycle DSP, write scan signals SC1 to SCm and sample scan signals SS1 to SSm can be output sequentially. During the display cycle DSP, write scan signals SC1 to SCm and sample scan signals SS1 to SSm that are in the same order can be applied to pixel PX at the same timing.

[0152] In the following description, the active state of a signal may be defined as a high level of the signal, and the deactivated state of a signal may be defined as a low level of the signal.

[0153] During the display cycle DSP, the activation period of each of the scan signals SC1 to SCm and SS1 to SSm can have a 2H time period. During the display cycle DSP, the scan signals SC1 to SCm and SS1 to SSm can overlap each other for a 1H time period. For example, and without limitation, scan signals SC1 and SS1 can overlap with scan signals SC2 and SS2 for a 1H time period, and scan signals SC2 and SS2 can overlap with scan signals SC3 and SS3 for a 1H time period, and so on.

[0154] For example, during the display cycle DSP, the (i+1)th scan signal can partially overlap with the ith scan signal. During the display cycle DSP, the (i+1)th write scan signal can overlap with the ith write scan signal for a period of 1H. Furthermore, during the display cycle DSP, the (i+1)th sampled scan signal can overlap with the ith sampled scan signal for a period of 1H.

[0155] During the blanking period BP, the scan driver SDV can select a pixel PX set in any row, and either a write scan signal or a sample scan signal can be applied to the selected pixel PX.

[0156] As an example, the i-th write scan signal SCi can be applied to the pixel PX connected to the i-th write scan line SCLi (see [link to documentation]). Figure 6 The i-th sampled scan signal SSi can be applied to the pixel PX connected to the i-th sampled scan line SSLi.

[0157] The blanking period BP may include a first time interval TP1, a second time interval TP2, and a third time interval TP3 that are set consecutively. For example, the first time interval TP1, the second time interval TP2, and the third time interval TP3 of the blanking period BP may occur consecutively. Here, aspects of this disclosure are not limited to a specific order of the time intervals in the blanking period BP, and specific numbers are simply provided to describe the elements and are not intended to describe the order of operations. The i-th scan signals SCi and SSi may be applied to the pixel PX connected to the i-th scan line SLi during the first time interval TP1, the second time interval TP2, and the third time interval TP3.

[0158] The i-th write scan signal SCi can be activated during the first time period TP1 and the third time period TP3, and deactivated during the second time period TP2. The i-th sample scan signal SSi can be activated during the first time period TP1, the second time period TP2, and the third time period TP3.

[0159] In an embodiment of the present invention, defective pixels can be detected. During the blanking period (BP), a pixel PX can be selected in the row preceding the row in which the defective pixel is located, and a write scan signal and a sampling scan signal can be applied to the selected pixel PX. This operation will be described in detail below.

[0160] Figure 11 It is used to describe pixels in Figure 10 The diagram shown illustrates the operations within the display cycle. Figures 12A to 12C It is used to describe pixels in Figure 10 The diagram shows the operations in the first, second, and third time periods.

[0161] In the following text, the settings in the display cycle DSP will be described as an example. Figure 7 The operation of the i-th pixel PXi in the i-th row shown is illustrated, but other pixels PX, which are not shown, can be operated in the same way as the i-th pixel PXi.

[0162] refer to Figure 10 and Figure 11 During the program period of the display cycle DSP, the activated i-th write scan signal SCi and the i-th sample scan signal SSi can be applied to the i-th pixel PXi. The second transistor T2 can be turned on in response to the i-th write scan signal SCi, and the third transistor T3 can be turned on in response to the i-th sample scan signal SSi.

[0163] During the display cycle DSP, the j-th data line DLj can receive the data voltage Vd. The data voltage Vd can be applied to the control electrode (or gate electrode) of the first transistor T1 through the j-th data line DLj.

[0164] During the display cycle DSP, the h-th reference line RLh can receive the reference voltage Vr. The reference voltage Vr can be applied to the second electrode (or source electrode) of the first transistor T1 through the h-th reference line RLh.

[0165] The control electrode of the first transistor T1 can be connected to the first node N1, and the second electrode of the first transistor T1 can be connected to the second node N2. Therefore, the voltage between the first node N1 and the second node N2 can be set as the difference between the data voltage Vd and the reference voltage Vr.

[0166] The charge corresponding to the difference between the data voltage Vd and the reference voltage Vr can be stored in the i-th capacitor CSTi. Therefore, during the program period, the voltage between the first node N1 and the second node N2 can be set according to the desired pixel current. The voltage between the first node N1 and the second node N2 can be defined as the gate-source voltage Vgs.

[0167] During the transmit period following the program phase, the i-th write scan signal SCi and the i-th sample scan signal SSi can be deactivated, and the second transistor T2 and the third transistor T3 can be turned off. The voltage between the first node N1 and the second node N2 can be maintained by the i-th capacitor CSTi.

[0168] Because the voltage between the first node N1 and the second node N2 is greater than the threshold voltage of the first transistor T1, pixel current can flow in the first transistor T1 during the emission period. During the emission period, the potential of the first node N1 and the potential of the second node N2 can increase due to the pixel current, while the voltage between the first node N1 and the second node N2 remains constant. When the potential of the second node N2 rises to the operating point level of the i-th light-emitting element OLEDi, the i-th light-emitting element OLEDi can emit light.

[0169] In the display cycle DSP, scan signals SC1 to SCm and SS1 to SSm can be sequentially applied to pixel PX, and pixel PX can operate like the i-th pixel PXi.

[0170] refer to Figure 10 and Figure 12A During the first time period TP1, the activated i-th write scan signal SCi and i-th sample scan signal SSi can be applied to the selected i-th pixel PXi. The second transistor T2 and the third transistor T3 can be turned on by the i-th write scan signal SCi and the i-th sample scan signal SSi.

[0171] During the first time period TP1, the j-th data line DLj can receive the data voltage Vs for sensing. The data voltage Vs for sensing can be applied to the control electrode of the first transistor T1 through the j-th data line DLj.

[0172] During the first time period TP1, the h-th reference line RLh can receive the reference voltage Vr. The reference voltage Vr can be supplied to the second electrode of the first transistor T1 through the h-th reference line RLh. Therefore, the voltage between the first node N1 and the second node N2 can be set to match the desired sensing pixel current.

[0173] refer to Figure 10 and Figure 12B During the second time period TP2, the i-th write scan signal SCi can be deactivated, while the i-th sampling scan signal SSi can remain active. The second transistor T2 can be turned off, and the third transistor T3 can remain on.

[0174] The gate-source voltage Vgs of the first transistor T1 can be sensed based on the data voltage Vs and the reference voltage Vr used for sensing. The sensed gate-source voltage Vgs can be defined as the sensed voltage Vsn. The sensed voltage Vsn can be provided to the data driver DDV through the h-th reference line RLh. The sensed voltage Vsn can be provided to the timing controller T-CON through the data driver DDV. The driving characteristics of the i-th pixel PXi can be sensed using the gate-source voltage Vgs.

[0175] The sensed gate-source voltage Vgs can be substantially correlated with the sensed pixel current flowing through the first transistor T1. The sensed pixel current can be calculated using the sensed gate-source voltage Vgs.

[0176] refer to Figure 10 and Figure 12C During the third time period TP3, the i-th write scan signal SCi can be activated, and the i-th sample scan signal SSi can remain activated. The second transistor T2 can be turned on, and the third transistor T3 can remain turned on.

[0177] During the third time period TP3, the j-th data line DLj can receive the recovery data voltage Vrec, and the h-th reference line RLh can receive the reference voltage Vr. The recovery data voltage Vrec can be applied to the control electrode of the first transistor T1, and the reference voltage Vr can be applied to the second electrode of the first transistor T1. The recovery data voltage Vrec can have a level substantially the same as the reference voltage Vr. Therefore, during the third time period TP3, the i-th pixel PXi can be initialized and can not emit light.

[0178] Figure 13 This is a diagram illustrating, as an example, the configuration of a cross-section of a defective pixel in which a defect occurs.

[0179] refer to Figure 13 The (i+1)th pixel PXi+1 can be defined as pixel PX disposed in the (i+1)th row. The first electrode AE ​​and the second electrode CE can be short-circuited in the (i+1)th pixel PXi+1. For example, when a foreign object M is disposed on the sixth insulating layer INS6, the portion of the first electrode AE ​​disposed on the foreign object M may protrude upwards and may contact the second electrode CE. In this case, the (i+1)th pixel PXi+1 may include a short-circuit resistance Rs formed due to a short circuit between a portion of the first electrode AE ​​and a portion of the second electrode CE.

[0180] The (i+1)th pixel PXi+1, including the short-circuit resistance Rs, can be defined as a defective pixel. A defective pixel can affect the operation of adjacent pixels.

[0181] Figure 14 It is a circuit diagram used to describe the operation of the i-th pixel set in the i-th row and the i+1-th pixel set in the i+1-th row during the display cycle. Figure 15 Is applied to Figure 14 The timing diagrams of the i-th and i+1-th scan signals of the i-th and i+1-th pixels are shown.

[0182] As an example, Figure 14 The (i+1)th pixel PXi+1 shown can be Figure 13 The defective pixel shown.

[0183] refer to Figure 14 The (i+1)th pixel PXi+1 can be connected to the j-th data line DLj, the h-th reference line RLh, the (i+1)th write scan line SCLi+1, and the (i+1)th sampling scan line SSLi+1. The (i+1)th write scan line SCLi+1 can receive the (i+1)th write scan signal SCi+1. The (i+1)th sampling scan line SSLi+1 can receive the (i+1)th sampling scan signal SSi+1.

[0184] The (i+1)th pixel PXi+1 may include a (1-1)th transistor T1-1, a (2-1)th transistor T2-1, a (3-1)th transistor T3-1, an (i+1)th capacitor CSTi+1, an (i+1)th light-emitting element OLEDi+1, and a short-circuit resistor Rs. Except for the short-circuit resistor Rs, the (i+1)th pixel PXi+1 may have the same circuit configuration as the ith pixel PXi. A brief description of the connection configuration between the elements of the (i+1)th pixel PXi+1 is as follows.

[0185] Transistor T1-1 (1-1) may include a first electrode connected to the first power line PL1, a control electrode connected to the first node N1-1, and a second electrode connected to the second node N2-1. Transistor T2-1 (2-1) may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1-1, and a control electrode connected to the (i+1)-th write scan line SCLi+1. Transistor T3-1 (3-1) may include a first electrode connected to the h-th reference line RLh, a second electrode connected to the second node N2-1, and a control electrode connected to the (i+1)-th sampling scan line SSLi+1.

[0186] The (i+1)th light-emitting element OLEDi+1 may include an anode connected to the (2-1)th node N2-1 and a cathode connected to the second power line PL2. The (i+1)th capacitor CSTi+1 may include a first electrode connected to the (1-1)th node N1-1 and a second electrode connected to the (2-1)th node N2-1. As described above, the short-circuit resistance Rs may be formed due to a short circuit between the first electrode AE ​​and the second electrode CE.

[0187] refer to Figure 14 and Figure 15 During the display cycle DSP, the i-th scan signals SCi and SSi, and the (i+1)-th scan signals SCi+1 and SSi+1 can be sequentially applied to the i-th pixel PXi and the (i+1)-th pixel PXi+1, respectively. As described above, the (i+1)-th scan signals SCi+1 and SSi+1 can partially overlap with the i-th scan signals SCi and SSi.

[0188] According to the reference Figure 11 The described operation, during the display cycle DSP, allows the i-th pixel PXi to receive a data voltage Vd and a reference voltage Vr in response to the i-th scan signal SCi and SSi. For example, during the display cycle DSP, the i-th pixel PXi can receive a data voltage Vd in response to the i-th write scan signal SCi and a reference voltage Vr in response to the i-th sample scan signal SSi. Therefore, as referenced... Figure 11 As described, the i-th pixel PXi can emit light.

[0189] Similar to the i-th pixel PXi, during the display cycle DSP, the (i+1)-th pixel PXi+1 can also receive the data voltage Vd and the reference voltage Vr in response to the (i+1)-th scan signals SCi+1 and SSi+1. The (i+1)-th scan signals SCi+1 and SSi+1 can include the (i+1)-th write scan signal SCi+1 and the (i+1)-th sample scan signal SSi+1. The (i+1)-th write scan signal SCi+1 and the (i+1)-th sample scan signal SSi+1 can be applied to the (i+1)-th pixel PXi+1 in the same timing.

[0190] The (i+1)th pixel PXi+1 can receive the data voltage Vd in response to the (i+1)th write scan signal SCi+1 and the reference voltage Vr in response to the (i+1)th sampling scan signal SSi+1. However, since the driving current flows to the short-circuit resistor Rs in the (i+1)th pixel PXi+1, the (i+1)th light-emitting element OLEDi+1 may not emit light.

[0191] The period during which the (i+1)th scan signals SCi+1 and SSi+1 overlap with the i-th scan signals SCi and SSi can be defined as the overlap period. When the i-th pixel PXi is driven, the (i+1)th sampled scan signal SSi+1 can be applied to the (i+1)th pixel PXi+1 during the overlap period, and the (3-1)th transistor T3-1 can be turned on. The second voltage ELVSS can be applied to the h-th reference line RLh through the short-circuit resistor Rs and the turned-on (3-1)th transistor T3-1.

[0192] The second voltage ELVSS can have a lower voltage level than the reference voltage Vr during the blanking period BP. The second voltage ELVSS can be applied to the h-th reference line RLh, and the level of the reference voltage Vr can be changed. For example, the level of the reference voltage Vr can be reduced to the level of the second voltage ELVSS. That is, the level of the reference voltage Vr can be reduced to the level of the second voltage ELVSS due to the (i+1)-th pixel PXi+1 including the short-circuit resistor Rs.

[0193] Therefore, a voltage drop can occur at the second node N2, and the gate-source voltage Vgs of the first transistor T1 can increase. Because the gate-source voltage Vgs of the first transistor T1 increases, the i-th light-emitting element OLEDi can emit light with a brightness higher than normal.

[0194] The i-th light-emitting element OLEDi can emit light with a brightness higher than normal and can be considered a bright pixel. In this case, the brightness difference between the (i+1)-th light-emitting element OLEDi+1 that does not emit light and the i-th light-emitting element OLEDi that emits light with high brightness may increase, and this brightness difference may be observed by the user. Figure 6 When the first pixel PX1, the second pixel PX2, and the third pixel PX3 shown are pixels set in the i-th row, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be regarded as bright pixels.

[0195] In an embodiment of the present invention, the increase in brightness of the i-th light-emitting element OLEDi can be easily detected during the blanking period BP, and this operation will be described in detail below.

[0196] Figure 16 This is a timing diagram of the i-th scan signal applied to the i-th pixel and the sense voltage output through the h-th reference line during the blanking period, assuming the (i+1)-th pixel is a normal pixel.

[0197] refer to Figure 16 According to reference Figures 12A to 12C The described operation involves the sensing voltage Vsn sensed in the i-th pixel PXi being output via the h-th reference line RLh. As an example, the sensing voltage Vsn can be charged to a first voltage level VL1 and then output.

[0198] Figure 17A and Figure 17B It is a diagram used to describe the operation of the i-th pixel and the i+1-th pixel in the first and second time periods when the i+1-th pixel is a defective pixel. Figure 18 This is a timing diagram of the i-th scan signal applied to the i-th pixel, the i+1-th scan signal applied to the i+1-th pixel, and the sensing voltage during the blanking period, when the i+1-th pixel is a defective pixel.

[0199] As an example, Figure 18 It is shown in dashed lines Figure 16 The sensing voltage Vsn is shown in the figure.

[0200] refer to Figure 17A , Figure 17B and Figure 18During the first time period TP1, the second time period TP2 and the third time period TP3, the i-th scan signal SCi and SSi can be applied to the i-th pixel PXi, and the (i+1)-th scan signal SCi+1 and SSi+1 can be applied to the (i+1)-th pixel PXi+1.

[0201] Specifically, the i-th write scan signal SCi can be activated and applied to the i-th pixel PXi during the first time period TP1 and the third time period TP3. The i-th sample scan signal SSi can be applied to the i-th pixel PXi during the first time period TP1, the second time period TP2, and the third time period TP3. The (i+1)-th sample scan signal SSi+1 of the (i+1)-th scan signals SCi+1 and SSi+1 can be activated and applied to the (i+1)-th pixel PXi+1 during the first time period TP1.

[0202] refer to Figure 17A and Figure 18 The i-th pixel PXi can receive the data voltage Vs for sensing in response to the i-th write scan signal SCi during the first time period TP1, and receive the reference voltage Vr in response to the i-th sampling scan signal SSi.

[0203] The (i+1)th pixel PXi+1 can be connected to the h-th reference line RLh during the first time period TP1 via the (i+1)th sampled scan signal SSi+1 via the (3-1)th transistor T3-1. The short-circuit resistor Rs can be connected to the h-th reference line RLh via the (3-1)th transistor T3-1.

[0204] The second voltage ELVSS can be applied to the h-th reference line RLh through the short-circuit resistor Rs and the turned-on 3-1 transistor T3-1. Therefore, the level of the reference voltage Vr can be changed and reduced to the level of the second voltage ELVSS. That is, the level of the reference voltage Vr can be changed by the (i+1)th pixel PXi+1 during the first time period TP1, and specifically, the level of the reference voltage Vr can be reduced. Because the level of the reference voltage Vr is reduced, it is related to... Figure 14 The operation is similar in the display cycle DSP, where the gate-source voltage Vgs of the first transistor T1 can be increased.

[0205] refer to Figure 17B and Figure 18 During the second time period TP2, the sensing voltage Vsn sensed in the i-th pixel PXi based on the data voltage Vs used for sensing, the reference voltage Vr, and the short-circuit resistance Rs can be output through the h-th reference line RLh. As the gate-source voltage Vgs of the first transistor T1 increases, the sensing voltage Vsn can be charged to a second voltage level VL2, which is higher than the first voltage level VL1, and then output.

[0206] For reference Figure 14 As described, during the display cycle DSP, according to the second voltage ELVSS applied to the h-th reference line RLh through the short-circuit resistor Rs, the i-th pixel PXi can emit light with a brightness higher than normal brightness. In an embodiment of the inventive concept, during the blanking cycle BP for sensing the characteristics of the i-th pixel PXi, the (i+1)-th pixel PXi+1 can be connected to the h-th reference line RLh and can output a sensing voltage Vsn whose voltage level is increased due to the influence of the short-circuit resistor Rs.

[0207] In the display cycle DSP, the difference ΔV between the first voltage level VL1 and the second voltage level VL2 can substantially correspond to the increase in brightness of the i-th pixel PXi based on the influence of the (i+1)-th pixel PXi+1 as a defective pixel.

[0208] The sensed voltage Vsn can be supplied to the data driver DDV via the h-th reference line RLh during the second time period TP2. The sensed voltage Vsn can then be supplied to the timing controller T-CON via the data driver DDV.

[0209] The timing controller T-CON can compensate for the data voltage Vd applied to the i-th pixel PXi based on the sensed voltage Vsn. For example, the timing controller T-CON can reduce the level of the data voltage Vd by a value corresponding to the difference between the first voltage level VL1 and the second voltage level VL2, and output the data voltage Vd. Therefore, the brightness of the i-th pixel PXi can be reduced to a normal level. Thus, the i-th pixel PXi can no longer be considered a bright spot. Furthermore, the brightness difference between the i-th pixel PXi and the (i+1)-th pixel PXi+1 can be reduced.

[0210] The (i+1)th write scan signal SCi+1 can be deactivated during the first time period TP1 to the third time period TP3. The (i+1)th sample scan signal SSi+1 can be deactivated during the second time period TP2 and the third time period TP3.

[0211] Figure 19 Is Figure 10 The diagram shows the timing of the signals in the display off cycle D-OFF, preceding the display on cycle D-ON. For clarity, when discussing... Figure 19 The display shows the time periods P1-P6 that occur during the D-OFF cycle and in Figure 10When the time periods TP1-TP3 occur during the display on cycle D-ON, the time periods P1 to P6 occurring during the display off cycle D-OFF can be referred to as the fourth to ninth time periods. For example, the first time period is the first time period in the display on cycle D-ON, and the fourth time period is the first time period of the second sensing period in the display off cycle D-OFF; the second time period is the second time period occurring during the display on cycle D-ON, and the fifth time period is the second time period occurring during the second sensing period of the display off cycle D-OFF, and so on.

[0212] refer to Figure 19 The display device DD can not display an image during the display off cycle D-OFF. However, power can be supplied to the display device DD, and sensing operations can be performed on the pixels PX of the display device DD.

[0213] The display off period D-OFF can include a first sensing period SNP1 and a second sensing period SNP2. Scan signals SC1 to SCm and SS1 to SSm can be output sequentially during the first sensing period SNP1.

[0214] Referring to the above example description of the i-th pixel PXi and the (i+1)-th pixel PXi+1, the i-th scan signals SCi and SSi, and the (i+1)-th scan signals SCi+1 and SSi+1, can be sequentially applied to the i-th pixel PXi and the (i+1)-th pixel PXi+1, respectively, during the first sensing period SNP1. The falling edges of the i-th scan signals SCi and SSi can overlap with the rising edges of the (i+1)-th scan signals SCi+1 and SSi+1. Figure 10 The timing diagram shown is different; states where only the falling and rising edges overlap can be defined as non-overlapping states.

[0215] The i-th write scan signal SCi and the i-th sample scan signal SSi can be applied to the i-th pixel PXi in the same timing during the first sensing period SNP1. The (i+1)-th write scan signal SCi+1 and the (i+1)-th sample scan signal SSi+1 can be applied to the (i+1)-th pixel PXi+1 in the same timing during the first sensing period SNP1.

[0216] Figure 10 The scan signals shown can be sequentially applied to pixels PX in all rows during the second sensing period SNP2. Specifically, the second sensing period SNP2 can include consecutive first period P1, second period P2, third period P3, fourth period P4, fifth period P5, and sixth period P6 associated with the i-th scan signals SCi and SSi and the (i+1)-th scan signals SCi+1 and SSi+1.

[0217] The timing of the scan signals applied to the i-th pixel PXi and the (i+1)-th pixel PXi+1 when i=1 will be described as an example below.

[0218] The i-th write scan signal SCi can be activated and applied to the i-th pixel PXi during the first time period P1 and the third time period P3. The i-th sample scan signal SSi can be activated and applied to the i-th pixel PXi during the first time period P1 to the third time period P3.

[0219] The (i+1)th write scan signal SCi+1 can be activated and applied to the (i+1)th pixel PXi+1 during the fourth time period P4 and the sixth time period P6. The (i+1)th sample scan signal SSi+1 can be activated and applied to the (i+1)th pixel PXi+1 during the first time period P1 and the fourth time period P4 to the sixth time period P6.

[0220] Figure 20 It is used to describe the i-th pixel and the (i+1)-th pixel in Figure 19 The diagram shows the operation during the first sensing period. Figure 21 It is used to describe the i-th pixel and the (i+1)-th pixel in Figure 19 The diagram shows the operation during the second sensing period.

[0221] refer to Figure 20 During the first sensing period SNP1, the i-th pixel PXi can receive the sensing voltage Vss and the reference voltage Vr via the j-th data line DLj and the h-th reference line RLh in response to the i-th scan signals SCi and SSi. The sensing voltage Vss can have a different voltage level than the sensing data voltage Vs.

[0222] The sensing voltage Vss can be applied to the first node N1, and the reference voltage Vr can be applied to the second node N2. The gate-source voltage Vgs of the first transistor T1 of the i-th pixel PXi can be sensed based on the sensing voltage Vss and the reference voltage Vr.

[0223] During the first sensing period SNP1, the (i+1)th pixel PXi+1 can receive the voltage Vss and the reference voltage Vr for sensing via the (i+1)th scan signal SCI+1 and SSi+1 through the j-th data line DLj and the h-th reference line RLh in response to the (i+1)th scan signal SCI+1 and SSi+1.

[0224] The sensing voltage Vss can be applied to node 1-1 N1-1, and the reference voltage Vr can be applied to node 2-1 N2-1. However, a second voltage ELVSS can be connected to the h-th reference line RLh via a short-circuit resistor Rs. Since the second voltage ELVSS is applied to the h-th reference line RLh, the level of the reference voltage Vr can be changed due to the influence of the second voltage ELVSS. Therefore, the voltage sensed in pixel i+1 PXi+1 can be outside the normal sensing voltage level.

[0225] In this scenario, the timing controller T-CON can identify the (i+1)th pixel PXi+1 as a defective pixel. Therefore, the position of the defective pixel can be detected. Since the position of the defective pixel is detected, the i-th pixel PXi can be selected in the row preceding the row of the (i+1)th pixel PXi+1 identified as the defective pixel in the blanking period BP described above, and scan signals SCi and SSi can be applied to the i-th pixel PXi.

[0226] refer to Figure 21 During the first time period P1, as in reference Figure 12A In the first time period TP1 described, the i-th pixel PXi can receive the data voltage Vs and reference voltage Vr for sensing in response to the i-th scan signals SCi and SSi.

[0227] Subsequently, with reference Figure 12B The operation in the second time period TP2 is similar. During the second time period P2, a sensing operation can be performed on the i-th pixel PXi, and a sensing voltage Vsn can be output. Figure 21 The sensing operation during the second time period P2 is essentially illustrated. Subsequently, during the third time period P3, the recovery data voltage Vrec described above can be applied to the i-th pixel PXi.

[0228] Similar to the operation in the first time period P1, during the fourth time period P4, the (i+1)th pixel PXi+1 can receive the data voltage Vs and reference voltage Vr for sensing in response to the (i+1)th scan signals SCi+1 and SSi+1. Similar to the operation in the second time period P2, during the fifth time period P5, a sensing operation can be performed on the (i+1)th pixel PXi+1, and similar to the operation in the second time period P2, during the sixth time period P6, the recovery data voltage Vrec described above can be applied to the (i+1)th pixel PXi+1. This operation can be performed on pixels up to PX set in the last row.

[0229] Therefore, with reference Figure 10 as well as Figures 12A to 12CThe operation described is similar, and the sensed voltage Vsn sensed in pixel PX can be output. Therefore, sensing operations can be performed on all pixels PX, and the driving characteristics of all pixels PX can be sensed.

[0230] refer to Figure 17A , Figure 17B and Figure 18 The described sensing operations can be performed additionally during the second sensing period SNP2. (See reference...) Figure 17A , Figure 17B and Figure 18 As described, the (i+1)th sampling scan signal SSi+1 can be applied to the (i+1)th pixel PXi+1 during the first time period P1. Therefore, the increase in the brightness of the i-th pixel PXi due to the influence of the short-circuit resistance Rs can be detected.

[0231] The timing controller T-CON can compensate for the data voltage Vd applied to the i-th pixel PXi by using the average of the sensing voltage Vsn detected in the second sensing period SNP2 and the blanking period BP.

[0232] If the (i+1)th pixel PXi+1 is not a defective pixel, a short-circuit resistance Rs can be avoided. Therefore, even if the (i+1)th sampling scan signal SSi+1 is applied to the (i+1)th pixel PXi+1 during the first time period P1, the second power line PL2 can be left unconnected to the h-th reference line RLh if the (i+1)th pixel PXi+1 is not a defective pixel.

[0233] If the (i+1)th pixel PXi+1 is not a defective pixel, since the second voltage ELVSS is not applied to the h-th reference line RLh, the sensing operation can be performed based on the data voltage Vs used for sensing and the normal reference voltage Vr.

[0234] Figure 22 This is a graph showing the test results obtained by testing the brightness changes in the defective pixel and the previous pixel while changing the short-circuit resistance of the defective pixel.

[0235] refer to Figure 22 The EL short-circuit resistance can represent the short-circuit resistance Rs described above. A low EL short-circuit resistance indicates a high degree of short circuit, and a high EL short-circuit resistance indicates a low degree of short circuit. When the anode and cathode are essentially not short-circuited, the EL short-circuit resistance can be significantly high, and a state where the EL short-circuit resistance is equal to or higher than approximately 1.E+10 can represent a state where the anode and cathode are essentially not short-circuited.

[0236] The code value Code can be a digital value related to the sensed voltage Vsn. The timing controller T-CON can compensate for the data voltage Vd based on the code value Code. When the sensed voltage Vsn is in a normal state, the code value Code can be 0.

[0237] The luminance ratio represents the ratio of the luminance of the i-th pixel PXi to that of the (i+1)-th pixel PXi+1. When the luminance ratio of the i-th pixel PXi is 100%, the i-th pixel PXi can have normal luminance. When the luminance ratio of the (i+1)-th pixel PXi+1 is 0%, the (i+1)-th pixel PXi+1 can not emit light and can be defined as a defective pixel.

[0238] When the sensing voltage Vsn sensed in the i-th pixel PXi increases according to the (i+1)-th pixel PXi+1, which is a defective pixel, the code value Code can be greater than 0. When the code value Code is approximately greater than 0, the luminance ratio of the i-th pixel PXi can be greater than 100%, and the i-th pixel PXi can be a bright pixel. The difference ΔCode between the code value Code (which is 0) and the code value Code (which is greater than 0) can correspond to the difference ΔV between the first voltage level VL1 and the second voltage level VL2 described above.

[0239] The timing controller T-CON can reduce the data voltage Vd to the value corresponding to the difference ΔCode between the code value Code (which is 0) and the code value Code (which is greater than 0), and then output the data voltage Vd.

[0240] Figure 23 This is a flowchart describing a driving method for a display device according to an embodiment of the present invention.

[0241] The above describes the detailed operation, and the following will refer to... Figure 23 The flowchart shown briefly describes the driving method of the display device DD.

[0242] refer to Figure 23 In step S100, during the display cycle DSP, the data voltage Vd and the reference voltage Vr can be applied to the i-th pixel PXi located in the i-th row synchronously with the i-th scan signals SCi and SSi. In step S200, during the display cycle DSP, the data voltage Vd and the reference voltage Vr can be applied to the (i+1)-th pixel PXi+1 located in the (i+1)-th row synchronously with the (i+1)-th scan signals SCi+1 and SSi+1.

[0243] In step S300, during the first time period TP1 of the blanking period BP following the display period DSP, the data voltage Vs used for sensing can be applied to the i-th pixel PXi synchronously with the i-th write scan signal SCi. In step S400, during the first time period TP1, the reference voltage Vr can be applied to the i-th pixel PXi synchronously with the i-th sampling scan signal SSi.

[0244] In step S500, during the first time period TP1, the (i+1)th pixel PXi+1 can be connected to the h-th reference line RLh synchronously with the (i+1)th sampling scan signal SSi+1. Therefore, the level of the reference voltage Vr can be reduced due to the (i+1)th pixel PXi+1 during the first time period TP1. In step S600, during the second time period TP2 after the first time period TP1, the sensing voltage Vsn sensed in the i-th pixel PXi based on the data voltage Vs used for sensing, the reference voltage Vr, and the short-circuit resistance Rs can be output through the h-th reference line RLh.

[0245] In step S700, the data voltage Vd applied to the i-th pixel PXi can be compensated based on the sensing voltage Vsn output through the h-th reference line RLh. In step S800, during the third time period TP3 following the second time period TP2, the recovery data voltage Vrec can be applied to the i-th pixel PXi synchronously with the i-th write scan signal SCi. Furthermore, in step S900, during the third time period TP3, the reference voltage Vr can be applied to the i-th pixel PXi synchronously with the i-th sampling scan signal SSi.

[0246] According to an embodiment of the present invention, when the i-th scan signal is applied to the i-th pixel disposed in the i-th row during the blanking period, the (i+1)-th scan signal can be applied to the (i+1)-th pixel disposed in the (i+1)-th row and which is a defective pixel, and the voltage drop of the (i+1)-th pixel can be reflected in the reference voltage applied to the i-th pixel. When the level of the reference voltage decreases due to the influence of the (i+1)-th pixel, the sensing voltage sensed in the i-th pixel can increase the decrease in level.

[0247] The increase in sensing voltage can substantially correspond to the increase in brightness of the i-th pixel. The data voltage applied to the i-th pixel can be compensated based on the increase in sensing voltage. Therefore, the brightness of the i-th pixel can be compensated, and the i-th pixel can emit light with normal brightness.

[0248] The embodiments of the present invention have been described above with reference to the present invention concept. However, those skilled in the art or those with ordinary skills will understand that various modifications and changes can be made to the present invention concept, as long as such modifications and changes do not depart from the spirit and technical scope of the present invention concept set forth in the claims.

[0249] Therefore, the technical scope of this invention is not limited to what is stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: The i-th pixel is located in the i-th row and receives data voltage and reference voltage in response to the i-th scan signal during the display cycle. as well as The (i+1)th pixel is located in the (i+1)th row and, during the display cycle, receives the data voltage and the reference voltage in response to the (i+1)th scan signal. The blanking period following the display period includes a first time period, a second time period, and a third time period, wherein the first time period, the second time period, and the third time period are consecutive. The i-th scan signal is applied to the i-th pixel during the first time period to the third time period, and the (i+1)-th scan signal is applied to the (i+1)-th pixel during the first time period. During the first time period, the i-th pixel receives a data voltage for sensing and a reference voltage, the level of which is changed by the (i+1)-th pixel, where i is a natural number greater than 0.

2. The display device according to claim 1, wherein, During the display cycle, the i-th scan signal and the (i+1)-th scan signal are sequentially applied to the i-th pixel and the (i+1)-th pixel, respectively, and the (i+1)-th scan signal at least partially overlaps with the i-th scan signal.

3. The display device according to claim 1, wherein, The level of the reference voltage is reduced by the (i+1)th pixel during the first time period.

4. The display device according to claim 1, wherein, The i-th scan signal includes the i-th write scan signal and the i-th sample scan signal. The (i+1)th scan signal includes the (i+1)th write scan signal and the (i+1)th sample scan signal, and The i-th write scan signal is activated and applied to the i-th pixel during the first time period and the third time period, the i-th sampling scan signal is activated and applied to the i-th pixel during the first time period to the third time period, and the (i+1)-th sampling scan signal is activated and applied to the (i+1)-th pixel during the first time period.

5. The display device according to claim 4, wherein, During the first time period, the i-th pixel receives the data voltage for sensing in response to the i-th write scan signal, and receives the reference voltage in response to the i-th sampling scan signal. During the first time period, the (i+1)th pixel is connected to the reference line receiving the reference voltage in response to the (i+1)th sampling scan signal.

6. The display device according to claim 5, wherein, The (i+1)th pixel includes: A light-emitting element includes an anode and a cathode, wherein the anode and the cathode are short-circuited, and A short-circuit resistor is formed at the portion of the display device where the short circuit has occurred and is connected to the reference line during the first time period.

7. The display device according to claim 6, wherein, During the second time period, the i-th write scan signal is deactivated, and During the second time period, the sensed voltage sensed in the i-th pixel based on the data voltage used for sensing, the reference voltage, and the short-circuit resistance is output through the reference line.

8. The display device according to claim 4, wherein, The (i+1)th write scan signal is deactivated during the first time period to the third time period, and the (i+1)th sample scan signal is deactivated during the second time period and the third time period.

9. The display device according to claim 4, wherein, During the display cycle, the i-th write scan signal and the i-th sample scan signal are applied to the i-th pixel in the same timing sequence. The i-th pixel receives the data voltage in response to the i-th write scan signal, and receives the reference voltage in response to the i-th sampling scan signal. During the display cycle, the (i+1)th write scan signal and the (i+1)th sample scan signal are applied to the (i+1)th pixel in the same timing sequence. The (i+1)th pixel receives the data voltage in response to the (i+1)th write scan signal and receives the reference voltage in response to the (i+1)th sample scan signal.

10. The display device according to claim 4, further comprising: A data line, connected to the i-th pixel and the (i+1)-th pixel, receives the data voltage during the display cycle, receives the data voltage for sensing during the first time period, and receives the recovery data voltage during the third time period; A reference line is connected to the i-th pixel and the (i+1)-th pixel, and receives the reference voltage during the display period, the first time period, and the third time period; The i-th write scan line is connected to the i-th pixel and receives the i-th write scan signal; The i-th sampling scan line is connected to the i-th pixel and receives the i-th sampling scan signal; The (i+1)th write scan line is connected to the (i+1)th pixel and receives the (i+1)th write scan signal; as well as The (i+1)th sampling scan line is connected to the (i+1)th pixel and receives the (i+1)th sampling scan signal.

11. The display device according to claim 10, wherein, The i-th pixel includes: The first transistor includes a first electrode connected to a first power line, a control electrode connected to a first node, and a second electrode connected to a second node; The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a control electrode connected to the i-th write scan line; The third transistor includes a first electrode connected to the reference line, a second electrode connected to the second node, and a control electrode connected to the i-th sampling scan line; The i-th capacitor includes a first electrode connected to the first node and a second electrode connected to the second node; and The i-th light-emitting element includes an anode connected to the second node and a cathode connected to the second electric line.

12. The display device according to claim 11, wherein, The (i+1)th pixel includes: The first-1 transistor includes a first electrode connected to the first power line, a control electrode connected to the first-1 node, and a second electrode connected to the second-1 node; The second-1st transistor includes a first electrode connected to the data line, a second electrode connected to the first-1st node, and a control electrode connected to the (i+1)th write scan line; The 3-1 transistor includes a first electrode connected to the reference line, a second electrode connected to the 2-1 node, and a control electrode connected to the (i+1)th sampling scan line; The (i+1)th capacitor includes a first electrode connected to the (1-1)th node and a second electrode connected to the (2-1)th node; The (i+1)th light-emitting element includes an anode connected to the (2-1)th node and a cathode connected to the second electric field line; and The short-circuit resistance is formed due to a short circuit between the anode portion of the (i+1)th light-emitting element and the cathode portion of the (i+1)th light-emitting element.

13. The display device according to claim 10, further comprising: A timing controller is configured to compensate the data voltage applied to the i-th pixel based on the sensed voltage output through the reference line connected to the i-th pixel during the second time period.

14. The display device according to claim 4, wherein, The display on cycle and the display off cycle preceding the display on cycle are defined. The display on cycle includes the display cycle and the blanking cycle. The display off cycle includes a first sensing period and a second sensing period. During the first sensing period, the i-th scan signal and the (i+1)-th scan signal are sequentially applied to the i-th pixel and the (i+1)-th pixel, respectively. The i-th pixel receives the voltage for sensing and the reference voltage in response to the i-th scan signal, and The (i+1)th pixel receives the voltage for sensing and the reference voltage in response to the (i+1)th scan signal.

15. The display device according to claim 14, wherein, The second sensing period includes a fourth period, a fifth period, a sixth period, a seventh period, an eighth period, and a ninth period, wherein the fourth period, the fifth period, the sixth period, the seventh period, the eighth period, and the ninth period are consecutive. The i-th write scan signal is activated and applied to the i-th pixel during the fourth and sixth time periods of the second sensing period, and the i-th sample scan signal is activated and applied to the i-th pixel during the fourth to sixth time periods of the second sensing period. The (i+1)th write scan signal is activated and applied to the (i+1)th pixel during the seventh and ninth periods of the second sensing period, and the (i+1)th sample scan signal is activated and applied to the (i+1)th pixel during the fourth period of the second sensing period and during the seventh to ninth periods of the second sensing period. The i-th pixel receives the data voltage and the reference voltage for sensing during the fourth period of the second sensing period, the (i+1)-th pixel receives the data voltage and the reference voltage for sensing during the seventh period of the second sensing period, and the level of the reference voltage is reduced by the (i+1)-th pixel during the fourth period of the second sensing period.

16. A driving method for a display device, the driving method comprising: During the display cycle, a data voltage and a reference voltage are applied to the i-th pixel located in the i-th row in sync with the i-th scan signal; During the display cycle, the data voltage and the reference voltage are applied to the (i+1)th pixel located in the (i+1)th row in sync with the (i+1)th scan signal; During the first time period of the blanking period following the display period, a data voltage for sensing is applied to the i-th pixel in sync with the i-th write scan signal of the i-th scan signal; During the first time period, the reference voltage is applied to the i-th pixel synchronously with the i-th sampled scan signal of the i-th scan signal; During the first time period, the (i+1)th pixel is connected to the reference line receiving the reference voltage in sync with the (i+1)th sampled scan signal of the (i+1)th scan signal; as well as During a second time period following the first time period, the sensed voltage sensed in the i-th pixel is output through the reference line, where i is a natural number greater than 0.

17. The driving method of claim 16, further comprising compensating the data voltage applied to the i-th pixel based on the sensing voltage output through the reference line.

18. The driving method of claim 16, further comprising reducing the level of the reference voltage via the (i+1)th pixel during the first time period. in, The (i+1)th pixel includes: A light-emitting element includes an anode and a cathode, wherein the anode and the cathode are short-circuited, and A short-circuit resistor is formed at the portion of the display device where the short circuit has occurred and is connected to the reference line during the first time period.

19. The driving method according to claim 16, further comprising: During the third time period following the second time period, a recovery data voltage is applied to the i-th pixel in sync with the i-th write scan signal; as well as During the third time period, the reference voltage is applied to the i-th pixel in sync with the i-th sampling scan signal.

20. Electronic devices, including: Display devices provide images to users; as well as One or more processors are configured to process image signals and provide the image signals to the display device. The display device includes: The i-th pixel, located in the i-th row, receives data voltage and reference voltage in response to the i-th scan signal during the display cycle, and The (i+1)th pixel is located in the (i+1)th row and, during the display cycle, receives the data voltage and the reference voltage in response to the (i+1)th scan signal. The blanking cycle following the display cycle includes a first time period, a second time period, and a third time period, wherein the first time period, the second time period, and the third time period are consecutive. The i-th scan signal is applied to the i-th pixel during the first time period to the third time period, and the (i+1)-th scan signal is applied to the (i+1)-th pixel during the first time period. During the first time period, the i-th pixel receives a data voltage for sensing and the reference voltage, and during the first time period, the level of the reference voltage is decreased by the (i+1)-th pixel, and During the second time period following the first time period, the sensed voltage sensed in the i-th pixel is output via a reference line, where i is a natural number greater than 0.

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