An implementation method for consistency of multiple power-on phases based on ADC acquisition

Abstract

The application discloses a kind of based on ADC acquisition multiple power-on phase consistency implementation methods, it is related to communication technical field, the method includes: step S1: preset clock system and set ADC channel, using FPGA main chip to execute output disable to clock generator;Step S2: using FPGA main chip writes in SYNC synchronization command, make the generation time of clock signal of each output channel of clock generator alignment;Step S3: using FPGA main chip to collect test signal from radio frequency device, calculate the cross-correlation function between channel data;Step S4: generate phase calibration data, execute digital domain real-time compensation, so that the phase of each channel data after compensation and reference channel data are aligned.The application measures the phase difference of actual transmission path by hardware synchronization reset, completes the phase alignment of each channel and reference channel, has the advantages that ADC channel data phase and reference channel keep alignment and effectively overcome the beneficial effects of FPGA clock distribution path uncertainty.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and specifically to a method for achieving phase consistency across multiple power-on acquisitions based on an ADC. Background Technology

[0002] In applications such as precision testing, phased array radar, and multi-channel beamforming, multi-channel ADCs are frequently required for synchronous data acquisition. These systems typically use an externally provided 100MHz reference clock and internally generate multiple operating clocks via phase-locked loops. After each power-on and power-off cycle, the phase difference between the FPGA digital logic clock and the external reference sampling clock changes, resulting in inconsistent initial phases of the data acquired from multiple channels, which fails to meet the requirements for experimental data analysis.

[0003] Specifically, during each cold start or warm restart of the system, the initial phase of the clock circuits within each chip is random, resulting in an inconsistent absolute phase of the acquired signal relative to the external world after each power-on. The start-up phase and locking process of the VCO (Voltage-Controlled Oscillator) within the RF_SOC and ADC are independent and random each time power is applied. Even if they share the same reference clock, the initial phase relationship of their output clocks is entirely new and unpredictable each time power is applied. Therefore, it is impossible to acquire signals from the external world from non-homogeneous systems. In other words, the initial oscillation phase and locking process of the PLL and VCO within the RF_SOC / ADC chips are independent, non-deterministic random events each time power is applied; simultaneously, the distribution, buffering, and logic usage paths of the same 100MHz reference clock within the FPGA exhibit nanosecond-level uncertainty at the start-up time after each configuration or reset. Even if the system shares the same external 100MHz reference clock source, the relative phase difference between the FPGA's internal logic clock edge and the ADC sampling clock edge is entirely new and unpredictable after each power-on / reset. Ultimately, this results in a situation where, when a multi-channel ADC acquires external signals from different sources, the initial phase of the digital sampling sequence obtained in each experimental run is different. In conventional equipment, if the random phase difference is not resolved, the fixed skew cannot be corrected alone to restore the absolute phase reference. Summary of the Invention

[0004] This invention provides a method for achieving phase consistency across multiple power-ups based on ADC acquisition, which solves the problem of random clock phase distribution differences in the main control chip's clock phase during repeated startups in existing precision clock systems.

[0005] This invention is achieved through the following technical solution: A method for achieving phase consistency across multiple power-on acquisitions using an ADC, the method comprising: Step S1: Preset a clock system including the FPGA main chip, clock generator and RF devices, set up multiple ADC channels from the RF devices to the FPGA main chip, start the clock system, and use the FPGA main chip to configure the clock generator's registers to keep the clock generator output disabled. Step S2: Use the FPGA main chip to write the SYNC synchronization command to the synchronization control register of the clock generator through the SPI interface. When the phase-locked loop lock indication inside the clock generator is valid, the clock generator will perform a hardware synchronization reset to align the generation time of the clock signals of each output channel of the clock generator. Step S3: Use the FPGA main chip to acquire test signals from the RF device, split the test signals into channel data corresponding to each ADC channel and send them to the logic unit of the FPGA main chip, set the first channel data as the reference channel, and calculate the cross-correlation function between the other channel data and the first data. Step S4: Generate phase calibration data based on the cross-correlation function, read the phase calibration data using the FPGA main chip, and perform real-time digital domain compensation on the data stream of all ADC channels based on the phase calibration data using the FPGA main chip, so that the compensated channel data is aligned with the reference channel data in phase.

[0006] Furthermore, during startup in step S1, the FPGA main chip continuously monitors the phase-locked loop (PLL) lock indication signal inside the clock generator until it is confirmed that the PLL has been stably locked to the externally input reference clock source in the clock generator.

[0007] Furthermore, the process of performing cross-correlation function calculation includes: setting the end of the ADC channel connected to the RF device as the input terminal and the other end connected to the FPGA main chip as the output terminal; feeding a test signal with a preset frequency and phase to the input terminals of all ADC channels; the FPGA main chip receives the four-channel digital sampling data generated by the output terminals of the ADC channels and sends it to the internal logic processing unit of the FPGA main chip; using the sequence of data from the first channel as the reference channel, performing cross-correlation function calculation with the data sequence of the reference channel on the data sequence of each of the remaining channels respectively.

[0008] Furthermore, the phase calibration data includes delay bias and phase bias; the process of generating phase calibration data based on the cross-correlation function includes: For each ADC channel, the delay offset of the corresponding ADC channel relative to the reference channel is obtained by searching the offset of the peak position of the cross-correlation function relative to the zero delay point, and the delay offset is marked as the delay deviation; the phase offset of the fractional sampling interval is obtained by performing sub-pixel estimation algorithms such as parabolic interpolation on the peak neighborhood data, and the phase offset is marked as the phase deviation.

[0009] Furthermore, a hardware synchronization reset operation is performed on the frequency divider and delay controller inside the clock generator for output; after the synchronization reset operation is completed, the FPGA main chip is used to control the clock output of the clock generator and provide the absolute phase clock signal after synchronization processing to its internal logic.

[0010] Furthermore, based on the absolute phase clock signal, the FPGA main chip releases the global reset and completes the initialization configuration of the phase-locked loop inside the clock generator, so that the phase difference between the FPGA internal working clock and the external reference clock source remains a fixed constant value after each execution of steps S1 to S2.

[0011] Furthermore, the process of performing real-time compensation in the digital domain includes: performing cyclic shift processing on the data sample sequence using delay bias, setting the number of sampling points of delay bias as the number of shift points of cyclic shift, and applying phase rotation processing to the shifted data in the frequency domain based on phase bias, so that the data of each channel after phase rotation is aligned with the data of the reference channel in phase.

[0012] Furthermore, the processes of the cyclic shifting process and the phase rotation process include: A continuous data sequence of channel data from all ADC channels is written into a ring buffer. The delay deviation is denoted as Δn. The read pointer of the ring buffer is offset by Δn memory units relative to the write pointer. The data sequence segment read by the pointer offset is concatenated with the historical data sequence segment located at the beginning of the ring buffer to form a continuous effective data output sequence. The effective data output sequence is then subjected to a Fast Fourier Transform (FFT) to convert it to the frequency domain. A phase rotation factor is applied to each frequency component in the frequency domain according to the phase deviation. The frequency domain data after phase rotation is then subjected to an Inverse Fast Fourier Transform (IFFT) to reconstruct the time domain data sequence. The reconstructed sequence is phase-aligned with the reference channel data sequence at sub-sampling point precision.

[0013] Furthermore, the ring buffer is implemented by a shift register array consisting of a cascaded chain of flip-flops, wherein the shift register array contains multiple tap output ports, each tap corresponding to a different delay level, and the offset operation of the read pointer is completed by selecting the tap output signal corresponding to the delay level.

[0014] Furthermore, the ring buffer also includes a pointer synchronization reset unit; after the system performs a clock synchronization operation, the pointer synchronization reset unit responds to the release of the global reset signal by simultaneously initializing the write pointer and the read pointer to the first address of the ring buffer.

[0015] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1. By using hardware synchronous reset, random phase differences between the output channels inside the clock generator are eliminated; combined with digital domain compensation, the data acquired by all ADC channels are aligned with the reference channel in phase after each system cold start or warm restart, ensuring the reproducibility of data acquired from multiple channels. 2. By directly measuring the comprehensive phase difference of the actual transmission path through the cross-correlation function, and performing compensation and phase alignment between each channel and the reference channel in the digital domain, the system can recover the absolute phase reference of the external world signal by combining the known external phase reference, which can effectively overcome the nanosecond-level uncertainty problem of the clock distribution path inside the FPGA. 3. By compensating for the phase difference in the digital domain, no manual intervention or external measuring instruments are required. Calibration can be completed within milliseconds after each power-on. The system does not rely on an extremely low-skew clock distribution network or a high-precision equal-length trace design, which reduces the difficulty of PCB design and engineering implementation and improves the system's engineering fault tolerance. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the present invention; Figure 2 This is a schematic diagram of the clock system of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0018] Examples, such as Figure 1 As shown, this embodiment is a method for achieving phase consistency across multiple power-on acquisitions using an ADC. The method includes: Step S1: Preset a clock system including the FPGA main chip, clock generator and RF devices, set up multiple ADC channels from the RF devices to the FPGA main chip, start the clock system, and use the FPGA main chip to configure the clock generator's registers to keep the clock generator output disabled. Step S2: Use the FPGA main chip to write the SYNC synchronization command to the synchronization control register of the clock generator through the SPI interface. When the phase-locked loop lock indication inside the clock generator is valid, the clock generator will perform a hardware synchronization reset to align the generation time of the clock signals of each output channel of the clock generator. Step S3: Use the FPGA main chip to acquire test signals from the RF device, split the test signals into channel data corresponding to each ADC channel and send them to the logic unit of the FPGA main chip, set the first channel data as the reference channel, and calculate the cross-correlation function between the other channel data and the first data. Step S4: Generate phase calibration data based on the cross-correlation function, read the phase calibration data using the FPGA main chip, and perform real-time digital domain compensation on the data stream of all ADC channels based on the phase calibration data using the FPGA main chip, so that the compensated channel data is aligned with the reference channel data in phase.

[0019] The clock system represents a multi-channel synchronous acquisition hardware platform consisting of an FPGA main chip, a clock generator, and RF devices. The RF devices integrate multiple ADC channels, with the output of each ADC channel connected to a corresponding input pin of the FPGA main chip. After system power-on or reset, the FPGA main chip first initializes the clock generator's registers via its internal or external control buses such as SPI or I²C. A key operation is disabling all output channels of the clock generator. During initial system startup, the clock generator is temporarily blocked from providing any operating clock to the RF devices and the FPGA main chip, thus preventing the random initial phase clock signal generated by the PLL / VCO inside the clock generator during power-on oscillation from prematurely entering subsequent links. By keeping the outputs disabled, a clean clock control starting point is created for subsequent unified hardware synchronous reset, preventing unpredictable clock edges from prematurely triggering the logic state inside the RF devices or FPGA, ensuring the effectiveness and determinism of subsequent synchronous operations.

[0020] The FPGA main chip writes a SYNC synchronization command to the clock generator's synchronization control register via the SPI interface. Upon detecting a valid PLL lock indication within the clock generator, it triggers a hardware synchronization reset. This hardware synchronization reset forces all output channel dividers or phase selectors within the clock generator to be reset to a preset initial state simultaneously, ensuring that the first clock edge of each output channel's clock signal originates from the same time reference point, thus aligning the clock edges of each channel in the time domain. The synchronization reset after the PLL lock indication is valid ensures that the voltage-controlled oscillator (VCO) frequency output by the PLL is stable. However, phase dispersion may exist between output channels due to different divider start and stop states. This step triggers the reset by writing the SYNC command, forcing this dispersion to zero, transforming the phase relationship of the clock signals from a random distribution after PLL lock to a deterministic and repeatable aligned state. After hardware synchronous reset, the clock phase difference between each output channel of the clock generator is fixed to zero or a known fixed value, thereby ensuring that the phase difference of the test signal acquired in the subsequent step S3 only comes from the analog link skew between ADC channels and the internal path delay of the FPGA, and no longer includes the random phase component of the clock generator output.

[0021] After the clock system completes hardware synchronization reset, the FPGA main chip controls the RF device to output a known test signal, and synchronously acquires this test signal through all ADC channels to obtain multi-channel parallel sampling data. The FPGA main chip splits the acquired multi-channel data into independent digital sampling sequences according to the channel, and sends these sequences to its internal logic unit. In specific implementations, DSP slices or programmable logic arrays can be used for subsequent processing of the logic unit. Using the sampling sequence of the first channel as the phase reference benchmark, i.e., the zero-phase reference channel, the sampling sequences of the remaining channels are cross-correlated with this reference sequence. The cross-correlation function is defined as a similarity measure of two sequences in the time-shift domain, and its peak position corresponds to the relative time delay difference between the two channels. This time delay difference multiplied by the signal angular frequency is converted into the relative phase difference between the channels. By detecting the peak coordinate of the cross-correlation function, the sampling phase deviation value of each non-reference channel relative to the reference channel can be accurately calculated. This deviation value integrates all random and fixed delay differences from the clock generator output, the internal path of the RF device, the ADC sampling time to the FPGA receiver, providing an accurate calibration basis for the digital domain real-time compensation in the subsequent step S4.

[0022] The FPGA main chip acquires test signals from the RF devices and breaks them down into channel data corresponding to each ADC channel. Using the first channel data as a phase reference, the cross-correlation function of each of the remaining channel data is calculated with respect to this reference channel data. Since the peak position of the cross-correlation function in the time domain directly reflects the relative time delay between two signal sequences, and this time delay corresponds to the phase difference of the sampling clock edge, the sampling phase deviation of each channel relative to the reference channel under the current power-on state can be quantitatively obtained by detecting the time offset of the cross-correlation function peak. As a possible implementation example, such as... Figure 2 As shown, the FPGA main chip uses an RF_SOC device, and the clock generator uses an HMC7044 chip. The HMC7044 chip outputs a clock to the digital circuit section of the RF_SOC device, the RF_SOC device outputs a digital-to-analog conversion signal to the RF device, and the RF device outputs a sampling clock to the analog circuit section of the RF_SOC device. The RF device uses a power divider to input the ADC multi-channel signal to the analog circuit section of the RF_SOC device. Based on the phase deviation calculated using the cross-correlation function, corresponding phase calibration data is generated. This calibration data can be expressed as a complex rotation factor, fractional delay filter coefficients, or phase accumulation offset, depending on the subsequent digital compensation implementation. Finally, the FPGA main chip reads this phase calibration data and applies it to the real-time data stream of all ADC channels. In the digital domain, phase rotation is achieved through a complex multiplier, subsampling delay adjustment is achieved through a Farrow fractional delay filter, or the initial phase of the digital downconversion (DDC) is adjusted through a numerically controlled oscillator (NCO), thereby dynamically compensating the sampling sequence of each channel. After compensation, the signal envelope and carrier phase in each channel data stream are strictly aligned with the reference channel data, which is equivalent to eliminating the inter-channel sampling clock edge deviation introduced by power-on randomness.

[0023] Furthermore, as a feasible implementation, when the FPGA main chip is kept running in step S1, it monitors the phase-locked loop lock indication signal inside the clock generator until it is confirmed that the phase-locked loop has been stably locked to the externally input reference clock source in the clock generator.

[0024] By conditionally binding the "clock generator output disabled" state with the "PLL phase-locked loop lock complete" event, the output channel of the clock generator remains disabled and does not participate in any synchronization operation when the internal clock reference of the clock generator is not yet stable. This provides a deterministic timing prerequisite for the correct execution of the hardware synchronization reset in step S2. During the clock system startup process, the FPGA main chip does not immediately execute the clock generator output enable or subsequent synchronization operation. Instead, it first establishes a continuous monitoring mechanism for the lock indication signal of the internal phase-locked loop of the clock generator. The lock indication signal is generated internally by the clock generator and is usually represented by a register status bit or a dedicated hardware pin level. Its valid state indicates that the phase detector of the PLL has detected that the frequency difference and phase difference between the reference clock and the feedback clock have converged to the preset lock window, the VCO control voltage has stabilized, and the entire PLL has entered the locked steady-state operating region. The FPGA main chip determines whether the PLL has been stably locked to the externally input reference clock source by reading this lock indication signal. Before the lock indicator signal is valid, the FPGA master chip remains in monitoring state and does not send any control commands to the clock generator to change the output state. Only when the lock indicator signal remains valid, confirming that the PLL has completed the capture process and entered stable lock, does the FPGA master chip determine that the system meets the conditions to enter the subsequent steps.

[0025] Furthermore, as a feasible implementation method, the process of performing cross-correlation function calculation includes: setting one end of the ADC channel connected to the radio frequency device as the input end and the other end connected to the FPGA main chip as the output end; feeding a test signal with a preset frequency and phase to the input ends of all ADC channels; the FPGA main chip receives the four-channel digital sampling data generated by the output end of the ADC channels and sends it to the internal logic processing unit of the FPGA main chip; using the sequence of data from the first channel as the reference channel, performing cross-correlation function calculation with the data sequence of the reference channel on the data sequence of each of the remaining channels respectively.

[0026] The physical connection relationships of the ADC channels are clearly defined: the end of the ADC channel connected to the RF device is defined as the input terminal, which receives the input from external analog signals; the end of the ADC channel connected to the FPGA main chip is defined as the output terminal, which transmits the digital sampled data after analog-to-digital conversion to the FPGA main chip. This definition aims to establish a clear signal flow description for subsequent signal injection and data acquisition. In practical applications, the RF device can be such as an RF transceiver, RF front-end, or antenna interface. During the testing phase, a test signal with a preset frequency and preset phase is fed into the input terminals of all ADC channels. The "common feed" means that the test signal is simultaneously applied to the analog input terminals of all ADC channels through a distribution network of equal length and equal impedance, ensuring that the electrical signals received by each channel at the input terminal have high consistency in frequency, phase, and amplitude characteristics. The frequency and phase of the test signal are preset known values, selected based on the principle of being within the effective bandwidth of the ADC and avoiding strong interference frequencies in the system, to facilitate subsequent digital domain processing. The FPGA main chip receives the four channels of digital sampled data generated by the output terminals of each ADC channel. The "four channels" here correspond to a four-channel ADC architecture. The four data channels represent the digital sequences output by four independent ADC channels after analog-to-digital conversion of the input signal at the same sampling clock edge. Finally, these four digital sampled data channels are sent to the logic processing unit inside the FPGA main chip. This logic processing unit may include a cross-correlation operation module, a buffer FIFO, and a phase calculation engine, used to perform subsequent cross-correlation function operations, peak detection, and phase difference extraction on the four data channels.

[0027] Furthermore, the phase calibration data includes delay bias and phase bias; the process of generating phase calibration data based on the cross-correlation function includes: For each ADC channel, the delay offset of the corresponding ADC channel relative to the reference channel is obtained by searching the offset of the peak position of the cross-correlation function relative to the zero delay point, and the delay offset is marked as the delay deviation; the phase offset of the fractional sampling interval is obtained by performing sub-pixel estimation algorithms such as parabolic interpolation on the peak neighborhood data, and the phase offset is marked as the phase deviation.

[0028] The delay bias characterizes a coarse-grained time offset in multiples of integer sampling periods, while the phase bias characterizes a fractional-grained phase offset less than one sampling period. For each ADC channel, the cross-correlation function between the digital sampled data sequence of that channel and the data sequence of the reference channel is calculated. The peak position of the cross-correlation function in the time domain reflects the relative time delay between the two sequences. By searching for the offset of this peak position relative to the zero-delay point (i.e., the theoretical reference position where the two sequences are perfectly aligned), the integer-sample-point level delay offset of the corresponding ADC channel relative to the reference channel is obtained, and this offset is labeled as the delay bias. Since the peak detection accuracy of the cross-correlation function at discrete sampling points is limited by the sampling interval, the phase information of the fractional sampling interval cannot be directly obtained. Therefore, a sub-pixel estimation algorithm is used to interpolate the cross-correlation function values ​​in the neighborhood of the peak. Specifically, the cross-correlation function values ​​of the peak point and several neighboring points before and after it are extracted, and the true peak position is estimated at sub-sampling accuracy using methods such as parabolic interpolation, Gaussian fitting, or quadratic curve fitting. The offset of this true peak position relative to the peak of the integer sampling point is the phase offset of the fractional sampling interval, and this offset is labeled as the phase bias.

[0029] Furthermore, as a feasible implementation, a hardware synchronization reset operation is performed on the frequency divider and delay controller inside the clock generator for output; after the synchronization reset operation is completed, the FPGA main chip is used to control the clock output of the clock generator and provide the absolute phase clock signal after synchronization processing to its internal logic.

[0030] A trigger command is written to the clock generator's internal synchronization control register, which is dedicated to the output channels, via the SPI interface. When this command is executed, the clock generator's internal logic generates a synchronization pulse. This pulse simultaneously resets the divider counters of all output channels and the phase accumulator of the delay controller, bringing the clock division phase of each output channel to zero. After the reset operation is complete, the clock signals of each output channel restart outputting on the same clock edge, thus achieving strict alignment of the output clock edges. Subsequently, the FPGA master chip enables the clock generator's output enable pin and distributes the received clock signal to the entire FPGA logic array through the FPGA's internal global clock buffer, ensuring that all synchronization circuits within the FPGA operate in this absolute phase clock domain. Through the above operations, this invention eliminates the random phase deviation between the FPGA logic clock and the ADC sampling clock, establishing a deterministic clock reference for subsequent inter-channel phase difference measurement and compensation.

[0031] Furthermore, as a feasible implementation method, based on the absolute phase clock signal, the FPGA main chip releases the global reset and completes the initialization configuration of the phase-locked loop inside the clock generator, so that the phase difference between the FPGA internal working clock and the external reference clock source remains a fixed constant value after each execution of steps S1 to S2.

[0032] After performing a hardware synchronous reset and outputting an absolute phase clock signal, the FPGA master chip connects this clock signal to its global clock buffer as the main operating clock for the entire FPGA logic array. Subsequently, a synchronous reset state machine within the FPGA master chip samples a software-configured reset release condition on the rising edge of this main operating clock, such as the delay counter reaching a preset value or the external reset signal being released, and synchronously releases the internal global reset signal on this clock edge. Simultaneously, the FPGA master chip writes a PLL initialization configuration command to the clock generator via the SPI interface. This command includes, but is not limited to, setting the PLL phase adjustment word, calibrating the tap position of the delay chain, or locking the threshold of the phase detector. After the above configuration is completed, the phase relationship between the internal operating clock output by the clock generator and the externally input 100MHz reference clock is locked to a preset fixed value determined by the design. Because the above operation sequence is strictly consistent after each power-on, and all timing edges are referenced to the absolute phase clock, the phase difference remains the same fixed constant value after each execution of steps S1 to S2, thus eliminating the random phase difference problem at its source.

[0033] Furthermore, as a feasible implementation method, the process of performing real-time compensation in the digital domain includes: performing cyclic shift processing on the data sample sequence using delay deviation, setting the number of sampling points of delay deviation as the number of shift points of cyclic shift, and applying phase rotation processing to the shifted data in the frequency domain based on phase deviation, so that the data of each channel after phase rotation is aligned with the data of the reference channel in phase.

[0034] Using the delay and phase deviations in the phase calibration data generated in the preceding steps, a two-stage compensation method combining time-domain shifting and frequency-domain phase rotation is employed to compensate the data streams of each channel. First, the delay deviation is used to perform a cyclic shift on the data sample sequence. The integer sample point offset represented by the delay deviation is used as the shift number for the cyclic shift, and the digital sample sequence of the current channel is rearranged at the sample level. The cyclic shift operation is achieved by changing the FIFO read start address or using cyclic indexing of the data buffer, ensuring that the shifted sequence is aligned with the reference channel sequence at the integer sample point level. Then, based on the cyclic shift, a phase rotation is applied to the shifted data in the frequency domain based on the phase deviation. Since the phase deviation represents a fractional phase offset less than one sampling period, its time-domain manifestation is a fractional delay between sample points, which cannot be directly compensated by integer shifting. After two-stage compensation through cyclic shifting and phase rotation, the data of each channel is phase-aligned with the reference channel data at both the integer and fractional sample point levels; that is, the compensated data sequences of each channel completely overlap with the reference channel data sequences in the time domain waveform. Integer delay compensation is achieved through cyclic shifting, requiring no multipliers or filter resources and only utilizing the block RAM address control logic within the FPGA. Fractional phase compensation is achieved through complex multiplication, requiring only one complex multiplier per operation. Compared to directly using the multiply-add operation of a fractional delay filter, this implementation significantly reduces the DSP unit and logic resource usage.

[0035] Furthermore, as a feasible implementation, the cyclic shifting process and the phase rotation process include: A continuous data sequence of channel data from all ADC channels is written into a ring buffer. The delay deviation is denoted as Δn. The read pointer of the ring buffer is offset by Δn memory units relative to the write pointer. The data sequence segment read by the pointer offset is concatenated with the historical data sequence segment located at the beginning of the ring buffer to form a continuous effective data output sequence. The effective data output sequence is then subjected to a Fast Fourier Transform (FFT) to convert it to the frequency domain. A phase rotation factor is applied to each frequency component in the frequency domain according to the phase deviation. The frequency domain data after phase rotation is then subjected to an Inverse Fast Fourier Transform (IFFT) to reconstruct the time domain data sequence. The reconstructed sequence is phase-aligned with the reference channel data sequence at sub-sampling point precision.

[0036] The core of this implementation lies in decoupling cyclic shifting and frequency-domain phase rotation, performing these processes separately in the time and frequency domains. This avoids the high computational complexity and hardware resource overhead associated with directly implementing a fractional delay filter in the time domain. Cyclic shifting is performed on the data sample sequence using delay bias, with the integer sample point offset represented by the delay bias serving as the shift value. This allows for sample-level rearrangement of the digital sample sequence for the current channel. Following the cyclic shifting, phase rotation is applied to the shifted data in the frequency domain based on the phase bias. Since the phase bias represents a fractional phase offset less than one sampling period, its time-domain manifestation is a fractional delay between sample points, which cannot be directly compensated for by integer shifting. Therefore, the shifted data sequence is transformed to the frequency domain, and a phase rotation factor corresponding to the phase bias is applied to each frequency point or each sample point. After these two stages of compensation—cyclic shifting and phase rotation—the data in each channel is phase-aligned with the reference channel data at both the integer and fractional sample point levels. In other words, the compensated data sequences of each channel completely overlap with the reference channel data sequences in the time domain waveform. By applying a phase rotation factor to each frequency component in the frequency domain, it is equivalent to achieving a fractional delay of a non-integer multiple of the sampling period in the time domain, which can achieve an alignment error much smaller than one sampling period, meeting the application requirements of phased array radar and other applications with extremely high phase accuracy requirements.

[0037] Furthermore, as a feasible implementation, the ring buffer is implemented by a shift register array consisting of a cascaded chain of flip-flops, wherein the shift register array includes multiple tap output ports, each tap corresponding to a different delay level, and the offset operation of the read pointer is completed by selecting the tap output signal corresponding to the delay level.

[0038] The shift register array is composed of multiple cascaded flip-flops, each stage storing data for one sampling period. Multiple tap output ports are led out from different stages of the shift register array, each tap corresponding to a data delay stage following that stage of flip-flops. For example, stage 0 tap outputs the current input data, stage 1 tap outputs data delayed by one sampling period, stage 2 tap outputs data delayed by two sampling periods, and so on. In this embodiment, the read pointer offset operation is limited to selecting the tap output signal corresponding to the delay stage number with the delay offset using a multiplexer, based on the delay offset value, as the output data for that channel. Since all stages of the shift register array's taps exist simultaneously, selecting different taps is equivalent to changing the offset of the read pointer relative to the write pointer, without actually moving data or maintaining read / write pointer counters. The RAM-based ring buffer requires at least one clock cycle for address calculation and RAM reading, and the RAM read latency may further increase at high sampling rates. This implementation uses a flip-flop chain and a combinational logic multiplexer. The tap selection is completed within the same clock cycle. There is only the inherent propagation delay of the flip-flop chain between the output data and the input data, which is usually in the sub-nanosecond range. This achieves integer delay compensation with zero additional pipeline delay.

[0039] Furthermore, as a feasible implementation, the ring buffer also includes a pointer synchronization reset unit; after the system performs a clock synchronization operation, the pointer synchronization reset unit, in response to the release of the global reset signal, initializes the write pointer and the read pointer to the first address position of the ring buffer simultaneously.

[0040] After the system performs a clock synchronization reset operation, the FPGA main chip releases a global reset signal. In response to this global reset signal, the pointer synchronization reset unit performs a pointer initialization operation: simultaneously resetting the write and read pointers of the ring buffer to the starting address of the ring buffer. It should be noted that the write and read pointers are abstract logical pointers used to describe the relative positional relationship between data writing and reading. For a shift register array implementation, the write pointer corresponds to the current write position at the data input terminal, i.e., it is always the input terminal of the shift register array; the read pointer corresponds to the selected tap position. Initializing both to the starting address simultaneously is equivalent to clearing all valid data in the shift register array, or treating it as invalid, and setting the default output of the tap selector to the 0th tap. By simultaneously initializing the read and write pointers to the starting address through the pointer synchronization reset unit, the influence of residual data from the previous cycle on the current calibration process is eliminated. Regardless of how many cold starts or warm restarts the system undergoes, the ring buffer always starts operating from the same zero-phase state, providing a definite starting reference for subsequent integer compensation based on delay deviation.

[0041] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for achieving phase consistency across multiple power-on acquisitions based on an ADC, characterized in that, The method includes: Step S1: Preset a clock system including the FPGA main chip, clock generator and RF devices, set up multiple ADC channels from the RF devices to the FPGA main chip, start the clock system, and use the FPGA main chip to configure the clock generator's registers to keep the clock generator output disabled. Step S2: Use the FPGA main chip to write the SYNC synchronization command to the synchronization control register of the clock generator through the SPI interface. When the phase-locked loop lock indication inside the clock generator is valid, the clock generator will perform a hardware synchronization reset to align the generation time of the clock signals of each output channel of the clock generator. Step S3: Use the FPGA main chip to acquire test signals from the RF device, split the test signals into channel data corresponding to each ADC channel and send them to the logic unit of the FPGA main chip, set the first channel data as the reference channel, and calculate the cross-correlation function between the other channel data and the first data. Step S4: Generate phase calibration data based on the cross-correlation function, read the phase calibration data using the FPGA main chip, and perform real-time digital domain compensation on the data stream of all ADC channels based on the phase calibration data using the FPGA main chip, so that the compensated channel data is aligned with the reference channel data in phase.

2. The method for achieving phase consistency across multiple power-on acquisitions based on ADC as described in claim 1, characterized in that, When the FPGA main chip is running in step S1, it monitors the phase-locked loop (PLL) lock indication signal inside the clock generator until it confirms that the PLL has been stably locked to the externally input reference clock source in the clock generator.

3. The method for achieving phase consistency across multiple power-on acquisitions based on ADC as described in claim 1, characterized in that, The process of performing cross-correlation function calculation includes: setting the end of the ADC channel connected to the RF device as the input terminal and the other end connected to the FPGA main chip as the output terminal; feeding a test signal with a preset frequency and phase to the input terminals of all ADC channels; the FPGA main chip receives the four digital sampling data generated by the output terminals of the ADC channels and sends them to the internal logic processing unit of the FPGA main chip; using the sequence of data from the first channel as the reference channel, performing cross-correlation function calculation with the data sequence of the reference channel on the data sequence of each of the remaining channels respectively.

4. The method for achieving phase consistency across multiple power-on acquisitions based on ADC as described in claim 3, characterized in that, The phase calibration data includes delay bias and phase bias; The process of generating phase calibration data based on the cross-correlation function includes: For each ADC channel, the delay offset of the corresponding ADC channel relative to the reference channel is obtained by searching the offset of the peak position of the cross-correlation function relative to the zero delay point, and the delay offset is marked as the delay deviation; the phase offset of the fractional sampling interval is obtained by performing sub-pixel estimation algorithms such as parabolic interpolation on the peak neighborhood data, and the phase offset is marked as the phase deviation.

5. The method for achieving phase consistency across multiple power-on acquisitions based on ADC as described in claim 1, characterized in that, A hardware synchronization reset operation is performed on the frequency divider and delay controller inside the clock generator for output. After the synchronization reset operation is completed, the FPGA main chip is used to control the clock output of the clock generator and provide the absolute phase clock signal after synchronization processing to its internal logic.

6. The method for achieving phase consistency across multiple power-on acquisitions based on ADC, as described in claim 5, is characterized in that... Based on the absolute phase clock signal, the FPGA main chip releases the global reset and completes the initialization configuration of the phase-locked loop inside the clock generator, so that the phase difference between the FPGA internal working clock and the external reference clock source remains a fixed constant value after each execution of steps S1 to S2.

7. The method for achieving phase consistency across multiple power-on acquisitions based on ADC, as described in claim 4, is characterized in that... The process of performing real-time compensation in the digital domain includes: performing cyclic shift processing on the data sample sequence using delay bias, setting the number of sampling points of delay bias as the number of shift points of cyclic shift, and applying phase rotation processing to the shifted data in the frequency domain based on phase bias, so that the data of each channel after phase rotation is aligned with the data of the reference channel in phase.

8. The method for achieving phase consistency across multiple power-on acquisitions based on ADC, as described in claim 7, is characterized in that... The processes of the cyclic shifting process and the phase rotation process include: A continuous data sequence of channel data from all ADC channels is written into a ring buffer. The delay deviation is denoted as Δn. The read pointer of the ring buffer is offset by Δn memory units relative to the write pointer. The data sequence segment read by the pointer offset is concatenated with the historical data sequence segment located at the beginning of the ring buffer to form a continuous effective data output sequence. The effective data output sequence is then subjected to a Fast Fourier Transform (FFT) to convert it to the frequency domain. A phase rotation factor is applied to each frequency component in the frequency domain according to the phase deviation. The frequency domain data after phase rotation is then subjected to an Inverse Fast Fourier Transform (IFFT) to reconstruct the time domain data sequence. The reconstructed sequence is phase-aligned with the reference channel data sequence at sub-sampling point precision.

9. The method for achieving phase consistency across multiple power-on acquisitions based on an ADC, as described in claim 8, is characterized in that... The ring buffer is implemented by a shift register array consisting of a cascaded chain of flip-flops. The shift register array contains multiple tap output ports, each tap corresponding to a different delay level. The offset operation of the read pointer is completed by selecting the tap output signal corresponding to the delay level.

10. The method for achieving phase consistency across multiple power-on acquisitions based on ADC, as described in claim 9, is characterized in that... The ring buffer also includes a pointer synchronization reset unit; after the system performs a clock synchronization operation, the pointer synchronization reset unit responds to the release of the global reset signal by simultaneously initializing the write pointer and the read pointer to the first address of the ring buffer.

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