Virtualization system, virtualization method of hardware timer, device and storage medium

Abstract

Disclosed are a virtualization system, a virtualization method of a hardware timer, equipment and a storage medium, and relate to the technical field of virtualization systems. The system comprises an interrupt controller, at least one processor core and a hardware timer corresponding to each processor core. The processor core is configured to run a software program on a bound virtual processor core in a non-root mode. The hardware timer is configured to generate a timeout interrupt signal in response to a timeout occurring, and send the timeout interrupt signal to the interrupt controller. The interrupt controller is configured to receive the timeout interrupt signal and transmit the timeout interrupt signal to the processor core corresponding to the hardware timer. The processor core is further configured to switch the running mode from the non-root mode to a root mode in response to receiving the timeout interrupt signal. The system can directly switch the running mode, does not need to save the context, and does not need to turn off the hardware timer, and can improve the accuracy of the virtual timer.

Description

Technical Field

[0001] This disclosure relates to the field of virtualization system technology, and in particular to a virtualization system, a virtualization method for a hardware timer, an apparatus, and a storage medium. Background Technology

[0002] In existing virtualization technologies, the following mechanism is typically used to ensure the correctness of timer functions: when a virtual central processing unit (vCPU) exits to the hypervisor for some reason, the hypervisor saves the context (such as count value, enable state, etc.) of the virtual timer (vTimer) corresponding to the vCPU and shuts down the corresponding hardware timer to prevent it from being triggered abnormally in the host environment.

[0003] This mechanism has significant drawbacks: Firstly, the frequent saving of the vTimer context and shutdown of the hardware timer by the hypervisor is complex and introduces additional processor (Central Processing Unit, CPU) overhead. Secondly, after the hardware timer expires, the system needs to execute a serialized software processing pipeline. Each step in this pipeline has scheduling and execution delays, and these delays are nondeterministic, accumulating and amplifying timing deviations. Ultimately, this leads to a severe degradation of the actual accuracy of the virtualized timer, making it unsuitable for applications with stringent timing deterministic requirements, such as autonomous driving and high-performance computing. Summary of the Invention

[0004] Existing virtualization systems struggle to balance the need for multi-timeline adaptation with low overhead.

[0005] To address the aforementioned technical problems, a first aspect of this disclosure provides a virtualization system, including an interrupt controller, at least one processor core, and hardware timers corresponding one-to-one with each processor core; wherein, the processor core is configured to be bound one-to-one with a virtual processor core. The processor core is configured to run software programs on the bound virtual processor core in non-root mode to set the timeout of its corresponding hardware timer. A hardware timer is configured to generate a timeout interrupt signal in response to a timeout and send the timeout interrupt signal to the interrupt controller. The interrupt controller is configured to receive timeout interrupt signals and transmit them to the processor core corresponding to the hardware timer. The processor core is also configured to switch its operating mode from non-root mode to root mode in response to a received timeout interrupt signal, thus completing the exit of the virtual processor core.

[0006] A second aspect of this disclosure provides a method for virtualizing a hardware timer, applied to a virtualization system. The virtualization system includes an interrupt controller, at least one processor core, and a hardware timer corresponding one-to-one with each processor core. Each processor core is configured to be bound one-to-one to a virtual processor core. The method for virtualizing the hardware timer includes: By running the software program on the bound virtual processor core in non-root mode through the processor core, the timeout of its corresponding hardware timer can be set. In response to a timeout, a hardware timer generates a timeout interrupt signal and sends the timeout interrupt signal to the interrupt controller. The interrupt controller receives timeout interrupt signals and transmits them to the processor core corresponding to the hardware timer. By responding to a timeout interrupt signal, the processor core switches its operating mode from non-root mode to root mode, thus completing the exit of the virtual processor core.

[0007] A third aspect of this disclosure provides a hardware timer virtualization device, the device comprising: By running the software program on the virtual processor core of the bound virtualization system in non-root mode through the processor core of the virtualization system, the timeout of the corresponding hardware timer in the virtualization system can be set. In response to a timeout, a hardware timer generates a timeout interrupt signal and sends it to the interrupt controller in the virtualization system. The interrupt controller receives timeout interrupt signals and transmits them to the processor core corresponding to the hardware timer. By responding to a timeout interrupt signal, the processor core switches its operating mode from non-root mode to root mode, thus completing the exit of the virtual processor core.

[0008] A fourth aspect of this disclosure provides an electronic device including a processor and a memory for storing processor-executable instructions; the processor is configured to read executable instructions from the memory and execute the instructions to implement the virtualization method of the hardware timer provided in the second aspect above.

[0009] A fifth aspect of this disclosure provides a computer-readable storage medium storing a computer program for executing the virtualization method of the hardware timer provided in the second aspect above.

[0010] A sixth aspect of this disclosure provides a computer program product that, when instructions in the computer program product are executed by a processor, performs the virtualization method for the hardware timer provided in the second aspect described above.

[0011] The virtualization system provided in this disclosure configures a processor core to be bound one-to-one with a vCPU, and each processor core corresponds one-to-one with a hardware timer. Therefore, each vCPU exclusively uses its corresponding hardware timer. Consequently, when the hardware timer generates a timeout interrupt signal, requiring a switch from non-root mode to root mode (i.e., exiting from the vCPU to the hypervisor), there is no need to save the context or disable the hardware timer. The processor core can directly switch operating modes, and the hypervisor handles the interrupt. This significantly shortens the exit path, reduces software latency and overhead, and significantly improves the accuracy of the virtual timer, better meeting the needs of high real-time applications. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of a virtualization system provided in an exemplary embodiment of this disclosure.

[0013] Figure 2 This is a flowchart illustrating a hardware timer virtualization method provided in an exemplary embodiment of this disclosure.

[0014] Figure 3 This is a flowchart illustrating another method for virtualizing a hardware timer provided in an exemplary embodiment of this disclosure.

[0015] Figure 4 This is a flowchart illustrating another hardware timer virtualization method provided in an exemplary embodiment of this disclosure.

[0016] Figure 5 This is a flowchart illustrating another hardware timer virtualization method provided in an exemplary embodiment of this disclosure.

[0017] Figure 6 This is a flowchart illustrating another hardware timer virtualization method provided in an exemplary embodiment of this disclosure.

[0018] Figure 7 This is a schematic diagram of the structure of a hardware timer virtualization device provided in an exemplary embodiment of this disclosure.

[0019] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0020] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0021] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0022] Application Overview In servers, embedded systems, and automotive applications, timers serve as a fundamental system service and are crucial. As application scenarios continue to evolve, traditional low-precision timers are no longer sufficient to meet the stringent real-time requirements of various tasks. Therefore, modern systems often require high-precision timer support. Especially in virtualized environments, effectively improving the accuracy and performance of timers has become a critical and challenging technical problem.

[0023] Existing virtualization technologies typically employ the following mechanism to maintain the correctness of timers: When a Guest virtual machine's vCPU exits to the Hypervisor due to an interrupt, exception, or system call, the Hypervisor saves the vTimer context corresponding to that vCPU, including the current count value, expiration time, enable status, and other register configurations. At the same time, it disables the hardware timer corresponding to the vTimer to prevent it from generating unexpected interrupts or triggers in the host environment during the vCPU's exit.

[0024] If there are unexpired vTimer tasks when a vCPU exits, the Hypervisor will start its own local timer (such as a physical timer or a Hypervisor-level timer) and set its expiration time to the remaining time of the vTimer. When the local timer expires, the Hypervisor will inject a vTimer interrupt into the corresponding Guest virtual machine and wake up the sleeping vCPU, ensuring that the vTimer interrupt is not lost. When the vCPU is rescheduled into the Guest virtual machine, the Hypervisor will restore the previously saved vTimer context and reprogram and start the hardware timer, allowing the vTimer in the Guest to continue to function normally.

[0025] However, the above mechanism has significant drawbacks. On the one hand, the operation of frequently saving the vTimer context and disabling the hardware timer by the hypervisor is complex and introduces additional processor overhead. On the other hand, after the hardware timer expires, the system needs to sequentially complete software processes such as virtual interrupt injection, target vCPU scheduling wake-up, vTimer context restoration, and hardware timer re-enabling. Each step involves scheduling and execution delays, and these delays are non-deterministic, accumulating and amplifying timing deviations. Ultimately, this leads to a severe degradation of the actual accuracy of the virtualized timer, making it unsuitable for applications with stringent timing deterministic requirements, such as autonomous driving and high-performance computing.

[0026] To address the aforementioned technical problems, this disclosure proposes a virtualization system comprising an interrupt controller, at least one processor core, and hardware timers corresponding one-to-one with each processor core. The system involves configuring each processor core to be bound one-to-one with a virtual processor core; configuring each processor core to run a software program on its bound virtual processor core in non-root mode to set the timeout of its corresponding hardware timer; configuring the hardware timer to generate a timeout interrupt signal in response to a timeout and send the timeout interrupt signal to the interrupt controller; configuring the interrupt controller to receive the timeout interrupt signal and transmit it to the processor core corresponding to the hardware timer; and configuring the processor core to switch its operating mode from non-root mode to root mode in response to receiving the timeout interrupt signal, thereby exiting the virtual processor core.

[0027] Because each processor core is configured to be bound one-to-one with a vCPU, and each processor core corresponds one-to-one with a hardware timer, each vCPU exclusively uses its corresponding hardware timer. Therefore, when a hardware timer generates a timeout interrupt signal, requiring a switch from non-root mode to root mode (i.e., exiting from the vCPU to the hypervisor), there is no need to save the context or disable the hardware timer; the processor core can directly switch operating modes, and the hypervisor handles the interrupt. This significantly shortens the exit path, reduces software latency and overhead, and dramatically improves the accuracy of the virtual timer, better meeting the demands of high real-time applications.

[0028] Exemplary Virtualization System Figure 1 This is a schematic diagram of the structure of a virtualization system provided in an exemplary embodiment of this disclosure. For example... Figure 1 As shown, the virtualization system 10 includes an interrupt controller 101, at least one processor core 102, and hardware timers 103 corresponding one-to-one with each processor core 102; wherein, the processor core 102 is configured to be bound one-to-one with a virtual processor core vCPU. Processor core 102 is configured to run software programs on the bound virtual processor core in non-root mode to set the timeout of its corresponding hardware timer 103. Hardware timer 103 is configured to generate a timeout interrupt signal in response to a timeout and send the timeout interrupt signal to interrupt controller 101. Interrupt controller 101 is configured to receive timeout interrupt signals and transmit the timeout interrupt signals to the processor core 102 corresponding to hardware timer 103. Processor core 102 is also configured to switch its operating mode from non-root mode to root mode in response to a received timeout interrupt signal, thus completing the exit of the virtual processor core.

[0029] The interrupt controller 101 is a key hardware component in a computer system, responsible for uniformly receiving, arbitrating, and forwarding interrupt requests from all hardware peripherals (such as timers, disks, network cards, etc.) outside the processor core.

[0030] Processor core 102 refers to a computing unit used to execute software processing programs, and its specific implementation can be flexibly selected according to the deployment scenario of virtualization system 10. For example, in high-performance computing platforms such as intelligent driving domain controllers, processor core 102 can be a central processing unit (CPU), a microcontroller unit (MCU), or an embedded processing unit. This disclosure does not limit the specific type of processor core 102; this disclosure uses a CPU as an example for illustrative purposes.

[0031] Virtual CPU (vCPU) refers to the virtual CPU that is abstracted by the Hypervisor and seen from inside the virtual machine; it is a software resource.

[0032] The software program on the virtual processor core bound to processor core 102 refers to the kernel timer driver and related timer management program used to set hardware timers.

[0033] When creating a virtual machine, the one-to-one binding relationship between each vCPU and a physical processor core can be explicitly specified through hypervisor commands or configuration. For example, in a virtualization environment, this one-to-one binding between virtual machine vCPUs and physical processor cores can usually be achieved through the cgroups ccpuset controller or by using the libvirt virtualization management tool.

[0034] Non-root mode refers to a lower privilege level mode supported by CPU hardware virtualization. In this mode, the CPU directly executes instructions within the virtual machine (Guest). It can be simply understood as the CPU "acting" as the vCPU it's bound to, running the software within the virtual machine; that is, in non-root mode, the vCPU executes the software program.

[0035] Root mode is the privileged mode in which the Hypervisor runs, possessing complete control over the physical hardware.

[0036] The timeout period of the hardware timer 103 can be set according to the application software. This embodiment of the disclosure does not limit the size of the timeout period of the hardware timer 103. This embodiment of the disclosure takes a timeout period of 10ms (milliseconds) of the hardware timer 103 as an example for illustrative explanation.

[0037] In non-root mode, processor core 102 functions as if running a Guest operating system on a physical machine, executing instructions on its bound vCPU. The Guest OS directly accesses and sets the timeout of the hardware timer 103 corresponding to processor core 102 through its standard kernel timer driver. For example, the Guest OS can directly configure a 10ms timeout for the hardware timer 103 corresponding to processor core 102 via the timer driver.

[0038] In some examples, to efficiently reuse a single hardware timer 103 resource, the Guest OS driver layer can maintain a timer request queue (e.g., a software linked list) sorted by expiration time. When a new timeout needs to be set, the new timeout can be compared with the current estimated expiration time of the hardware timer 103. Based on the comparison result, it is determined whether to immediately reconfigure the hardware timer 103 or to insert the request to set the new timeout into the timer request queue for delayed processing.

[0039] Taking hardware timer 103 as an example, currently configured with a timeout of 10ms and executing the 10ms timeout. If a new timeout needs to be set, the following steps should be performed: S1. Compare the newly set timeout with the current estimated expiration time of the hardware timer 103.

[0040] S2. If the new timeout is 8ms, which expires earlier than the current 10ms, meaning 8ms is the nearest next expiration time, the timer driver will immediately reconfigure the hardware timer 103, updating its timeout to the earlier 8ms to ensure that the most recent event is responded to first.

[0041] S3. If the new timeout is 12ms, which is later than the current 10ms, the driver will not immediately change the hardware timer configuration. Instead, it will add the timer request to a software list sorted by expiration time for queuing management.

[0042] S4. After the hardware timer 103 triggers a timeout interrupt and the interrupt handling is completed, the driver will traverse and search the software linked list, retrieve the timer request with the earliest expiration time in the linked list, configure its corresponding timeout time to the hardware timer 103, and start a new round of timing.

[0043] The timeout interrupt signal is a hardware signal used to notify the CPU that an event has occurred.

[0044] When the hardware timer 103 reaches its timeout period and the hardware circuit detects this state, it immediately generates a timeout interrupt signal at its output and sends it directly to the interrupt controller 101 via physical circuitry (such as the chip's internal bus or interrupt line). The interrupt controller 101 receives the timeout interrupt signal from the hardware timer 103 through its hardware pins or interrupt status register and accurately identifies the hardware timer 103 that triggered the timeout interrupt signal based on the physical input pin or interrupt number of the signal. Subsequently, the interrupt controller 101 determines the target processor core corresponding to the interrupt based on the system's preset static binding relationship (i.e., the fixed mapping between each hardware timer and a physical processor core), and finally sends an inter-processor interrupt completion signal to the target core.

[0045] In some examples, because the hardware timer 103 has a dedicated physical output pin for sending a level or edge signal to the interrupt controller 101 when a timeout occurs, and the interrupt controller 101 has a set of dedicated physical input pins, each pin being fixedly connected to a corresponding hardware timer 103, when a hardware timer 103 times out, the generated timeout interrupt signal will drive the corresponding specific input pin on the interrupt controller 101 through its dedicated physical connection. The internal hardware logic of the interrupt controller 101 can directly sense which physical pin has generated a valid signal, thereby uniquely identifying the hardware timer 103 connected to that pin.

[0046] In other examples, when the hardware timer 103 issues a timeout interrupt signal, it is automatically or during the configuration phase assigned a globally unique interrupt vector number (interrupt number) to identify the source and type of the interrupt. When the interrupt controller 101 receives the timeout interrupt signal, its internal logic directly reads and parses the interrupt number, and queries the pre-established mapping relationship between interrupt numbers and hardware timers 103, thereby accurately determining the hardware timer 103 that generated the timeout interrupt signal.

[0047] When processor core 102 (target processor core) receives an inter-processor interrupt from interrupt controller 101, in response, the hardware of processor core 102 will switch its running mode from non-root mode to root mode, automatically save the execution state of vCPU to memory, and return the control of the processor core from the software in the virtual machine to the underlying Hypervisor, thus completing a virtual machine exit event.

[0048] The virtualization system provided in this disclosure configures a processor core to be bound one-to-one with a vCPU, and each processor core corresponds one-to-one with a hardware timer. Therefore, each vCPU exclusively uses its corresponding hardware timer. Consequently, when the hardware timer generates a timeout interrupt signal, requiring a switch from non-root mode to root mode (i.e., exiting from the vCPU to the hypervisor), there is no need to save the context or disable the hardware timer. The processor core can directly switch operating modes, and the hypervisor handles the interrupt. This significantly shortens the exit path, reduces software latency and overhead, and significantly improves the accuracy of the virtual timer, better meeting the needs of high real-time applications.

[0049] Continue to refer to Figure 1 As shown, the hardware timer 103 is specifically configured to: start timing in response to receiving a timeout setting; and determine that a timeout has occurred and generate a timeout interrupt signal in response to the timeout period being reached.

[0050] When the software writes a timeout value to a specific register of the hardware timer 103, that is, when the hardware timer 103 receives the timeout value, it can immediately clear its internal counter and start automatically incrementing the countdown. The hardware timer 103 continuously compares the value of its internal counter with the previously set timeout value. When the two are equal, the hardware timer 103 determines that a timeout has occurred and generates a timeout interrupt signal.

[0051] The virtualization system provided in this embodiment starts timing in response to receiving a timeout setting via a hardware timer; in response to the timeout reaching the set timeout, it determines that a timeout has occurred and generates a timeout interrupt signal. The hardware timer can be efficiently managed directly through the operating system, enabling vCPU exit to be triggered by an interrupt, thus creating conditions for the Hypervisor's scheduling intervention.

[0052] In some examples, after processor core 102 exits the vCPU and enters the Hypervisor, it is necessary to perform corresponding configurations based on the interrupt type of the timeout interrupt signal to implement interrupt response. Specifically, when the interrupt type of the timeout interrupt signal is a virtual interrupt, the running mode needs to be switched from Hypervisor to vCPU first, and then the corresponding interrupt response needs to be performed.

[0053] Continue to refer to Figure 1 As shown, processor core 102 is also configured to determine the interrupt type corresponding to the timeout interrupt signal in root mode; in response to the interrupt type being a virtual interrupt type, the running mode is switched from root mode to non-root mode to complete the entry of the virtual processor core.

[0054] Interrupt types can include either virtual interrupt types or hardware interrupt types.

[0055] For example, processor core 102 can determine the timeout interrupt type based on the interrupt number of the timeout interrupt signal.

[0056] In some examples, processor core 102 is specifically configured to determine the interrupt number in the timeout interrupt signal in root mode, and determine the interrupt type corresponding to the timeout interrupt signal based on the correspondence between the interrupt number and the interrupt type.

[0057] In root mode with the highest privilege (such as Hypervisor mode), processor core 102 can read the interrupt number from interrupt controller 101 or related registers, obtain the correspondence table between interrupt numbers and interrupt types maintained internally by processor core 102, and look up the interrupt type corresponding to the interrupt number from the table. For example, if the interrupt number is 26, looking up the table will show that 26 corresponds to "interrupt for Hypervisor", which is usually a physical interrupt; if the interrupt number is 27, looking up the table will show that 27 corresponds to a virtual interrupt.

[0058] In some embodiments of this disclosure, after the processor core 102 determines that the interrupt type is a virtual interrupt type, it needs to virtualize the interrupt controller 101 first, and trigger the virtual processor core to switch the operating mode through the virtual interrupt signal generated by the virtualized interrupt controller 101, and then perform interrupt response.

[0059] In some examples, processor core 102 is also configured to perform virtual interrupt injection configuration on interrupt controller 101 in response to an interrupt of type virtual interrupt; interrupt controller 101 is also configured to generate and send virtual interrupt signals in response to the virtual interrupt injection configuration; processor core 102 is also configured to process the corresponding virtual interrupt handler in response to the virtual interrupt signal after the running mode switches from root mode to non-root mode.

[0060] After processor core 102 determines that the timeout interrupt signal is a virtual interrupt, the Hypervisor running on processor core 102 first queries the interrupt mapping table of the target Guest OS (i.e., the virtual machine corresponding to the hardware timer 103 that generated this interrupt) to determine the virtual interrupt number corresponding to the timeout interrupt signal. Then, based on the interrupt affinity configured for hardware timer 103, the current vCPU state, etc., it determines the vCPU, and based on the hardware priority of the timeout interrupt signal, it determines the virtual priority. Finally, it writes the virtual interrupt number, virtual priority, target vCPU, and other fields to the internal status register of the virtual interrupt controller of the target Guest OS, completing the injection configuration.

[0061] The virtual interrupt controller can generate a virtual interrupt signal recognizable by the Guest OS in response to interrupt information write operations to the internal status register, and mark the virtual interrupt signal as pending. Simultaneously, the virtual interrupt controller can perform management operations such as interrupt arbitration, preemption scheduling, and queuing based on the priority in the interrupt information.

[0062] When the processor core 102 can switch from root mode to non-root mode, the interrupt handling logic of the Guest OS will query the status of its virtual interrupt controller. Once the virtual interrupt signal is detected, the corresponding virtual interrupt handler will be called immediately to complete the interrupt response and processing.

[0063] In this embodiment of the disclosure, the virtual interrupt handler can be a pre-defined software routine of the operating system specifically designed to handle timeout interrupts. This embodiment of the disclosure does not limit the functionality of the software routine.

[0064] The exemplary system provided in this disclosure is configured so that each processor core is bound to a vCPU one-to-one, and each processor core corresponds one-to-one with a hardware timer. Therefore, each vCPU exclusively uses a corresponding hardware timer. Consequently, when the processor core determines that the interrupt type corresponding to the timeout interrupt signal is a virtual interrupt type, the virtualized interrupt controller, in response to the virtual interrupt signal generated by the virtualized interrupt controller, needs to switch its operating mode from root mode to non-root mode. That is, when exiting from the hypervisor to the vCPU, there is no need to save the context or disable the hardware timer; the processor core can directly switch operating modes, and the vCPU handles the interrupt. This significantly shortens the exit path, reduces software latency and overhead, and significantly improves the accuracy of the virtual timer, better meeting the needs of high real-time applications.

[0065] Exemplary methods Corresponding to the virtualization system provided in the above embodiments, this disclosure also provides a method for virtualizing a hardware timer.

[0066] Figure 2 This is a flowchart illustrating a hardware timer virtualization method provided in an exemplary embodiment of this disclosure. Figure 2 As shown, this hardware timer virtualization method can be applied to, for example... Figure 1 The virtualization system 10 shown may include the following steps 201 to 204.

[0067] Step 201: Run the software program on the bound virtual processor core in non-root mode through the processor core to set the timeout of its corresponding hardware timer.

[0068] Step 202: In response to a timeout, the hardware timer generates a timeout interrupt signal and sends the timeout interrupt signal to the interrupt controller; Step 203: Receive the timeout interrupt signal through the interrupt controller and transmit the timeout interrupt signal to the processor core corresponding to the hardware timer; Step 204: By responding to the timeout interrupt signal received by the processor core, the running mode is switched from non-root mode to root mode, thus completing the exit of the virtual processor core.

[0069] like Figure 3 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 202, which generates a timeout interrupt signal in response to a timeout using a hardware timer, may include steps 2021 and 2022.

[0070] Step 2021: Respond to the received timeout setting via a hardware timer and start timing.

[0071] Step 2022: The hardware timer responds to the timeout period, determines that a timeout has occurred, and generates a timeout interrupt signal.

[0072] like Figure 4 As shown above, in the above Figure 2 Based on the illustrated embodiment, the virtualization method for the hardware timer further includes the following steps 205 and 206.

[0073] Step 205: Determine the interrupt type corresponding to the timeout interrupt signal through the processor core in root mode.

[0074] Step 206: By responding to the interrupt type as virtual interrupt by the processor core, the running mode is switched from root mode to non-root mode, thus completing the entry into the virtual processor core.

[0075] like Figure 5 As shown above, in the above Figure 4 Based on the embodiment shown, step 205 determines the interrupt type corresponding to the timeout interrupt signal through the processor core in root mode, which may include the following steps 2051 and 2052.

[0076] Step 2051: Determine the interrupt number in the timeout interrupt signal through the processor core in root mode.

[0077] Step 2052: Based on the correspondence between interrupt number and interrupt type, determine the interrupt type corresponding to the timeout interrupt signal.

[0078] like Figure 6 As shown above, in the above Figure 4 Based on the illustrated embodiment, step 206 involves the processor core responding to an interrupt of type virtual interrupt by switching the running mode from root mode to non-root mode, thereby completing the entry of the virtual processor core. This step may include steps 2061 to 2063.

[0079] Step 2061: Configure the interrupt controller to inject virtual interrupts by setting the processor core response interrupt type to virtual interrupt type.

[0080] Step 2062: Generate and send a virtual interrupt signal in response to the virtual interrupt injection configuration via the interrupt controller.

[0081] Step 2063: After the processor core switches from root mode to non-root mode in operation mode, it responds to the virtual interrupt signal and processes the corresponding virtual interrupt handler.

[0082] Regarding the hardware timer virtualization method in the above embodiments, the specific steps and corresponding beneficial effects of the hardware timer virtualization method have been described in detail in the corresponding embodiments of the aforementioned virtualization system section. Please refer to the corresponding execution operation methods and beneficial technical effects of the aforementioned exemplary virtualization system section, which will not be repeated here.

[0083] Virtualization device for exemplary hardware timers Corresponding to the hardware timer virtualization method provided in the above embodiments, this disclosure also provides a hardware timer virtualization device.

[0084] Figure 7 This is a flowchart illustrating a virtualization device for a hardware timer provided in an exemplary embodiment of this disclosure. Figure 7 As shown, the virtualization device 70 of the hardware timer may include a timeout setting module 701, a timeout interrupt triggering module 702, an interrupt transmission module 703, and a first operating mode switching module 704.

[0085] The timeout setting module 701 is used to run a software program on the bound virtual processor core through the processor core in non-root mode to set the timeout of its corresponding hardware timer.

[0086] The timeout interrupt triggering module 702 is used to generate a timeout interrupt signal in response to a timeout by using a hardware timer, and send the timeout interrupt signal to the interrupt controller. The interrupt transmission module 703 is used to receive timeout interrupt signals through the interrupt controller and transmit the timeout interrupt signals to the processor core corresponding to the hardware timer; The first operating mode switching module 704 is used to switch the operating mode from non-root mode to root mode in response to a timeout interrupt signal received by the processor core, thereby completing the exit of the virtual processor core.

[0087] In some embodiments of this disclosure, the timeout interrupt triggering module 702 is specifically used to start timing in response to receiving the timeout time setting via a hardware timer; and to determine that a timeout has occurred and generate a timeout interrupt signal in response to the timeout time reaching the set time via a hardware timer.

[0088] In some embodiments of this disclosure, the virtualization device 70 for the hardware timer further includes: The interrupt type determination module is used to determine the interrupt type corresponding to the timeout interrupt signal through the processor core in root mode.

[0089] The second operating mode switching module is used to switch the operating mode from root mode to non-root mode by responding to the interrupt type of the processor core as a virtual interrupt type, thereby completing the entry of the virtual processor core.

[0090] In some embodiments of this disclosure, the interrupt type determination module is specifically used to determine the interrupt number in the timeout interrupt signal through the processor core in root mode; and to determine the interrupt type corresponding to the timeout interrupt signal based on the correspondence between the interrupt number and the interrupt type.

[0091] In some embodiments of this disclosure, the second operating mode switching module is specifically used to configure the interrupt controller to perform virtual interrupt injection in response to the interrupt type being virtual interrupt by the processor core; to generate and send a virtual interrupt signal in response to the virtual interrupt injection configuration by the interrupt controller; and to process the corresponding virtual interrupt handler in response to the virtual interrupt signal by the processor core after switching the operating mode from root mode to non-root mode.

[0092] Regarding the virtualization device for a hardware timer in the above embodiments, the specific methods of operation of each module and the corresponding beneficial effects have been described in detail in the corresponding embodiment section of the aforementioned hardware timer virtualization method section. Please refer to the corresponding execution operation methods and beneficial technical effects in the above exemplary method section, which will not be repeated here.

[0093] Exemplary electronic devices Figure 8 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this disclosure, such as... Figure 8 As shown, the electronic device 80 may include a processor 801 and a memory 802 for storing executable instructions of the processor 801; wherein, the processor 801 is used to read executable instructions from the memory 802 and execute the instructions to implement the above-mentioned... Figures 2 to 6 The embodiment shown provides a method for virtualizing hardware timers.

[0094] The processor 801 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 80 to perform desired functions.

[0095] The memory 802 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 801 may execute the program instructions to implement the hardware timer virtualization method of the various embodiments of this disclosure described above and / or other desired functions.

[0096] In one example, the electronic device 80 may also include an input device 803 and an output device 804, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0097] Of course, for the sake of simplicity, Figure 8 Only some of the components of the electronic device 80 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 80 may include any other suitable components depending on the specific application.

[0098] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the virtualization method of the hardware timer of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0099] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0100] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the virtualization method of the hardware timer of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0101] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0102] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0103] Various modifications and variations can be made to this disclosure without departing from its spirit and scope. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A virtualization system comprising an interrupt controller, at least one processor core, and a hardware timer corresponding to each of said processor cores; wherein, The processor core is configured to be bound one-to-one with a virtual processor core; The processor core is configured to run a software program on the bound virtual processor core in non-root mode to set the timeout of its corresponding hardware timer. The hardware timer is configured to generate a timeout interrupt signal in response to a timeout and send the timeout interrupt signal to the interrupt controller; The interrupt controller is configured to receive the timeout interrupt signal and transmit the timeout interrupt signal to the processor core corresponding to the hardware timer; The processor core is also configured to switch its operating mode from the non-root mode to the root mode in response to receiving the timeout interrupt signal, thereby exiting the virtual processor core.

2. The virtualization system of claim 1, wherein, The hardware timer is configured as follows: In response to receiving the set timeout period, the timer begins; In response to the timeout period being reached, a timeout is determined and the timeout interrupt signal is generated.

3. In the virtualization system according to claim 1 or 2, the processor core is further configured to determine the interrupt type corresponding to the timeout interrupt signal in the root mode; and in response to the interrupt type being a virtual interrupt type, switch the running mode from the root mode to the non-root mode to complete the entry of the virtual processor core.

4. The virtualization system of claim 3, wherein, The processor core is specifically configured to, in the root mode, determine the interrupt number in the timeout interrupt signal; and, based on the correspondence between the interrupt number and the interrupt type, determine the interrupt type corresponding to the timeout interrupt signal.

5. The virtualization system according to claim 3, wherein the processor core is further configured to perform virtual interrupt injection configuration on the interrupt controller in response to the interrupt type being the virtual interrupt type; The interrupt controller is also configured to generate and send the virtual interrupt signal in response to the virtual interrupt injection configuration; The processor core is also configured to, in response to the virtual interrupt signal, process the corresponding virtual interrupt handler after the operating mode switches from the root mode to the non-root mode.

6. A method for virtualizing a hardware timer, applied to a virtualization system, the virtualization system comprising an interrupt controller, at least one processor core, and a hardware timer corresponding to each of the processor cores; wherein, The processor core is configured to be bound one-to-one with a virtual processor core; the method includes: In non-root mode, the processor core runs the software program bound to the virtual processor core to set the timeout of its corresponding hardware timer. In response to a timeout, the hardware timer generates a timeout interrupt signal and sends the timeout interrupt signal to the interrupt controller. The interrupt controller receives the timeout interrupt signal and transmits the timeout interrupt signal to the processor core corresponding to the hardware timer. The processor core responds to the timeout interrupt signal by switching its operating mode from non-root mode to root mode, thus completing the exit of the virtual processor core.

7. The method according to claim 6, further comprising: The processor core determines the interrupt type corresponding to the timeout interrupt signal in the root mode. The processor core responds to the interrupt type being virtual interrupt type by switching the running mode from root mode to non-root mode, thus completing the entry of the virtual processor core.

8. The method according to claim 7, further comprising: The processor core responds to the interrupt type as the virtual interrupt type and configures the interrupt controller to perform virtual interrupt injection. The interrupt controller generates and sends the virtual interrupt signal in response to the virtual interrupt injection configuration. After the processor core switches from the root mode to the non-root mode, it responds to the virtual interrupt signal and processes the corresponding virtual interrupt handler.

9. An electronic device, comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the virtualization method of the hardware timer according to any one of claims 6-8.

10. A computer-readable storage medium storing a computer program, which, when executed by a processor, performs the virtualization method of the hardware timer according to any one of claims 6-8.

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