MOS manufacturing method and MOS device

Abstract

The embodiment of the application provides a MOS preparation method and a MOS device. In the process of diffusing the doped impurities in the anti-static layer, the first polysilicon filling in the first groove and the second groove is not affected, and then the drain-source saturation current IDSS is improved. The application is aimed at the shortcomings of high on-resistance and large chip area of the LDMOS, combines the advantages of the trench field effect transistor, optimizes the process of the anti-static layer, and realizes a front drain trench MOS preparation method which can increase the current density, reduce the on-resistance per unit chip area, and improve the drain-source saturation current IDSS.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a MOS fabrication method and a MOS device. Background Technology

[0002] like Figure 1 As shown, laterally diffused metal-oxide-semiconductor (LDMOS) has a lightly doped N-drift region between the drain and the channel to withstand reverse voltage. The higher the breakdown voltage, the longer the drift region needs to be, which directly occupies a large amount of chip area and increases the resistance of the current path. The current in LDMOS flows only laterally on the chip surface, resulting in a very small conductive cross-sectional area. Furthermore, the P-body region and N+ source region form a JFET (junction field-effect transistor) region, introducing additional resistance. This leads to disadvantages of LDMOS, such as high on-resistance, low current density, and large chip area.

[0003] The conventional antistatic structure process is as follows: silicon nitride, oxide layer, polysilicon deposition → high-concentration P-type implantation → antistatic layer photolithography → polysilicon removal → oxide layer and silicon nitride removal → photoresist removal → antistatic layer diffusion.

[0004] From the above process flow and as... Figure 2 As can be seen from the schematic diagram, if the filling control of the polysilicon in the front trench is not good, cracks may exist. The diffusion oxidation of the discharge layer will cause the polysilicon seam to be opened up, weakening the gate's control over the lower channel and locally shortening the effective channel length, thus leading to abnormal drain-source saturation current IDSS. Summary of the Invention

[0005] To address or mitigate the problems existing in the prior art, embodiments of this application provide a MOS fabrication method, including:

[0006] Multiple spaced first trenches and second trenches are formed by etching an epitaxial layer, wherein the epitaxial layer is disposed on the upper surface of a substrate, and both the epitaxial layer and the substrate are N-type doped.

[0007] A first oxide layer is grown in the first trench and the second trench, then the first oxide layer is removed, and a second oxide layer is grown on the side of the first trench and the second trench, and then a first polysilicon is deposited in the first trench and the second trench.

[0008] The epitaxial layer is photolithographically etched, and then ion implantation is performed in the regions where the first trench and the second trench are located to form a first P-type implantation region;

[0009] A nitride layer, a third oxide layer, and a P-type polycrystalline silicon are formed sequentially from bottom to top on the upper surface of the epitaxial layer;

[0010] Photolithography is performed on the P-type polysilicon, followed by etching of the P-type polysilicon, the third oxide layer, and the nitride layer in sequence, leaving only the nitride layer, the third oxide layer, and the P-type polysilicon on the upper surface of the epitaxial layer located on the side of the first P-type implantation region, so as to form an antistatic layer;

[0011] Ion implantation is performed on the region of the P-type polysilicon near the first trench and the region between the first trench to form a first N-type implantation region and a second N-type implantation region, respectively.

[0012] A dielectric layer is deposited on the upper surface of the epitaxial layer and the upper surface of the antistatic layer, and a third trench is formed in the region of the second trench away from the first trench, the third trench extending into the substrate;

[0013] A third N-type injection region is formed at the bottom of the third trench;

[0014] A first contact hole and a second contact hole are formed in the second P-type implantation region and the first N-type implantation region of the P-type polysilicon, a third contact hole is formed between the first trenches, and a fourth contact hole is formed in the second trenches.

[0015] A third P-type injection region is formed at the bottom of the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole;

[0016] A barrier layer is deposited on the side of the third trench, and then the third trench is filled with a first metal;

[0017] A second metal is deposited on the upper surface of the dielectric layer, and then the second metal is photolithographically etched and etched to form a gate lead metal, a source lead metal, a drain lead metal, a second P-type implantation region lead metal, and a first N-type implantation region lead metal.

[0018] As a preferred embodiment of this application, before etching the epitaxial layer to form a plurality of spaced first trenches and second trenches, the process includes:

[0019] A fourth oxide layer is grown on the epitaxial layer, and then the fourth oxide layer is subjected to photolithography and etching to remove the photoresist.

[0020] In a preferred embodiment of this application, the injection energy of the first P-type injection region is 30 KeV to 200 KeV, and the injection dose ranges from 1E12 to 1E14.

[0021] In a preferred embodiment of this application, the P-type polycrystalline silicon is obtained by ion implantation, specifically including:

[0022] The second polysilicon was ion implanted to form P-type polysilicon, with an implantation energy of 20 KeV to 40 KeV and an implantation dose range of 1E13 to 5E14.

[0023] As a preferred embodiment of this application, before etching the P-type polysilicon, the process specifically includes:

[0024] The P-type polycrystalline silicon is subjected to ion propulsion at a propulsion temperature of 1000℃~1200℃.

[0025] In a preferred embodiment of this application, the ion implantation energy for the P-type polycrystalline silicon near the first trench and between the first trench is 40 KeV to 110 KeV, the implantation dose range is 5E14 to 5E15, and the propulsion temperature of the implanted ions is 900°C to 950°C.

[0026] In a preferred embodiment of this application, the substrate doping concentration is greater than the epitaxial layer doping concentration.

[0027] In a second aspect, embodiments of this application also provide a MOS device, fabricated by the method described in any one of the first aspects, comprising: a substrate and an epitaxial layer;

[0028] The epitaxial layer has a first trench and a second trench, and the first trench and the second trench are filled with a first polycrystalline silicon.

[0029] A first P-type injection region is provided in the epitaxial layer, and the first trench and the second trench are provided in the first P-type injection region;

[0030] An antistatic layer is provided on the upper surface of the epitaxial layer in the region on one side of the first P-type injection region, and the first P-type injection region is located on the side of the first trench away from the second trench.

[0031] The antistatic layer comprises, from bottom to top, a nitride layer, a third oxide layer, and P-type polysilicon. The P-type polysilicon contains a second P-type implantation region and a first N-type implantation region. A second N-type implantation region is provided between the first trenches, and the depth of the second N-type implantation region is less than that of the first P-type implantation region.

[0032] A dielectric layer is deposited on the upper surface of the epitaxial layer and the upper surface of the antistatic layer. A third trench is formed in the region of the second trench away from the first trench. The third trench extends into the substrate. A barrier layer is deposited on the side of the third trench. The third trench is filled with a first metal. A third N-type implantation region is provided at the bottom of the third trench.

[0033] The second P-type injection region and the first N-type injection region are respectively provided with a first contact hole and a second contact hole, a third contact hole is formed between the first trenches, the third contact hole extends into the first P-type injection region, and a fourth contact hole is provided in the second trench. The first contact hole, the second contact hole, the third contact hole and the fourth contact hole all penetrate the dielectric layer.

[0034] A third P-type injection area is provided at the bottom of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole;

[0035] The upper surface of the dielectric layer is provided with gate lead-out metal, source lead-out metal, drain lead-out metal, second P-type injection region lead-out metal and first N-type injection region lead-out metal at intervals;

[0036] The second P-type injection region lead-out metal is connected to the second P-type injection region lead-out metal filled in the first contact hole, the first N-type injection region lead-out metal is connected to the second N-type injection region lead-out metal filled in the second contact hole, the source lead-out metal is connected to the source lead-out metal filled in the third contact hole, the gate lead-out metal is connected to the gate lead-out metal filled in the fourth contact hole, and the drain lead-out metal is connected to the first metal.

[0037] Compared with existing technologies, the embodiments of this application do not affect the morphology of the first polysilicon filled in the first and second trenches during the diffusion of doped impurities in the antistatic layer, thereby improving the drain-source saturation current (IDSS). Addressing the drawbacks of LDMOS such as high on-resistance and large chip area, this application combines the advantages of trench field-effect transistors and optimizes the antistatic layer process to achieve a front-side drain trench MOS fabrication method that increases current density, reduces on-resistance per unit chip area, and improves the drain-source saturation current (IDSS). Attached Figure Description

[0038] Non-limiting and non-exhaustive embodiments of the invention are described by way of example with reference to the following figures, wherein:

[0039] Figure 1 A cross-sectional view of a MOS device provided by the prior art is shown;

[0040] Figure 2 A cross-sectional view of a MOS device obtained using a process provided by the prior art is shown.

[0041] Figures 3 to 13 Cross-sectional views of each step in the MOS fabrication process are shown. Detailed Implementation

[0042] To make the above and other features and advantages of the present invention clearer, the invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explanation to those skilled in the art and are exemplary only, not restrictive.

[0043] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] In the embodiments of this application, the main difference between N-type doping and P-type doping lies in the type of impurity, the conductive carriers, and the type of semiconductor formed.

[0046] N-type doping is achieved by incorporating pentavalent elements (such as phosphorus or arsenic) into a semiconductor. These elements provide additional electrons, giving the semiconductor good electronic conductivity and a negative charge. In N-type semiconductors, the primary charge carriers are electrons.

[0047] P-type doping is achieved by incorporating trivalent elements (such as boron). These elements create holes in the semiconductor, which carry a positive charge, causing the P-type semiconductor to exhibit electrical conductivity. In P-type semiconductors, the dominant charge carriers are holes.

[0048] In a first aspect, embodiments of this application provide a method for fabricating a MOS, comprising:

[0049] Step S101: Etching the epitaxial layer 2 to form multiple spaced first trenches 3 and second trenches 4, wherein the epitaxial layer 2 is disposed on the upper surface of the substrate 1, and both the epitaxial layer 2 and the substrate 1 are N-type doped.

[0050] It should be noted that the reference Figure 3 First, a fourth oxide layer with a thickness of 1000 Å to 5000 Å needs to be grown on the surface of the epitaxial layer 2 using a thermal growth process. The fourth oxide layer is then photolithographically etched and etched. The photoresist used in the photolithography is then removed. In the epitaxial layer 2 corresponding to the openings etched into the fourth oxide layer, a first trench 3 and a second trench 4 are formed through an etching process. The remaining fourth oxide layer is then removed by etching. Multiple first trenches 3 and second trenches 4 are spaced apart. The first trenches 3 and second trenches 4 are used to bring out the gate. The width of the first trenches 3 and second trenches 4 is 0.1 μm to 0.5 μm, and the depth is 0.5 μm to 5 μm. The depth of the second trench 4 is greater than the depth of the first trench 3. The doping concentration of the substrate 1 is greater than the doping concentration of the epitaxial layer 2.

[0051] Step S102: A first oxide layer is grown on the side of the first trench 3 and the second trench 4, then the first oxide layer is removed, and a second oxide layer 5 is grown on the side of the first trench 3 and the second trench 4, and then a first polysilicon 6 is deposited in the first trench 3 and the second trench 4.

[0052] It should be noted that the reference Figure 4 A first oxide layer, a sacrificial oxide layer, is grown on the sides of the first trench 3 and the second trench 4 using a thermal growth process. This first oxide layer grows on both the surface of the epitaxial layer 2 and the sides of the first trench 3 and the second trench 4. Various defects may exist on the surfaces of the first trench 3 and the second trench 4, such as particles, metal contamination, organic contamination, native oxide films, and micro-roughness, which can severely affect device quality and yield. During its growth, the sacrificial oxide layer can cover some of the initial surface defects to a certain extent. The sacrificial oxide layer may also encapsulate some contaminants during its growth; subsequent etching to remove the sacrificial oxide layer effectively removes these contaminants, reducing the impact of silicon wafer surface defects on subsequent device manufacturing.

[0053] After repairing the side surface of the first trench 3 with the first oxide layer, the second oxide layer 5 is grown on the side surface of the first trench 3 and the second trench 4 and on the upper surface of the epitaxial layer 2 by a thermal growth process. The second oxide layer 5 is a gate oxide layer. Finally, the first polysilicon 6 is deposited in the first trench 3 and the second trench 4 by a deposition process. Then, the first polysilicon 6 is etched back by an etching process to remove the first polysilicon 6 on the upper surface of the epitaxial layer 2. Only the second oxide layer 5 remains on the upper surface of the epitaxial layer 2.

[0054] Step S103: Photolithography is performed on the epitaxial layer 2, and then ion implantation is performed in the region where the first trench 3 and the second trench 4 are located to form the first P-type implantation region 7.

[0055] It should be noted that the reference Figure 5 First, the epitaxial layer 2 is photolithographically etched to facilitate ion implantation. Then, a high concentration of P-type impurities is implanted through the ion implantation process to form the first P-type implantation region 7, in preparation for the formation of the source region. The implantation energy is 30 KeV to 200 KeV, and the implantation dose range is 1E12 to 1E14. Finally, the photoresist used for photolithography on the epitaxial layer 2 is removed.

[0056] Step S104: A nitride layer 8, a third oxide layer 9, and a P-type polysilicon 10 are formed sequentially from bottom to top on the upper surface of the epitaxial layer 2.

[0057] It should be noted that the reference Figure 6 A silicon nitride layer with a thickness of 100 Å to 400 Å, a third oxide layer with a thickness of 1000 Å to 3000 Å, and a second polysilicon layer with a thickness of 4000 Å to 8000 Å are deposited on the surface of the second oxide layer 5 by a deposition process. Then, a high-concentration P-type impurity implantation process is performed to form P-type polysilicon 10. The implantation energy of P-type polysilicon 10 is 20 KeV to 40 KeV, and the implantation dose ranges from 1E13 to 5E14.

[0058] Step S105: Photolithography is performed on the P-type polysilicon 10, and then the P-type polysilicon 10, the third oxide layer 9 and the nitride layer 8 are etched sequentially, leaving only the nitride layer 8, the third oxide layer 9 and the P-type polysilicon 10 on the upper surface of the epitaxial layer 2 on one side of the first P-type implantation region 7, so as to form an antistatic layer.

[0059] It should be noted that the reference Figure 7 First, the P-type polysilicon 10 is photolithographically etched and etched back. Then, the photoresist used for photolithography on the P-type polysilicon 10 is removed. Finally, a portion of the nitride layer 8 and the third oxide layer 9 on the upper surface of the epitaxial layer 2 are removed by photolithography and etching processes, leaving only the nitride layer 8 and the third oxide layer 9 on the side of the first P-type implantation region on the upper surface of the epitaxial layer 2. That is, only the nitride layer 8 and the third oxide layer 9 in the region where the P-type polysilicon 10 is located are retained. The anti-static layer can protect the second oxide layer 5 (gate oxide layer) from electrostatic breakdown and improve the surge and electrostatic reliability of the device in production, assembly, and application. The anti-static layer integrates a bidirectional protection structure (such as a back-to-back diode) between the gate and the source, providing a low-resistance discharge channel. When electrostatic discharge occurs, the structure is instantly turned on, clamping the voltage within the safe range of 6-15V. When the anti-static layer is present, the current path is: charge - gate - ESD protection structure - source (zero damage to the gate oxide layer).

[0060] The P-type polycrystalline silicon provided in this application embodiment is obtained by ion implantation, specifically including: ion implantation of a second polycrystalline silicon to form P-type polycrystalline silicon, with an implantation energy of 20 KeV to 40 KeV and an implantation dose range of 1E13 to 5E14.

[0061] Before etching the P-type polysilicon, the specific steps include:

[0062] The P-type polycrystalline silicon is subjected to ion propulsion at a temperature of 1000℃~1200℃ for a duration of approximately 10~60 minutes.

[0063] Step S106: Ion implantation is performed on the side of the P-type polysilicon 10 near the first trench 3 and between the first trench 3 to form a first N-type implantation region 11 and a second N-type implantation region 12, respectively.

[0064] It should be noted that the reference Figure 8 Ion implantation is performed on the P-type polysilicon 10 near the first trench 3 and between the first trench 3, using a high concentration of N-type impurities. The implantation energy is 40 KeV to 110 KeV, and the implantation dose ranges from 5E14 to 5E15. Ion propulsion is then carried out at a temperature of 900°C to 950°C for a duration of 20 to 40 minutes. This forms a first N-type implantation region 11 and a second N-type implantation region 12. The depth of the second N-type implantation region 12 is less than the depth of the first P-type implantation region 7.

[0065] Step S107: Deposit a dielectric layer on the upper surface of the epitaxial layer 2 and the upper surface of the antistatic layer, and form a third trench 15 in the region of the second trench 4 away from the first trench 3, the third trench 15 extending into the substrate 1;

[0066] It should be noted that a dielectric layer is deposited on the upper surface of the antistatic layer and the upper surface of the epitaxial layer 2 through a deposition process. Then, a third trench 15 is formed in the region of the second trench 4 away from the first trench 3 using photolithography and dry etching processes. The third trench 15 extends into the substrate 1. The dry etching angle is 85°~90°, and the etching depth depends on the barrier layer's filling capability. The dielectric layer sampling dual-layer structure (upper dielectric layer 13 and lower dielectric layer 14) in this embodiment is designed to balance via planarization, ion contamination protection, and material isolation, with each layer performing its specific function and complementing each other's advantages.

[0067] The upper dielectric layer 14 is a boron- and phosphorus-containing silicon glass, which has excellent fluidity and reflow capability at high temperatures. It can effectively fill high aspect ratio contact holes, achieve local surface planarization, and ensure the process window for subsequent photolithography and etching. At the same time, phosphorus can absorb mobile ions (such as Na+), improving device reliability.

[0068] The lower dielectric layer 13 is undoped with SiO2, is dense and has high chemical stability. It acts as a "barrier" to prevent boron and phosphorus from diffusing and contaminating the active region or gate below during BPSG reflow or subsequent thermal processes, thus avoiding drift of key parameters such as threshold voltage.

[0069] Step S108: A third N-type injection region 16 is formed at the bottom of the third trench 15;

[0070] It should be noted that the reference Figure 10 High-concentration N-type implantation is performed at the bottom of the third trench 15 using an ion implantation process to form the third N-type implantation region 16, with an implantation angle of 0°~45°. The resistance can be reduced through the third N-type implantation region 12.

[0071] Step S109: A first contact hole 17 and a second contact hole 18 are formed in the second P-type implantation region 10 and the first N-type implantation region 11 of the P-type polysilicon 10, a third contact hole 19 is formed between the first trenches 3, and a fourth contact hole 20 is formed in the second trenches 4.

[0072] For further explanation, please refer to the following: Figure 11 Through photolithography and dry etching processes, a first contact hole 17 and a second contact hole 18 are formed correspondingly in the second P-type injection region and the first N-type injection region of the P-type polysilicon 10. A third contact hole 19 is formed between the first trenches 3, and a fourth contact hole 20 is formed in the second trench 4. The first contact hole 17 and the second contact hole 18 are mainly used to bring out the PN junction formed between the second P-type injection region 10 and the first N-type injection region 11. The third contact hole 19 is formed between the first trenches 3 to bring out the source electrode. The fourth contact hole 20 is formed in the second trench 4 to bring out the gate electrode.

[0073] Step S110: A third P-type injection region 21 is formed at the bottom of the first contact hole 17, the second contact hole 18, the third contact hole 19 and the fourth contact hole 20;

[0074] For further explanation, please refer to the following: Figure 11 P-type impurities are implanted at the bottom of the first contact hole 17, the second contact hole 18, the third contact hole 19 and the fourth contact hole 20 by ion implantation to form a third P-type implantation region 21. The third P-type implantation region 21 can reduce the electric field at the bottom of the trench, increase the breakdown voltage, suppress channel punch-through, and improve leakage current, etc.

[0075] Step S111: Deposit a barrier layer 22 on the side of the third trench 15, and then fill the third trench 15 with a first metal;

[0076] It should be noted that the reference Figure 12 A barrier layer 22 is deposited on the side of the third trench 15, followed by filling the third trench 15 with a first metal. In semiconductor metallization / interconnection processes, this involves first depositing an ultra-thin, continuous, conformal barrier layer (Barrier / Liner) on the side of high aspect ratio structures such as contact holes, vias, trenches, and TSVs, and then filling with the main conductive tungsten metal. The barrier layer prevents the conductive tungsten metal from diffusing into SiO2 / low-k dielectric / silicon, avoiding leakage, junction failure, and device performance degradation. It also allows the metal to bond firmly to the dielectric / silicon, preventing delamination and peeling. Furthermore, it provides a uniform nucleation surface, reduces voids, and improves the filling quality of high aspect ratio structures.

[0077] In step S112, a second metal is deposited on the upper surface of the dielectric layer, and then the second metal is photolithographically etched and etched to form the gate lead metal 26, the source lead metal 25, the drain lead metal 27, the second P-type implantation region lead metal 23, and the second N-type implantation region lead metal 24.

[0078] It should be noted that the reference Figure 13 First, a second metal is deposited, followed by photolithography and etching of the second metal, then photoresist removal, and then a passivation layer 28 is deposited on the upper surface of the second metal. The passivation layer is then photolithographically etched and etched to prevent the gate lead metal 26, source lead metal 25, drain lead metal 27, second P-type implantation region lead metal 23, and second N-type implantation region lead metal 24 from being interconnected.

[0079] Secondly, such as Figure 13 As shown, this application embodiment also provides a MOS device, which is fabricated by the method described in the first aspect, including: a substrate 1 and an epitaxial layer 2;

[0080] The epitaxial layer has a first trench 3 and a second trench 4, and the first trench 3 and the second trench 4 are filled with a first polycrystalline silicon 6.

[0081] A first P-type injection region 7 is provided in the epitaxial layer 2, and the first trench 3 and the second trench 4 are provided in the first P-type injection region 7;

[0082] An antistatic layer is provided on the upper surface of the epitaxial layer 2 near the first P-type injection region 7; the first P-type injection region 7 is located on the side of the first trench 3 away from the second trench 4.

[0083] The antistatic layer comprises, from bottom to top, a nitride layer 8, a third oxide layer 9, and a P-type polycrystalline silicon. The P-type polycrystalline silicon contains a second P-type implantation region 10 and a first N-type implantation region 11. A second N-type implantation region 12 is provided between the first trenches 3, and the depth of the second N-type implantation region 12 is less than that of the first P-type implantation region 7.

[0084] A dielectric layer is deposited on the upper surface of the epitaxial layer 2 and the upper surface of the antistatic layer. A third trench 15 is formed in the region of the second trench 4 away from the first trench 1. The third trench 15 extends into the substrate 1. A barrier layer 22 is deposited on the side of the third trench 15. The third trench 15 is filled with a first metal. A third N-type implantation region 16 is provided at the bottom of the third trench 15.

[0085] The second P-type injection region 10 and the first N-type injection region 11 are respectively provided with a first contact hole 17 and a second contact hole 18. A third contact hole 19 is provided between the first trenches 4. The third contact hole 19 extends into the first P-type injection region 7. A fourth contact hole 20 is provided in the second trenches 4. The first contact hole 17, the second contact hole 18, the third contact hole 19 and the fourth contact hole 20 all penetrate the dielectric layer.

[0086] The bottom of the first contact hole 17, the second contact hole 18, the third contact hole 19 and the fourth contact hole 20 are provided with a third P-type injection area 21;

[0087] The upper surface of the dielectric layer is provided with a gate lead-out metal 26, a source lead-out metal 25, a drain lead-out metal 27, a second P-type injection region lead-out metal 23, and a first N-type injection region lead-out metal 24 at intervals.

[0088] The second P-type injection region lead-out metal 23 is connected to the second P-type injection region lead-out metal filled in the first contact hole 17, the second N-type injection region lead-out metal 24 is connected to the first N-type injection region lead-out metal filled in the second contact hole 18, the source lead-out metal 25 is connected to the source lead-out metal filled in the third contact hole 19, the gate lead-out metal 26 is connected to the gate lead-out metal filled in the fourth contact hole 20, and the drain lead-out metal 27 is connected to the first metal.

[0089] This application embodiment improves the drain-source saturation current (IDSS) by adjusting the antistatic layer fabrication process: silicon nitride, third oxide layer, polysilicon deposition → high-concentration P-type implantation → ESD lithography → first polysilicon removal → photoresist removal → ESD diffusion → third oxide layer, silicon nitride removal. The diffusion oxidation process does not affect the morphology of the first polysilicon in the trench.

[0090] This application addresses the drawbacks of LDMOS, such as high on-resistance and large chip area, by combining the advantages of trench MOS. In LDMOS, the current flows laterally across the entire drift region, resulting in a long path and high resistance. In trench MOS, the current can flow not only laterally across the surface but also vertically along the trench sidewalls. Furthermore, multiple trench gates can be fabricated within a single cell, allowing for the parallel connection of multiple conductive channels, significantly increasing the drive current and reducing on-resistance. Through optimization of the antistatic layer process, a front-side drain trench MOS fabrication method is achieved, which increases current density, reduces on-resistance per unit chip area, and improves the drain-source saturation current (IDSS).

[0091] The technical features of the above implementation schemes can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above implementation schemes are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] Although the invention has been described in conjunction with embodiments, those skilled in the art will understand that the above description and drawings are exemplary and not restrictive, and the invention is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the invention.

Claims

1. A method for fabricating a MOS, characterized in that, include: Multiple spaced first trenches and second trenches are formed by etching an epitaxial layer, wherein the epitaxial layer is disposed on the upper surface of a substrate, and both the epitaxial layer and the substrate are N-type doped. A first oxide layer is grown in the first trench and the second trench, then the first oxide layer is removed, and a second oxide layer is grown on the side of the first trench and the second trench, and then a first polysilicon is deposited in the first trench and the second trench. The epitaxial layer is photolithographically etched, and then ion implantation is performed in the regions where the first trench and the second trench are located to form a first P-type implantation region; A nitride layer, a third oxide layer, and a P-type polycrystalline silicon are formed sequentially from bottom to top on the upper surface of the epitaxial layer; Photolithography is performed on the P-type polysilicon, followed by etching of the P-type polysilicon, the third oxide layer, and the nitride layer in sequence, leaving only the nitride layer, the third oxide layer, and the P-type polysilicon on the upper surface of the epitaxial layer located on the side of the first P-type implantation region, so as to form an antistatic layer; Ion implantation is performed on the region of the P-type polysilicon near the first trench and the region between the first trench to form a first N-type implantation region and a second N-type implantation region, respectively. A dielectric layer is deposited on the upper surface of the epitaxial layer and the upper surface of the antistatic layer, and a third trench is formed in the region of the second trench away from the first trench, the third trench extending into the substrate; A third N-type injection region is formed at the bottom of the third trench; A first contact hole and a second contact hole are formed in the second P-type implantation region and the first N-type implantation region of the P-type polysilicon, a third contact hole is formed between the first trenches, and a fourth contact hole is formed in the second trenches. A third P-type injection region is formed at the bottom of the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole; A barrier layer is deposited on the side of the third trench, and then the third trench is filled with a first metal; A second metal is deposited on the upper surface of the dielectric layer, and then the second metal is photolithographically etched and etched to form a gate lead metal, a source lead metal, a drain lead metal, a second P-type implantation region lead metal, and a first N-type implantation region lead metal.

2. The MOS fabrication method according to claim 1, characterized in that, Before etching the epitaxial layer to form multiple spaced first and second trenches, the process includes: A fourth oxide layer is grown on the epitaxial layer, and then the fourth oxide layer is subjected to photolithography and etching to remove the photoresist.

3. The MOS fabrication method according to claim 1, characterized in that, The injection energy of the first P-type injection region is 30 KeV to 200 KeV, and the injection dose ranges from 1E12 to 1E14.

4. The MOS fabrication method according to claim 1, characterized in that, The P-type polycrystalline silicon is obtained through ion implantation, specifically including: The second polysilicon was ion implanted to form P-type polysilicon, with an implantation energy of 20 KeV to 40 KeV and an implantation dose range of 1E13 to 5E14.

5. The MOS fabrication method according to claim 4, characterized in that, Before etching the P-type polysilicon, the specific steps include: The P-type polycrystalline silicon is subjected to ion propulsion at a propulsion temperature of 1000℃~1200℃.

6. The MOS fabrication method according to claim 1, characterized in that, The ion implantation energy for the P-type polycrystalline silicon near the first trench and between the first trench is 40 KeV to 110 KeV, the implantation dose range is 5E14 to 5E15, and the propulsion temperature of the implanted ions is 900℃ to 950℃.

7. The MOS fabrication method according to claim 1, characterized in that, The substrate doping concentration is greater than the epitaxial layer doping concentration.

8. A MOS device, characterized in that, Prepared by the method according to any one of claims 1 to 7, comprising: a substrate and an epitaxial layer; The epitaxial layer has a first trench and a second trench, and the first trench and the second trench are filled with a first polycrystalline silicon. A first P-type injection region is provided in the epitaxial layer, and the first trench and the second trench are provided in the first P-type injection region; An antistatic layer is provided on the upper surface of the epitaxial layer in the region on one side of the first P-type injection region, and the first P-type injection region is located on the side of the first trench away from the second trench. The antistatic layer comprises, from bottom to top, a nitride layer, a third oxide layer, and P-type polysilicon. The P-type polysilicon contains a second P-type implantation region and a first N-type implantation region. A second N-type implantation region is provided between the first trenches, and the depth of the second N-type implantation region is less than that of the first P-type implantation region. A dielectric layer is deposited on the upper surface of the epitaxial layer and the upper surface of the antistatic layer. A third trench is formed in the region of the second trench away from the first trench. The third trench extends into the substrate. A barrier layer is deposited on the side of the third trench. The third trench is filled with a first metal. A third N-type implantation region is provided at the bottom of the third trench. The second P-type injection region and the first N-type injection region are respectively provided with a first contact hole and a second contact hole, a third contact hole is formed between the first trenches, the third contact hole extends into the first P-type injection region, and a fourth contact hole is provided in the second trench. The first contact hole, the second contact hole, the third contact hole and the fourth contact hole all penetrate the dielectric layer. A third P-type injection area is provided at the bottom of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole; The upper surface of the dielectric layer is provided with gate lead-out metal, source lead-out metal, drain lead-out metal, second P-type injection region lead-out metal and first N-type injection region lead-out metal at intervals; The second P-type injection region lead-out metal is connected to the second P-type injection region lead-out metal filled in the first contact hole, the first N-type injection region lead-out metal is connected to the second N-type injection region lead-out metal filled in the second contact hole, the source lead-out metal is connected to the source lead-out metal filled in the third contact hole, the gate lead-out metal is connected to the gate lead-out metal filled in the fourth contact hole, and the drain lead-out metal is connected to the first metal.

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