A real-time control system, method, medium, and electronic equipment for high-precision multi-group parallel motion model testing of power systems.

Abstract

This invention discloses a high-precision real-time control system and method for multiple parallel dynamic model tests in a power system. The system includes: a dynamic model test control unit, a field-programmable gate array (FPGA) real-time controller, and an actuator unit. The dynamic model test control unit is used to manage tasks for multiple sets of dynamic model tests, assign corresponding control tasks to each set of dynamic model tests, and send the control tasks to the FPGA real-time controller. The FPGA real-time controller is used to divide the test into independent logic control domains corresponding to the multiple sets of dynamic model tests, execute the control tasks based on the independent logic control domains, and output independent control instructions for each set of dynamic model tests. The actuator unit is used to independently control the switching action of the corresponding dynamic model test based on the independent control instructions for each set of dynamic model tests.

Description

Technical Field

[0001] This invention relates to the field of electrical engineering technology, and more specifically, to a real-time control system, method, medium, and electronic equipment for high-precision multi-group parallel motion model testing of power systems. Background Technology

[0002] Dynamic physical simulation (DPMS) of power systems is an important means of studying transient processes in power systems, verifying the performance of relay protection devices, and analyzing system stability characteristics. DPMS tests simulate various operating conditions and fault scenarios under laboratory conditions by constructing a physical model similar to the actual power system.

[0003] The existing dynamic model test control system has the following main technical limitations: (1) Insufficient timing control precision: Existing systems mostly use microcontrollers or PLCs to implement switch control, with a time resolution of 10-100ms, which is difficult to meet the timing requirements of high-precision fault simulation.

[0004] (2) Lack of ability to conduct multiple parallel tests: Traditional systems are mostly designed for single-group tests and cannot support multiple independent tests at the same time. The equipment utilization rate is low and the test efficiency is limited.

[0005] (3) Single triggering method: The existing system mainly supports immediate triggering and simple delayed triggering, lacking advanced triggering modes such as closing angle synchronous triggering and GPS time synchronous triggering.

[0006] (4) Insufficient isolation and security: There is a lack of effective electrical isolation and resource mutual exclusion mechanisms when multiple parallel tests are conducted, which poses a safety hazard. Summary of the Invention

[0007] This invention proposes a high-precision real-time control system and method for multiple parallel dynamic simulation tests in power systems, in order to solve the problem of how to provide a high-precision real-time control for multiple parallel dynamic simulation tests in power systems.

[0008] To address the aforementioned problems, according to one aspect of the present invention, a high-precision real-time control system for multi-group parallel dynamic model testing in a power system is provided, the system comprising: a dynamic model testing control unit, a field-programmable gate array (FPGA) real-time controller, and an actuator unit; The dynamic model test control unit is used to manage multiple sets of dynamic model tests, assign corresponding control tasks to each set of dynamic model tests, and send the control tasks to the FPGA real-time controller. The FPGA real-time controller is used to divide the system into independent logic control domains corresponding to multiple sets of dynamic model tests, and to execute the control task based on the independent logic control domains, outputting independent control instructions for each set of dynamic model tests. The actuator unit is used to independently control the switching action of the corresponding dynamic model test based on the independent control command of each group of dynamic model tests.

[0009] Preferably, the FPGA real-time controller uses a ≥100MHz active crystal oscillator as the system clock, and performs timing control on the independent control commands based on the system clock.

[0010] Preferably, each independent logic control domain corresponds one-to-one with a group of dynamic model tests; The independent logic control domain includes an independent timing register, a source selector, and an output channel; the independent timing register is used to provide dedicated timing for the independent logic control domain, the source selector is used to determine the control source of the independent logic control domain, and the output channel is used to output independent control commands corresponding to the dynamic model test; The actuator unit includes an independent execution module corresponding to each group of dynamic model tests. Each independent execution module includes an independent power circuit, and the power circuits of each group of dynamic model tests are electrically isolated from each other.

[0011] Preferably, the independent logic control domain is used to support multiple triggering modes, including: immediate triggering, external switch triggering, closing angle triggering, GPS / BeiDou time triggering, and hard input triggering.

[0012] Preferably, the dynamic model test control unit manages multiple sets of dynamic model tests based on a dynamic resource allocation mechanism, including: Each group of dynamic model tests is dynamically allocated and exclusively uses resources, including: One FPGA control channel corresponding to the independent logic control domain, a corresponding quantitative digital output port, and a corresponding quantitative analog input port; One GPS / BeiDou time synchronization channel is provided for use by the independent logic control domain; And a set of independent execution modules corresponding to the execution unit.

[0013] Preferably, the FPGA real-time controller executes the control task based on three-level mutual exclusion control, including: Level 1: Software allocation is mutually exclusive, and the access and locking of physical resources are determined by the dynamic model test control unit; Level 2: Hardware bus isolation, achieving hardware-level parallelism without interference through the independent logic control domain; Level 3: Timing safety lockout, which uses a hard logic mutex gate set at the output of the FPGA real-time controller to intercept dangerous instructions by timing constraints.

[0014] Preferably, the actuator unit includes: an intermediate relay, a high-precision AC contactor, and a thyristor module; The intermediate relay is used to receive independent control commands output by the FPGA real-time controller and convert the independent control commands into control signals to achieve electrical isolation of the control signals and amplification of drive power. The high-precision AC contactor is used to control the switching of the primary circuit of the dynamic model test based on the power-amplified control signal. The thyristor module is used to enable the rapid execution of the fault point switch and phase selection switch in the dynamic model test based on the control signal after power amplification.

[0015] Preferably, the FPGA real-time controller employs a dual-layer timing compensation algorithm of static pre-compensation + dynamic closed-loop correction to control the relative time error of the switching action of the actuator unit to ≤1ms, wherein: The static pre-compensation is to pre-calibrate the inherent operating delay of the intermediate relay, high-precision AC contactor or thyristor module in the actuator unit, and store the inherent operating delay as a compensation parameter in the dynamic model test control unit. When the FPGA real-time controller issues an independent control command, it sends a trigger signal in advance based on the compensation parameter corresponding to the delay time. The dynamic closed-loop correction involves constructing a feedback loop through the auxiliary contacts of the actuator unit, collecting the actual action time of the switch in real time, comparing the time deviation between the expected action time and the actual action time, and dynamically iteratively adjusting the time delay drift caused by component aging or environmental changes to control the time dispersion of the switch action within the microsecond level.

[0016] According to another aspect of the present invention, the present invention provides a method for real-time control of high-precision multi-group parallel action mode test of power system based on the above-described system, the method comprising: The dynamic model test control unit manages multiple sets of dynamic model tests, assigns corresponding control tasks to each set of dynamic model tests, and sends the control tasks to the FPGA real-time controller. The FPGA real-time controller is divided into independent logic control domains corresponding to multiple groups of dynamic model tests, and the control task is executed based on the independent logic control domains, outputting independent control instructions for each group of dynamic model tests. The actuator unit independently controls the switching action of the corresponding dynamic model test based on the independent control command of each group of dynamic model tests.

[0017] According to another aspect of the present invention, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method as described in claim 9.

[0018] According to another aspect of the present invention, the present invention provides an electronic device, comprising: The aforementioned computer-readable storage medium; and One or more processors for executing a program in the computer-readable storage medium.

[0019] This invention provides a high-precision real-time control system and method for multiple parallel dynamic simulation tests in power systems. The system includes: a dynamic simulation test control unit, a field-programmable gate array (FPGA) real-time controller, and an actuator unit. The dynamic simulation test control unit manages tasks for multiple sets of dynamic simulation tests, assigns corresponding control tasks to each set, and sends the control tasks to the FPGA real-time controller. The FPGA real-time controller is divided into independent logic control domains corresponding to the multiple sets of dynamic simulation tests, executes control tasks based on these independent logic control domains, and outputs independent control instructions for each set of dynamic simulation tests. The actuator unit independently controls the switching actions of the corresponding dynamic simulation tests based on the independent control instructions for each set. This invention achieves fundamental physical hardware isolation by dividing the FPGA into independent logic control domains, ensuring that multiple sets of tests can run independently and in parallel without interference. Attached Figure Description

[0020] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures: Figure 1 This is a structural diagram of a high-precision multi-group parallel motion model test real-time control system for a power system according to an embodiment of the present invention; Figure 2 A timing control flowchart according to an embodiment of the present invention; and Figure 3 This is a flowchart of a high-precision multi-group parallel motion model test real-time control method for a power system according to an embodiment of the present invention. Detailed Implementation

[0021] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0022] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0023] Figure 1 This is a structural diagram of a high-precision multi-group parallel motion model test real-time control system for a power system according to an embodiment of the present invention; This invention provides a high-precision real-time control system for multi-group parallel motion model testing in power systems, achieving the following technical objectives: (1) Achieve millisecond-level (≤1ms) switching action timing control accuracy to meet the requirements of high-precision fault simulation.

[0024] (2) Supports the independent operation of 5 groups of parallel tests, with complete electrical isolation and resource mutual exclusion control between each group.

[0025] (3) Provides multiple triggering modes: immediate trigger, external switch trigger, closing angle trigger, GPS / BeiDou time trigger, and hard input trigger.

[0026] (4) Achieve high-precision control with a frequency accuracy of 0.01Hz and an angle accuracy of 0.1° under the closing angle trigger mode.

[0027] The high-precision multi-group parallel motion model test real-time control system provided by this invention adopts a hierarchical distributed architecture and mainly includes the following core modules: Table 1. Functions and Responsibilities of Core System Modules

[0028] The overall system architecture of this invention is as follows: Figure 1 As shown, a three-level control structure of "industrial control computer-FPGA-execution unit" is adopted. The dynamic model test control unit runs the control software and is responsible for task management, parameter configuration and human-machine interaction; the FPGA serves as the real-time control core, realizing high-precision timing control, logic operation and signal processing; the execution mechanism layer completes the switching action of the physical dynamic model equipment.

[0029] like Figure 1 As shown, the present invention provides a high-precision multi-group parallel dynamic model test real-time control system for power systems. The system includes: a dynamic model test control unit, a field-programmable gate array (FPGA) real-time controller, and an actuator unit. The dynamic model test control unit is used to manage multiple sets of dynamic model tests, assign corresponding control tasks to each set of dynamic model tests, and send the control tasks to the FPGA real-time controller. The FPGA real-time controller is used to divide the system into independent logic control domains corresponding to multiple sets of dynamic model tests, and to execute control tasks based on the independent logic control domains, outputting independent control instructions for each set of dynamic model tests. Preferably, the independent logic control domain is used to support multiple triggering modes, including: immediate triggering, external switch triggering, closing angle triggering, GPS / BeiDou time triggering, and hard input triggering.

[0030] The actuator unit is used to independently control the switching action of the corresponding dynamic model test based on the independent control command of each group of dynamic model tests.

[0031] Preferably, the FPGA real-time controller uses an active crystal oscillator of ≥100MHz as the system clock, and performs timing control on independent control instructions based on the system clock.

[0032] Preferably, each independent logic control domain corresponds one-to-one with each group of dynamic model tests; The independent logic control domain includes an independent timing register, a source selector, and an output channel. The independent timing register is used to provide dedicated timing for the independent logic control domain, the source selector is used to determine the control source for the independent logic control domain, and the output channel is used to output the independent control commands corresponding to the dynamic model test. Preferably, the FPGA real-time controller performs control tasks based on three-level mutual exclusion control, including: Level 1: Software allocation is mutually exclusive, and the access and locking of physical resources are determined by the dynamic model test control unit; Level 2: Hardware bus isolation, achieving hardware-level parallelism without interference through independent logic control domains; Level 3: Timing safety lockout, which uses hard logic mutex gates set at the output of the FPGA real-time controller to intercept dangerous instructions by timing constraints.

[0033] Preferably, the FPGA real-time controller employs a dual-layer timing compensation algorithm of static pre-compensation + dynamic closed-loop correction to control the relative time error of the switching action of the actuator unit to ≤1ms, wherein: Static pre-compensation is used to pre-calibrate the inherent operating delay of intermediate relays, high-precision AC contactors or thyristor modules in the actuator unit, and store the inherent operating delay as a compensation parameter in the dynamic model test control unit. When the FPGA real-time controller issues independent control commands, it sends a trigger signal based on the compensation parameter and the corresponding delay time in advance. Dynamic closed-loop correction constructs a feedback loop through the auxiliary contacts of the actuator unit, collects the actual action time of the switch in real time, compares the time deviation between the expected action time and the actual action time, and dynamically iterates and adjusts the time delay drift caused by component aging or environmental changes, controlling the time dispersion of the switch action to the microsecond level.

[0034] This invention is illustrated by taking the parallel operation of five groups of dynamic model tests as an example. The independence between each group is achieved through the following design: (1) Electrical isolation design Each test group is equipped with an independent FPGA control channel or area, and each area has an independent timing register, trigger source selector, and output channel. The power circuits use independent contactor / thyristor modules, and there is no electrical connection between the power circuits.

[0035] (2) Dynamic resource allocation mechanism The system employs a dynamic resource allocation strategy, dynamically allocating and exclusively using the following resources for each test group: one FPGA control channel, corresponding quantitative digital output, corresponding quantitative analog input, one GPS time synchronization channel, and corresponding actuator. Resource allocation is dynamically determined by the control system when the test group is created and is not adjusted during the test.

[0036] The control system software maintains a "resource status table" and is responsible for retrieving available FPGA channels, I / O ports, and actuators before the experiment begins. The control system's resource manager is responsible for checking the legality of the allocation scheme, performing a "resource locking" operation to prevent test group A from misusing the actuators of test group B, and releasing and reclaiming resources.

[0037] (3) Mutual exclusion control mechanism To prevent interference between multiple sets of experiments, the system implements three levels of mutual exclusion control: Level 1: Software allocation mutual exclusion (admission layer). During the test group initialization phase, the industrial control computer software scans physical resources (FPGA channels, actuators, I / O ports). When a target resource is idle and available, it can be allocated to the current test group and its usage rights can be forcibly locked, thus preventing resource conflicts from the source.

[0038] Level 2: Hardware bus isolation (physical layer). The FPGA is divided into five completely independent logic resource domains. Each domain has its own instruction register and timing generator. Even if multiple tests are triggered simultaneously, their signal processing is completed on their respective physical loops, achieving true parallelism without mutual interference.

[0039] Level 3: Timing Safety Lockout (Execution Layer). At the final stage of the FPGA output, a hard logic mutex gate is set. For actions with physical destructive potential (such as closing and tripping commands on the same phase line), even if the dynamically allocated logic fails, the hard logic layer will forcibly intercept the action according to preset microsecond-level timing constraints (e.g., the action interval must be >10ms), ensuring the safety of the actuator.

[0040] Switch control method The system controls the following switching devices, and the control relationships and timing logic between these devices are as follows: Table 2 Controlled Objects and Action Characteristics

[0041] High-precision timing and triggering schemes (1) Millisecond-level timing control implementation mechanism The system employs an FPGA to achieve millisecond-level timing control, using an active crystal oscillator of ≥100MHz as the FPGA system clock. Leveraging its parallel processing capabilities, independent logic comparators are provided for each group of parallel experiments. Parallel comparisons are made between the current time and the preset action time, enabling fine-grained decomposition and execution of action instructions on the order of 1ms.

[0042] (2) Switching relative time error control strategy To ensure that the relative time error between switches is ≤1ms, the system establishes a two-layer correction model of "static pre-compensation + dynamic closed loop": • Hardware delay calibration and pre-compensation: The inherent operating time (such as closing delay) of intermediate relays, high-precision AC contactors, or thyristors is pre-determined and entered as compensation parameters into the resource management subsystem. The FPGA automatically issues a trigger signal in advance of the above delay time when executing instructions.

[0043] • Closed-loop correction and dispersion control: A feedback loop is constructed through the auxiliary contacts of the actuator to collect the time scale of the actual switch action in real time. The system compares the "expected action time" with the "actual action time" and dynamically iteratively adjusts the time dispersion to control it within the microsecond level, taking into account drift caused by component aging or environmental changes.

[0044] (3) Triggering methods supported The system supports the following five trigger modes: Table 3 Trigger Mode Description

[0045] The actuator unit includes an independent execution module corresponding to each group of dynamic model tests. Each independent execution module includes an independent power circuit, and the power circuits of each group of dynamic model tests are electrically isolated from each other.

[0046] Preferably, the dynamic model test control unit manages multiple sets of dynamic model tests based on a dynamic resource allocation mechanism, including: Each group of dynamic model tests is dynamically allocated and exclusively uses resources, including: One FPGA control channel corresponding to the independent logic control domain, one corresponding quantitative digital output port, and one corresponding quantitative analog input port; One GPS / BeiDou time synchronization channel is provided for use by an independent logic control domain; And a set of independent execution modules corresponding to the execution unit.

[0047] Preferably, the actuator unit includes: an intermediate relay, a high-precision AC contactor, and a thyristor module; Intermediate relays are used to receive independent control commands output by the FPGA real-time controller and convert them into control signals to achieve electrical isolation and drive power amplification of the control signals. High-precision AC contactors are used for switching control of the primary circuit in dynamic model testing based on a power-amplified control signal. The thyristor module is used to enable rapid action of the fault point switch and phase selection switch in dynamic model testing based on the power-amplified control signal.

[0048] The system of this invention includes the following key subsystems: (1) Experimental Task Management Subsystem It is responsible for the logical scheduling of the entire test lifecycle, including task creation, parameter issuance, start, pause, stop, and reset. It transforms user-defined test requirements (such as fault types and action sequences) into an executable instruction stream.

[0049] (2) Experimental Resource Management Subsystem Access control and dynamic allocation are implemented. Before the experiment starts, one FPGA channel, one GPS channel, and their corresponding I / O pins and actuators are scanned and exclusively allocated. By maintaining a resource status table, the first level of mutual exclusion is implemented at the software level to ensure absolute physical resource isolation between each parallel experimental group.

[0050] (3) High-precision timing control subsystem Leveraging FPGA hardware, it achieves fine-grained action timing of ≤1ms. It supports frequency tracking with an accuracy of 0.01Hz and closing angle calculation with an accuracy of 0.1°, ensuring deterministic switching action.

[0051] (4) Fault simulation subsystem Control the operation logic of primary-side analog equipment (such as fault switches, phase selection switches, transition resistance switches, etc.).

[0052] Based on the instructions of the timing control subsystem, the end-to-end test fault control process from "normal operation" to "fault initiation" and "fault clearance" is completed.

[0053] (5) Real-time monitoring subsystem Provides visual feedback on the test status, including real-time switch position, dynamic voltage and current waveforms, and test progress monitoring. Monitoring data streams are transmitted independently, ensuring that monitoring activities do not consume the computing resources of the control link and guaranteeing real-time control.

[0054] (6) Data recording subsystem All electromagnetic transient data and action time stamps during the experiment are stored synchronously.

[0055] This invention supports joint tracing and comparative analysis of multiple sets of experimental data based on GPS / BeiDou unified timestamps.

[0056] Figure 2 This is a timing control flowchart according to an embodiment of the present invention.

[0057] like Figure 2 As shown, this invention first enters the trigger condition monitoring stage, and determines that the branch consists of three paths based on the trigger mode, corresponding to different high-precision triggering mechanisms: Closing Angle Trigger: Performs closing angle judgment and prediction. Suitable for closing tests requiring precise control of voltage phase, enabling real-time calculation of grid frequency and phase.

[0058] Satellite time triggering: Performs timestamp comparison (e.g., GPS / BeiDou). Utilizes high-precision time synchronization signals as a globally unified clock reference to ensure time synchronization across multiple sets of experiments.

[0059] Hard-input trigger: Performs level monitoring and filtering. By acquiring external hardware switch signals and performing anti-interference filtering, the reliability of the trigger signal is ensured.

[0060] This invention performs unified timing processing, and the above three branches eventually converge to the timing solution and delay compensation node: In this invention, regardless of whether the input is a phase angle, timestamp, or level signal, the system uniformly converts it into a precise time command. This invention dynamically compensates for the physical delay of the actuator, ensuring absolute accuracy in the timing of command issuance.

[0061] This invention strictly controls the instruction flow of multiple parallel tasks at the FPGA controller level and prevents malfunctions through hardware logic mutual exclusion.

[0062] This invention drives the actuator (contactor / thyristor) to operate and collects feedback signals from auxiliary contacts in real time, forming a hardware closed loop.

[0063] This invention is compatible with three triggering modes: phase, time, and hard switching, to meet the diverse needs of power system fault simulation, grid connection testing, and other scenarios.

[0064] This invention solves the problem of asynchronous actions in power grid testing by using "timing calculation + delay compensation".

[0065] This invention uses motion error feedback for real-time correction, which can maintain extremely high control accuracy and stability over a long period of time.

[0066] The timing control process of this invention is adapted to the dynamic model test scenario of power system, and can realize the independent control of multiple parallel tests without interference. It has extremely high engineering practical value for verifying the accuracy of power grid protection device operation and analyzing system transient stability.

[0067] The present invention has the following technical effects: (1) The timing control accuracy is significantly improved: the switching action accuracy is improved from the traditional 5-20ms to ≤1ms, supporting refined fault initial phase angle simulation.

[0068] (2) The test efficiency is greatly improved: it supports 5 groups of parallel tests, the equipment utilization rate is increased by 5 times, and multiple test tasks can be carried out at the same time, significantly shortening the test cycle.

[0069] (3) Rich and flexible triggering modes: It supports multiple triggering modes, especially closing angle triggering and GPS / BeiDou time triggering, to meet the needs of complex test scenarios. The closing angle control accuracy reaches 0.1° and the frequency accuracy is 0.01Hz.

[0070] (4) Easy to operate: The entire process is automatically controlled, reducing experimental deviations caused by manual intervention.

[0071] The following provides illustrative examples of embodiments of the present invention.

[0072] Embodiment 1 of the present invention: Single-group fault simulation test Taking a simulated single-phase ground fault as an example, the test configuration is as follows: • Experimental group: Group 1 • Trigger mode: Trigger immediately • Switch sequence: T=0ms: Fault switch closed (simulating phase A grounding) T=100ms: Circuit breaker trips T=500ms: Reclosing operation T=600ms: Fault switch disconnected (fault cleared) Embodiment 2 of the present invention: Closing angle control test Taking the circuit breaker closing at voltage peak as an example, the test configuration is as follows: • Experimental group: Group 2 • Triggering mode: Closing angle triggering • Parameter settings: Frequency = 50.00Hz, Correction angle = 0.0°, Trigger angle = 90.0° The system obtains the voltage phase reference through zero-crossing detection, calculates the target closing time, and outputs the closing signal when the voltage phase angle reaches 90°. The actual closing angle error is ≤0.1°.

[0073] Embodiment 3 of the present invention: GPS synchronization triggering test Taking cross-laboratory collaborative experiments as an example, the experiment configuration is as follows: • Experimental group: Group 3 • Trigger mode: GPS time trigger • Target time: 2024-03-01 10:00:00.000 The system receives GPS time signals and triggers the test when the system time matches the target time. The synchronization accuracy is ≤1ms, which meets the requirements of cross-laboratory collaborative testing.

[0074] Embodiment 4 of the present invention: Resource allocation for parallel experiments The test task management subsystem identifies the physical wiring requirements of Test Group 1 and Test Group 2, and locks their respective FPGA logic domains and I / O terminals through the resource management subsystem. During this period, if other tests attempt to request resources already used by this test, the system will intercept them according to the software mutual exclusion mechanism.

[0075] (1) Test Group 1 (500kV line phase selection and closing test) Resource allocation: The system dynamically allocates the first FPGA control channel, the first to eighth switch outputs, and the first GPS synchronization channel.

[0076] Control objective: Control the simulated circuit breaker to close when the A-phase voltage closing angle is 30°.

[0077] Trigger mode: Triggering at specified closing angle (frequency reference 50Hz).

[0078] (2) Test Group 2 (220kV line reclosing instantaneous fault test) Resource allocation: The system dynamically allocates the second FPGA control channel, the 9th-16th switch output channels, and the second GPS synchronization channel.

[0079] Control objective: A three-phase short-circuit fault occurs 100ms after the simulated line is running. After the relay protection trips, reclosing is performed 600ms later.

[0080] Trigger mode: Trigger immediately.

[0081] (1) Design of dynamic model test control system architecture: The real-time control system for supporting high-precision multi-group parallel dynamic model test adopts a hierarchical distributed architecture design.

[0082] (2) High-precision control method: FPGA-based millisecond-level timing control method, from software command to actuator action of the whole link timing compensation algorithm, to achieve a relative time error of ≤1ms for switching action.

[0083] (3) Multiple sets of parallel control logic and resource allocation method: Implement the logic and resource allocation method of 5 sets of dynamic model test resources that are completely isolated and do not interfere with each other within a single FPGA architecture.

[0084] (4) Multi-source fusion triggering mechanism: a composite triggering scheme that is compatible with satellite time, hard input and logic level.

[0085] Figure 3 This is a flowchart of a high-precision multi-group parallel motion model test real-time control method for a power system according to an embodiment of the present invention.

[0086] like Figure 3 As shown, the present invention provides a method for real-time control of high-precision multi-group parallel action mode test of power system based on the above-mentioned system, the method comprising: Step 301: Perform task management on multiple groups of dynamic model tests through the dynamic model test control unit, assign corresponding control tasks to each group of dynamic model tests, and send the control tasks to the FPGA real-time controller; Step 302: Divide the FPGA real-time controller into independent logic control domains corresponding to multiple groups of dynamic model tests, and execute control tasks based on the independent logic control domains to output independent control instructions for each group of dynamic model tests; Preferably, the FPGA real-time controller uses an active crystal oscillator of ≥100MHz as the system clock, and performs timing control on independent control instructions based on the system clock.

[0087] Preferably, the independent logic control domain is used to support multiple triggering modes, including: immediate triggering, external switch triggering, closing angle triggering, GPS / BeiDou time triggering, and hard input triggering.

[0088] Preferably, the FPGA real-time controller performs control tasks based on three-level mutual exclusion control, including: Level 1: Software allocation is mutually exclusive, and the access and locking of physical resources are determined by the dynamic model test control unit; Level 2: Hardware bus isolation, achieving hardware-level parallelism without interference through independent logic control domains; Level 3: Timing safety lockout, which uses hard logic mutex gates set at the output of the FPGA real-time controller to intercept dangerous instructions by timing constraints.

[0089] Preferably, the FPGA real-time controller employs a dual-layer timing compensation algorithm of static pre-compensation + dynamic closed-loop correction to control the relative time error of the switching action of the actuator unit to ≤1ms, wherein: Static pre-compensation is used to pre-calibrate the inherent operating delay of intermediate relays, high-precision AC contactors or thyristor modules in the actuator unit, and store the inherent operating delay as a compensation parameter in the dynamic model test control unit. When the FPGA real-time controller issues independent control commands, it sends a trigger signal based on the compensation parameter and the corresponding delay time in advance. Dynamic closed-loop correction constructs a feedback loop through the auxiliary contacts of the actuator unit, collects the actual action time of the switch in real time, compares the time deviation between the expected action time and the actual action time, and dynamically iterates and adjusts the time delay drift caused by component aging or environmental changes, controlling the time dispersion of the switch action to the microsecond level.

[0090] Step 303: The actuator unit independently controls the switching action of the corresponding dynamic model test based on the independent control command of each group of dynamic model tests.

[0091] Preferably, each independent logic control domain corresponds one-to-one with each group of dynamic model tests; The independent logic control domain includes an independent timing register, a source selector, and an output channel. The independent timing register is used to provide dedicated timing for the independent logic control domain, the source selector is used to determine the control source for the independent logic control domain, and the output channel is used to output the independent control commands corresponding to the dynamic model test. The actuator unit includes an independent execution module corresponding to each group of dynamic model tests. Each independent execution module includes an independent power circuit, and the power circuits of each group of dynamic model tests are electrically isolated from each other.

[0092] Preferably, the dynamic model test control unit manages multiple sets of dynamic model tests based on a dynamic resource allocation mechanism, including: Each group of dynamic model tests is dynamically allocated and exclusively uses resources, including: One FPGA control channel corresponding to the independent logic control domain, one corresponding quantitative digital output port, and one corresponding quantitative analog input port; One GPS / BeiDou time synchronization channel is provided for use by an independent logic control domain; And a set of independent execution modules corresponding to the execution unit.

[0093] Preferably, the actuator unit includes: an intermediate relay, a high-precision AC contactor, and a thyristor module; Intermediate relays are used to receive independent control commands output by the FPGA real-time controller and convert them into control signals to achieve electrical isolation and drive power amplification of the control signals. High-precision AC contactors are used for switching control of the primary circuit in dynamic model testing based on a power-amplified control signal. The thyristor module is used to enable rapid action of the fault point switch and phase selection switch in dynamic model testing based on the power-amplified control signal.

[0094] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a real-time control method for high-precision multi-group parallel action mode test of a power system.

[0095] This invention provides an electronic device, comprising: The aforementioned computer-readable storage medium; and One or more processors for executing a program in a computer-readable storage medium.

[0096] The present invention has been described with reference to a few embodiments. However, it will be apparent to those skilled in the art that other embodiments besides those disclosed above fall equivalently within the scope of the present invention.

[0097] Generally, all terms used in this invention are interpreted according to their ordinary meaning in the art, unless otherwise expressly defined herein. All references to “a / the / the [device, component, etc.]” ​​are openly interpreted as at least one instance of said device, component, etc., unless otherwise expressly stated. The steps of any method disclosed herein need not be performed in the exact order disclosed unless explicitly stated otherwise.

[0098] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-precision real-time control system for multi-group parallel motion model testing in a power system, characterized in that, The system includes: a dynamic model test control unit, a field-programmable gate array (FPGA) real-time controller, and an actuator unit; The dynamic model test control unit is used to manage multiple sets of dynamic model tests, assign corresponding control tasks to each set of dynamic model tests, and send the control tasks to the FPGA real-time controller. The FPGA real-time controller is used to divide the system into independent logic control domains corresponding to multiple sets of dynamic model tests, and to execute the control task based on the independent logic control domains, outputting independent control instructions for each set of dynamic model tests. The actuator unit is used to independently control the switching action of the corresponding dynamic model test based on the independent control command of each group of dynamic model tests.

2. The system according to claim 1, characterized in that, The FPGA real-time controller uses a ≥100MHz active crystal oscillator as the system clock and performs timing control on the independent control commands based on the system clock.

3. The system according to claim 1, characterized in that, Each independent logic control domain corresponds one-to-one with each group of dynamic model tests; The independent logic control domain includes an independent timing register, a source selector, and an output channel; the independent timing register is used to provide dedicated timing for the independent logic control domain, the source selector is used to determine the control source of the independent logic control domain, and the output channel is used to output independent control commands corresponding to the dynamic model test; The actuator unit includes an independent execution module corresponding to each group of dynamic model tests. Each independent execution module includes an independent power circuit, and the power circuits of each group of dynamic model tests are electrically isolated from each other.

4. The system according to claim 3, characterized in that, The independent logic control domain is used to support multiple triggering modes, including: immediate triggering, external switch triggering, closing angle triggering, GPS / BeiDou time triggering, and hard input triggering.

5. The system according to claim 1, characterized in that, The dynamic model test control unit manages multiple sets of dynamic model tests based on a dynamic resource allocation mechanism, including: Each group of dynamic model tests is dynamically allocated and exclusively uses resources, including: One FPGA control channel corresponding to the independent logic control domain, a corresponding quantitative digital output port, and a corresponding quantitative analog input port; One GPS / BeiDou time synchronization channel is provided for use by the independent logic control domain; And a set of independent execution modules corresponding to the execution unit.

6. The system according to claim 1, characterized in that, The FPGA real-time controller executes the control task based on three-level mutual exclusion control, including: Level 1: Software allocation is mutually exclusive, and the access and locking of physical resources are determined by the dynamic model test control unit; Level 2: Hardware bus isolation, achieving hardware-level parallelism without interference through the independent logic control domain; Level 3: Timing safety lockout, which uses a hard logic mutex gate set at the output of the FPGA real-time controller to intercept dangerous instructions by timing constraints.

7. The system according to claim 1, characterized in that, The actuator unit includes: an intermediate relay, a high-precision AC contactor, and a thyristor module; The intermediate relay is used to receive independent control commands output by the FPGA real-time controller and convert the independent control commands into control signals to achieve electrical isolation of the control signals and amplification of drive power. The high-precision AC contactor is used to control the switching of the primary circuit of the dynamic model test based on the power-amplified control signal. The thyristor module is used to enable the rapid execution of the fault point switch and phase selection switch in the dynamic model test based on the control signal after power amplification.

8. The system according to claim 1, characterized in that, The FPGA real-time controller employs a dual-layer timing compensation algorithm of static pre-compensation + dynamic closed-loop correction to control the relative time error of the switching action of the actuator unit to ≤1ms, wherein: The static pre-compensation is to pre-calibrate the inherent operating delay of the intermediate relay, high-precision AC contactor or thyristor module in the actuator unit, and store the inherent operating delay as a compensation parameter in the dynamic model test control unit. When the FPGA real-time controller issues an independent control command, it sends a trigger signal in advance based on the compensation parameter corresponding to the delay time. The dynamic closed-loop correction involves constructing a feedback loop through the auxiliary contacts of the actuator unit, collecting the actual action time of the switch in real time, comparing the time deviation between the expected action time and the actual action time, and dynamically iteratively adjusting the time delay drift caused by component aging or environmental changes to control the time dispersion of the switch action within the microsecond level.

9. A real-time control method for high-precision multi-group parallel motion model tests of a power system based on the system described in claim 1, characterized in that, The method includes:; The dynamic model test control unit manages multiple sets of dynamic model tests, assigns corresponding control tasks to each set of dynamic model tests, and sends the control tasks to the FPGA real-time controller. The FPGA real-time controller is divided into independent logic control domains corresponding to multiple groups of dynamic model tests, and the control task is executed based on the independent logic control domains, outputting independent control instructions for each group of dynamic model tests. The actuator unit independently controls the switching action of the corresponding dynamic model test based on the independent control command of each group of dynamic model tests.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in claim 9.

11. An electronic device, characterized in that, include: The computer-readable storage medium as described in claim 10; as well as One or more processors for executing a program in the computer-readable storage medium.

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