Power quality calculation method for power intelligent terminal

Abstract

The application discloses a power quality calculation method of an electric power intelligent terminal, and comprises the following steps: acquiring multi-channel original waveform data of an exchange sampling metering unit; after sampling reduction and extraction, the multi-channel original waveform data is input into parallel full-band channels and narrow-band fundamental wave channels respectively for filtering, so that full-band waveform data and narrow-band fundamental wave waveform data are obtained; two-way data is written into a shared memory queue by using a double sequence number writing protocol to generate a buffer waveform data frame; the buffer waveform data frame passing through consistency discrimination is read, and local fundamental wave frequency is calculated based on the narrow-band fundamental wave waveform data; the number of sampling points of an analysis window for the full-band waveform data is dynamically adjusted according to the frequency, and operator multiplexing calculation is performed on the full-band waveform data based on a hierarchical calculation scheduling architecture, so that a power quality index set is obtained. The application suppresses non-synchronous sampling errors, and improves the algorithm power multiplexing efficiency and real-time performance of multi-index concurrent calculation.

Description

Technical Field

[0001] This invention relates to the field of power equipment technology, and in particular to a power quality calculation method for a smart power terminal. Background Technology

[0002] Power quality monitoring is fundamental to assessing and ensuring the safe and stable operation of smart grids. With the widespread integration of nonlinear impact loads and massive distributed power sources in new power systems, the spectral composition of grid voltage and current signals is becoming increasingly complex. This requires underlying power terminal equipment to possess the technical capability to simultaneously acquire multi-dimensional indicators and perform high-precision time-frequency analysis in complex alternating electrical environments.

[0003] Existing power quality monitoring terminals mostly employ a single data acquisition and processing pipeline. At the front-end signal conditioning stage, they typically rely on a single broadband digital filtering mechanism to coarsely preserve the overall signal picture, or at the main control stage, they use a purely software-based single-threaded sequential structure to process each electrical indicator one by one. When faced with non-ideal operating conditions such as grid frequency drift or load surges, the discrete transformation window of this fixed parameter is difficult to strictly align with the physical cycle of the actual waveform. Furthermore, under the constraint of limited microprocessor computing resources, the independent sequential calculation of multiple indicators leads to significant data read blocking and latency accumulation when the system handles high-concurrency tasks such as short-term transient event capture and long-term statistical analysis of multi-dimensional parameters.

[0004] In summary, existing methods are susceptible to interference from micro-fluctuations in the underlying fundamental frequency in high-frequency measurement under asynchronous sampling environments, and face significant bottlenecks in the efficiency of underlying data flow and system computing power scheduling under high-concurrency processing conditions with multiple indicators. Therefore, it is necessary to study a computational analysis mechanism that can balance waveform analysis accuracy and real-time performance in complex power grid conditions with multi-core concurrent processing. Summary of the Invention

[0005] The purpose of this invention is to provide a power quality calculation method for a smart power terminal, in order to solve the aforementioned problems in the prior art.

[0006] Technical solution: A power quality calculation method for a smart power terminal, comprising: Acquire raw waveform data of the power grid from multiple channels in real time collected by the metering unit; The original waveform data (i.e., multi-channel raw waveform data) is downsampled and extracted, and the extracted data is input into parallel full-band and narrow-band fundamental wave paths for digital filtering to obtain full-band waveform data and narrow-band fundamental wave waveform data. A dual-serial-number writing protocol is used to write full-band waveform data and narrowband fundamental waveform data into a shared memory queue, generating buffered waveform data frames. Read the buffered waveform data frames that have passed the consistency test from the shared memory queue, and parse out the full-band waveform data and narrowband fundamental waveform data in the buffered waveform data frames; Calculate the local fundamental frequency based on narrowband fundamental waveform data; The number of sampling points in the analysis window for the full-band waveform data is dynamically adjusted based on the local fundamental frequency, and the operator multiplexing calculation is performed on the full-band waveform data based on the pre-configured hierarchical computing scheduling architecture to obtain a set of power quality indicators.

[0007] Beneficial effects: This invention primarily reduces asynchronous sampling errors and improves the computational power reuse efficiency and real-time performance of concurrent multi-index calculations. Specifically, addressing the technical challenge of asynchronous sampling caused by power grid frequency fluctuations leading to spectral leakage, it employs an adaptive windowing and discrete fixed-point spectrum recursion method based on frequency tracking closed-loop. This aligns the time-domain truncation window with the zero-crossing boundary of the actual power frequency cycle and directly calculates harmonic amplitudes at fundamental frequency deviation points. This reduces the frequency analysis residual under asynchronous sampling conditions from the conventional discrete grid level to a controllable micro-range, improving the accuracy of broadband distortion measurement. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the overall process of the power quality calculation method of the power intelligent terminal of the present invention.

[0009] Figure 2 This is a schematic diagram of the multi-channel waveform downsampling and dual-channel filtering process provided by the present invention.

[0010] Figure 3 This is a schematic diagram of the process of generating buffered waveform data frames based on the dual serial number writing protocol of the present invention.

[0011] Figure 4 This is a schematic diagram of the shared memory queue waveform data frame consistency judgment and backtracking reading process provided by the present invention. Detailed Implementation

[0012] Example 1: This example provides a power quality calculation method for a smart power terminal. This method operates on a heterogeneous multi-core hardware topology environment that includes a metering unit, a small core unit, shared memory, and a main control large core unit. The main steps include: like Figure 1 As shown, in step 101, the original waveform data of the power grid multi-channels collected in real time by the cross-measuring unit is obtained.

[0013] Specifically, the metering unit, as the front-end hardware node for data acquisition, uses its internal high-precision analog-to-digital conversion circuit to synchronously sample the physical quantities of voltage and current of each phase connected to the power grid at high frequency.

[0014] The acquisition process continues under the drive of a fixed sampling clock. The acquired multi-channel data streams are packaged and transmitted to the small core unit of the system via the serial peripheral interface bus.

[0015] The multi-channel synchronous acquisition mechanism establishes a precise time profile of the power grid's physical state in the digital domain, providing a fundamental underlying data source with a unified time reference for the parallel calculation of multi-dimensional power quality indicators.

[0016] In some alternative implementations, when the cross-data collection metering unit is configured with 16-bit sampling precision, the physical layer transmission rate of the serial peripheral interface bus can be configured to 4 Mbit / s to meet the real-time bandwidth requirements for the data stream generated by the seven parallel electrical channels at a sampling frequency of 25.6 kHz.

[0017] As an alternative, when the analog-to-digital conversion accuracy is improved to a 24-bit configuration, the bus transmission rate needs to be increased to no less than 8 Mbit / s, or a hardware direct memory access controller can be introduced on the small core unit side to be responsible for the automatic transfer of data blocks, thereby reducing the concurrent interrupt response load of the main processor.

[0018] Step 102: Downsample the original waveform data from the multi-channel source and input the extracted data into parallel full-band and narrow-band fundamental wave paths for digital filtering to obtain full-band waveform data and narrow-band fundamental wave waveform data.

[0019] In this embodiment, downsampling is specifically achieved by discarding some sampling points and combining them with anti-aliasing constraints to reduce the computational pressure of high-frequency data streams on subsequent stages, while retaining the effective spectral range that conforms to the Nyquist theorem.

[0020] Furthermore, the parallel dual-path design performs feature-dimension isolation and splitting on a unified data source at the logical level.

[0021] The full-band path is equipped with a low-pass filter with a high cutoff frequency to retain high-order harmonic components and high-frequency transient distortion components without distortion, thereby outputting full-band waveform data that can comprehensively reflect the broadband distortion state of the power grid.

[0022] In contrast, the narrowband fundamental wave path is equipped with a bandpass filter with an extremely narrow passband range. This filter is used to perform out-of-band attenuation on the same source data, stripping away all high-frequency harmonics and broadband noise, thereby extracting a single, pure 50Hz power frequency component to obtain narrowband fundamental wave waveform data.

[0023] Based on the above structural separation, the inherent algorithmic conflict between the need for a pure fundamental frequency for high-precision frequency tracking and the need to retain high-frequency components for harmonic analysis can be resolved, thus establishing the necessary data flow foundation for subsequent dynamic closed-loop control.

[0024] Step 103: Using a dual-serial-number writing protocol, write the full-band waveform data and narrowband fundamental waveform data into a shared memory queue to generate a buffered waveform data frame.

[0025] Specifically, the dual-serial number write protocol is a lock-free concurrency control mechanism for heterogeneous multi-core processor architectures.

[0026] As the sole data producer, the small core unit actively acquires a globally incrementing write sequence counter value when pushing data into the pre-allocated shared memory queue space.

[0027] When performing physical memory write operations, the small core unit strictly follows the timing sequence of first writing the prefix sequence number in the head address range of the target memory block, then sequentially storing the payloads of full-band waveform data and narrowband fundamental waveform data, and finally writing the suffix sequence number in the tail address range of the target memory block.

[0028] Once the serial number imprints at the beginning and end are successfully stored in the memory medium, a complete buffered waveform data frame is encapsulated in the shared memory queue.

[0029] By injecting the same sequence number at both ends of the data frame as an integrity boundary identifier, this mechanism avoids pipeline blocking problems caused by using system-level mutex locks in high-frequency data exchange scenarios at the millisecond level, and ensures the integrity of data flow across cores from the underlying protocol level.

[0030] Step 104: Read the buffered waveform data frame that has passed the consistency check from the shared memory queue, and parse out the full-band waveform data and narrow-band fundamental waveform data in the buffered waveform data frame.

[0031] The main control core unit acts as a data consumer, polling the shared memory queue according to its own computing scheduling cycle.

[0032] During a read operation, the main control big core unit extracts the sequence number values ​​from the header and tail of the current target frame for logical comparison. If and only if the header and tail sequence number values ​​are equal, the main control big core unit determines that the current read process does not overlap with the write operation of the small core unit in time and space, confirms that the frame data is in a static and complete safe state, and then accepts it as a buffered waveform data frame that has passed the consistency judgment.

[0033] For the received data frame, the main control core unit unpacks and maps its memory payload to the local cache according to the preset byte offset mapping table, and reconstructs the independent full-band waveform data stream and narrowband fundamental waveform data stream.

[0034] In some embodiments, if the main control big core unit finds that the first and last sequence numbers are inconsistent, it directly determines that the current data frame is in an intermediate state of being overwritten and updated by the small core unit. The main control big core unit will actively give up reading the memory block at the current index position and backtrack to the historical node direction according to the queue ring topology until the most recent complete closed data frame is hit.

[0035] Step 105: Calculate the local fundamental frequency based on the narrowband fundamental waveform data.

[0036] Specifically, the local fundamental frequency is achieved by performing time-domain zero-crossing feature extraction on the narrowband fundamental waveform data. Since the narrowband fundamental waveform data has already been stripped of multiple waveform reflection interferences caused by harmonics in the preprocessing stage, its time-domain waveform exhibits a smooth, single sinusoidal trend.

[0037] The main control core unit monitors key nodes where the signal crosses from negative to positive or from positive to negative, records the time difference between adjacent zero-crossing points in the same direction, and maps the reciprocal of the time difference to the transient fundamental frequency of the power grid within the current local observation window.

[0038] This step utilizes the high signal-to-noise ratio data separated in the previous step to reduce the interference of waveform distortion under complex power grid loads on the frequency measurement logic, and establishes a true frequency reference that follows the fluctuations of the actual operating conditions of the power grid.

[0039] Step 106: Dynamically adjust the number of sampling points in the analysis window for the full-band waveform data based on the local fundamental frequency, and perform operator multiplexing calculation on the full-band waveform data based on the pre-configured hierarchical computing scheduling architecture to obtain a set of power quality indicators.

[0040] In this embodiment, the main control core unit establishes a feedback control closed loop from the frequency measurement end to the harmonic analysis end. When a local fundamental frequency drifts, the system calculates in real time the precise number of sampling points required to cover an integer number of actual waveform periods based on this frequency, and directly updates the number of sampling points in the analysis window using the dynamically calculated target value. By dynamically expanding and contracting the analysis window, the discrete spectrum analysis grid can be aligned with the actual waveform of the power grid, suppressing the spectrum leakage problem caused by period truncation error under asynchronous sampling conditions.

[0041] Meanwhile, the hierarchical computing scheduling architecture specifically decouples the complex and diverse power quality index calculation tasks into several basic operator layers and combined application layers by constructing a directed acyclic graph model.

[0042] The underlying operators are responsible for extracting common intermediate parameters such as half-cycle effective value and full-cycle effective value from the full-band waveform data and storing the calculation results; the upper-level different business modules such as voltage deviation, voltage fluctuation, and three-phase imbalance access and reuse these generated intermediate parameters in parallel.

[0043] This hierarchical operator reuse mechanism reduces the total amount of floating-point operation redundancy when heterogeneous terminals process multiple tasks simultaneously, and ultimately efficiently aggregates and outputs a set of power quality indicators that include multi-dimensional electrical health status assessment results.

[0044] Example 2: Based on Example 1 above, this example further describes the specific steps of downsampling and digital filtering of multi-channel raw waveform data. In one possible implementation, the steps include: like Figure 2 As shown, in step 201, integer decimation and anti-aliasing low-pass filtering are performed on the multi-channel original waveform data to obtain downsampled waveform data.

[0045] Specifically, integer decimation is achieved by adjusting the sampling rate through configuring the decimation factor in the digital signal processing module.

[0046] For example, when the front-end analog-to-digital converter performs sampling at a frequency of 25.6 kHz, 512 discrete sampling points are acquired per power frequency cycle.

[0047] Upon receiving the data stream, a decimation factor of 2 is configured for uniform decimation at a ratio of 2:1. Before performing spatial point-by-point discarding, the system applies a low-pass filter to the input data stream to limit the signal bandwidth.

[0048] The anti-aliasing low-pass filter can be implemented using a finite-length unit impulse response filter with an order of 64. The cutoff frequency threshold of this filter is set to 6000Hz, and the stopband attenuation is set to be greater than or equal to 60dB.

[0049] After this low-pass bandwidth limitation and interval decimation, the sampling frequency is converted from 25.6kHz to 12800Hz, resulting in rate-matched downsampled waveform data that avoids spectral aliasing.

[0050] Step 202: The downsampled waveform data is subjected to bandwidth-limited filtering in the first frequency band through the full-band path to obtain full-band waveform data.

[0051] In this embodiment, the full-band path corresponds to the logical broadband data parallel branch.

[0052] The first frequency band is set as the bandwidth between the DC cutoff frequency of 0Hz and 6000Hz. The downsampled waveform data transmitted through the full-band path retains the fundamental frequency and harmonic components up to a preset specific order, such as retaining the 19th harmonic component.

[0053] In digital signal processing, there is a transient response time when the filter transitions from stopband attenuation to a stable output state. To suppress the numerical fluctuations introduced by this transient process, several transient response points are actively removed in the initial stage of the filtered output.

[0054] For example, with the aforementioned 64th-order filter configuration, the pre-sampled points in the unsteady-state phase are discarded, and the full-band waveform data that has entered the steady-state phase is output. This waveform data serves as a broadband characteristic data source for subsequent harmonic calculations, voltage deviation, and unbalance measurements.

[0055] Step 203: The downsampled waveform data is processed by bandpass filtering in the second frequency band through the narrowband fundamental wave path to extract the power frequency fundamental wave component and obtain the narrowband fundamental wave waveform data.

[0056] Specifically, the narrowband fundamental frequency path and the full-band path are executed in parallel within the memory space of the small core unit.

[0057] The bandpass filtering in the second frequency band is implemented using a 128th-order bandpass finite-length unit impulse response filter. The lower passband frequency is set to 40Hz, and the upper passband frequency to 70Hz. A Hanning window function is used to smooth the tap coefficients in the time-domain weighted design. By applying this passband response characteristic, harmonics deviating from the power frequency and high-frequency components in the downsampled waveform data are filtered out, extracting the narrowband fundamental waveform data composed of the power frequency components.

[0058] In some alternative implementations, taking into account the physical characteristics of the group delay of the digital filter, the group delay introduced by the integer decimation above, plus the group delay introduced by the bandpass filtering in this step, and the additional transient margin that needs to be removed to reach steady state by the filter stopband attenuation, causes the overall data flow to be shifted backward on the time axis.

[0059] With this configuration, the total delay value converges to 190 sampling points. By configuring equal buffer offset values ​​in both the full-band and narrow-band fundamental wave paths, the output full-band waveform data and narrow-band fundamental wave waveform data are kept aligned in the time domain index.

[0060] In addition, if the system is connected to a power grid environment with a nominal frequency of 60Hz, the lower limit frequency of the second frequency band can be adjusted to 50Hz and the upper limit frequency of the passband can be adjusted to 80Hz to match the base frequency of different operating areas.

[0061] Example 3: Unlike Example 2 above, this example provides another process for downsampling and digitally filtering multi-channel raw waveform data. Specifically, this example uses a parallel path of hardware synchronous initial filtering and pure software-based off-path reconstruction on the small core side to achieve dual-path decoupling, thereby sharing the software filtering computation load of the small core unit. The remaining steps are the same as in Example 1, and can be referred to the foregoing description; they will not be repeated here.

[0062] In one possible implementation, the following steps are included: Step 301: Perform synchronous initial filtering and extraction processing on the multi-channel raw waveform data using the cross-acquisition side hardware to obtain hardware-filtered waveform data.

[0063] Specifically, this step alters the physical execution boundaries of digital filtering. The cross-data measurement unit integrates a hardware digital signal processor module.

[0064] After the multi-channel raw waveform data is output from the analog-to-digital converter on the acquisition side, it is directly input into the hardware digital signal processor module. The module's built-in low-pass digital filter operator performs synchronous initial filtering to remove interference components above a certain frequency. The decimation ratio is configured at the hardware level to reduce the number of data points output per cycle, thus obtaining the hardware-filtered waveform data.

[0065] The processed discrete sequence is sent to the small core unit in block transmission via the serial peripheral interface bus. This method utilizes the fixed hardware resources of the acquisition chip, reducing the preprocessing computational overhead of the small core unit at the data receiving end.

[0066] Step 302: On the software side, the initial filtered waveform data of the hardware is split and one of the branch data is used as the full-band waveform data.

[0067] In this embodiment, "software side" specifically refers to the kernel program execution environment of the small core unit.

[0068] After receiving the hardware-filtered data via interrupt service routine or direct memory access channel, the small core unit allocates two physical pointers in memory to perform split mapping on the physical addresses of the same data block. The branch data corresponding to one of the pointers does not undergo any additional band-limiting filtering and directly retains all the spectral components after hardware initial filtering.

[0069] The small core unit treats this as full-band waveform data and stores it in a designated buffer. This branch data retains the combined characteristics of the fundamental and higher harmonics, which is used for subsequent broadband performance analysis by the large core unit.

[0070] Step 303: The fundamental component of the data from another branch is extracted using a software splitting algorithm to reconstruct the narrowband fundamental waveform data.

[0071] Specifically, the small core unit uses branch data derived from another physical pointer to perform fundamental frequency separation at a purely software level. The software separation algorithm is implemented using a software cascaded integrator comb filter or a low-order infinite impulse response bandpass filter operator.

[0072] Since the hardware pre-filter has already removed high-frequency noise, the software algorithm only needs to suppress specific order harmonics in the low-frequency band. The software splitting algorithm applies a narrowband constraint of 50Hz center frequency to the current branch data, removing residual DC bias and low-order distortions other than the fundamental frequency, thereby reconstructing narrowband fundamental waveform data containing only the power frequency fundamental frequency component.

[0073] As an alternative approach, software splitting algorithms can also be implemented by performing fundamental waveform reconstruction based on moving average in the time domain.

[0074] By establishing a circular sliding window with a length matching the nominal power frequency period, the current branch data is input into the window for equal-weighted superposition and averaging, thereby canceling the symmetrical subharmonic components and realizing the software stripping and reconstruction of the fundamental waveform.

[0075] Combination Figure 3 and Figure 4 Example 4 further describes the specific steps of writing full-band waveform data and narrowband fundamental waveform data into a shared memory queue using a dual-serial-number writing protocol and performing read consistency judgment.

[0076] In one possible implementation, the following steps are included: Step 401: Obtain the global write sequence number of the current write operation.

[0077] Specifically, the small core unit maintains an unsigned integer variable with an auto-incrementing property in its memory control domain. This variable serves as a global write sequence number to record the number of data frames written since the system started.

[0078] Each time a new write interrupt or direct memory access completion callback is triggered, the small core unit reads the current value of this variable and increments it by one. This incrementing variable is cyclically cleared to zero after overflow, providing a timing indicator for unidirectional data flow.

[0079] The incrementing variable is cyclically cleared to zero after overflowing, providing a timing identifier for unidirectional data flow. In simpler terms, the incrementing variable provides a timing identifier for unidirectional incremental data flow.

[0080] Step 402: Write the global write sequence number as the pre-write sequence number into the first preset field of the head of the current queue member in the shared memory queue.

[0081] In this embodiment, the shared memory queue is divided into two hundred fixed-length queue members in the physical storage medium. The small core unit locates the starting memory address of the corresponding current queue member based on the current write pointer index.

[0082] In the first preset field with an initial memory address offset of zero, the small core unit writes the obtained global write sequence number. This first preset field occupies 4 bytes of storage space and is used to record the status imprint at the moment the write action begins, i.e., the pre-write sequence number.

[0083] During the process of writing the pre-write sequence number at the head of the current queue member, writing the full-band waveform data and the narrow-band fundamental waveform data, and writing the post-write sequence number at the tail, instruction flow control is executed, as shown in 403 and 405: Step 403: After writing the pre-write sequence number, inject a first memory barrier instruction into the execution pipeline of the processing unit (i.e., processor core, or small core unit) that performs the write operation, so as to force the write operation of the global write sequence number to precede the memory write operation of subsequent waveform data.

[0084] Specifically, modern microprocessor cores employ out-of-order execution pipelines and multi-level cache mechanisms, which may cause the order of instructions generated by the compiler to be reversed from the actual physical memory access order on the bus. To establish a strict memory access dependency, the little core unit inserts a first memory barrier instruction into the instruction stream.

[0085] This instruction intercepts and suspends all subsequent memory operation requests in the execution pipeline until the write operation initially sent to the first preset field is acknowledged on the bus. This barrier control mechanism prevents instruction reordering, allowing the memory observer to detect that the update of the pre-write sequence number is at the forefront of the data write operation.

[0086] Step 404: Store the full-band waveform data and narrowband fundamental waveform data sequentially into the data area of ​​the current queue member.

[0087] After the small core unit crosses the barrier command, it sequentially moves waveform samples to the data area of ​​the current queue member according to the pre-configured channel mapping relationship. The data area is divided into multiple consecutive fixed-length byte blocks according to the phase voltage and phase current. At the same time as storing the waveform load, the small core unit appends a data acquisition timestamp field to the end of the data area. This field consists of a continuous byte sequence of year, month, day, hour, minute, second, and microsecond, used to provide time traceability reference.

[0088] Step 405: After the full-band waveform data and narrow-band fundamental waveform data are stored sequentially, a second memory barrier instruction is injected into the execution pipeline to force the write operation of the write sequence number to lag behind the memory write operation of the data area.

[0089] Similar to the pre-emptive barrier control, the small core unit invokes the memory barrier action again after writing the waveform load and acquisition timestamp into the data area.

[0090] The second memory barrier instruction blocks subsequent store instructions that have not yet been issued in the pipeline, requiring the cache controller to clear the current write buffer. This step establishes a physical barrier, ensuring that the contents of the data area are solidified on the bus before the system is allowed to execute the next write command for the tail field.

[0091] Step 406: Write the global write sequence number as the write sequence number in the second preset field at the end of the current queue member, update the queue head write pointer of the shared memory queue, and generate a buffered waveform data frame.

[0092] The small core unit locates the end of the physical space of the current queue member and writes the same value cached in step 401 into the second preset field that occupies 4 bytes.

[0093] At this point, the header and tail of the data block are wrapped with the same numerical identifier. After the operation is completed, the small core unit increments the global write pointer index value at the head of the shared memory queue and performs a modulo operation to point to the next memory block to be written. Thus, a complete buffered waveform data frame is constructed in physical memory.

[0094] Step 407: Read the queue head write pointer of the shared memory queue to determine the target read frame position.

[0095] The main control core unit acts as the read end, accessing the control header area of ​​the shared memory queue through the cross-core bus interface.

[0096] The main control core unit extracts the current queue head write pointer, decrements the pointer value by one, and then takes the modulo of the total queue capacity to calculate the index of the queue member whose operation was most recently completed by the small core unit.

[0097] The main control core unit maps the physical address corresponding to the index to the target read frame location.

[0098] Step 408: Obtain the pre-write sequence number and post-write sequence number of the data frame corresponding to the target read frame position.

[0099] The main control core unit performs read operations on the first 4 bytes and the last 4 bytes of the memory block according to the target read frame position, and temporarily stores the two variables obtained into local registers, which correspond to the pre-write sequence number and the post-write sequence number, respectively. Since the read operation does not lock the shared memory, this memory access operation may overlap with the write operation of the small core unit in the time domain.

[0100] Step 409: Compare the serial number before writing with the serial number after writing to determine consistency.

[0101] The main control core unit calls the arithmetic logic unit to perform an equality comparison operation on the pre-write sequence number and the post-write sequence number temporarily stored in the register.

[0102] Through this logical operation, the system can infer the data stability of the target memory block during the reading process without relying on spinlocks or mutexes.

[0103] In the first execution path, if the sequence number before writing is the same as the sequence number after writing, the data frame is determined to be complete and is used as a buffered waveform data frame that passes the consistency check.

[0104] Specifically, when the two values ​​are strictly equal, it indicates that when the main control big core unit performs a read operation, the small core unit has not initiated an overwrite write to the data frame, or the data frame has not yet entered the next round of cyclic write.

[0105] This status indicates that there is no risk of misalignment between old and new data in the internal data area. The main control core unit then extracts and accepts all waveform samples from within the system using a partial migration method.

[0106] In the second execution path, if the sequence number before writing and the sequence number after writing are inconsistent, it is determined that the current data frame is in the intermediate state of writing. The current data frame is skipped and the historical frame index is traced back until the complete historical data frame is obtained. The complete historical data frame is then used as the buffer waveform data frame that passes the consistency judgment.

[0107] When there is a difference between the two values, it means that the main control big core unit has just intervened in the physical process of the small core unit updating the data frame, and the read data area may be mixed with fragments of different periods.

[0108] Under this condition, the main control core unit does not execute the retry waiting logic to avoid blocking the computation scheduling. Instead, it directly decrements the current read index by 1, jumps to the previous adjacent queue member in the historical direction of the time axis, and re-executes the above sequence number comparison process.

[0109] Since the small core unit is in a single-threaded sequential write state, the historical data frame is necessarily in a static period after the write is completed. The main control large core unit can obtain the lossless timing data with a single jump.

[0110] Those skilled in the art will understand that the specific improvement in data flow latency of the above-mentioned lock-free communication mechanism compared to the traditional mutex mechanism may vary depending on the processor architecture, bus bandwidth, and concurrent access frequency.

[0111] Example 5: Based on Example 1 above, this example further describes the specific steps involved in performing operator multiplexing calculations on full-band waveform data using a pre-configured hierarchical computing scheduling architecture to obtain a set of power quality indicators. In one possible implementation, the following steps are included: Step 501: In the first layer of the hierarchical computing scheduling architecture, the basic shared data is updated using half-cycle as the time scale. Specifically, the root mean square value of half-cycle for each channel is calculated using the currently received full-band waveform data; the root mean square values ​​of two adjacent half-cycles are aggregated to obtain the root mean square value of the full-cycle; and the zero-crossing points are extracted using the narrowband fundamental waveform data to obtain the zero-crossing time sequence.

[0112] Specifically, the main control core unit establishes a three-dimensional directed acyclic graph computation model that includes a basic data layer, an indicator data layer, and an application output layer.

[0113] In the basic data layer, the system wakes up the first layer operator every half-cycle of the fundamental frequency within the microsecond-level interrupt response framework.

[0114] The operator iterates through the full-band waveform data of each phase voltage and current channel and performs discrete root mean square (RMS) evaluation.

[0115] U rms_half =sqrt((1 / N half )*sum(x w (n) 2 )); Among them, U rms_half The root mean square value of the half-cycle, sqrt is the square root operation, N half x represents the number of discrete sampling points contained within a single half-cycle time span, sum is the cumulative summation operation, and x represents the number of discrete sampling points contained within a single half-cycle time span. w (n) is the discrete sequence of full-band waveform data of the current channel, where n is the sequence index.

[0116] After obtaining the discrete half-cycle root mean square value, in order to avoid redundant waveform point-level traversal, the system directly uses the statistical results of adjacent half-cycles to synthesize the full-cycle physical quantity.

[0117] U rms_full =sqrt((U rms_half_A 2 +U rms_half_B 2 ) / 2); Among them, U rms_full U is the root mean square value of the full-cycle wave. rms_half_A U is the root mean square value of the first half-cycle of the current waveform period. rms_half_B It is the root mean square value of the second half-cycle of the current waveform period.

[0118] In the parallel branch that performs root mean square calculation, the system calibrates and records the zero-crossing time sequence based on the sign flip events extracted from the narrowband fundamental waveform data, which serves as the basis for time-domain slicing of the subsequent spectrum division.

[0119] Step 502: In the second layer of the hierarchical computing scheduling architecture, the aggregation of intermediate indicators is triggered periodically according to a preset cycle aggregation window, specifically as follows: Using the full-cycle root mean square value generated in the first layer, perform root mean square calculation on multiple consecutive full-cycle root mean square values ​​to obtain the multi-cycle effective value; The moving average is obtained by averaging the effective values ​​of multiple multi-cycle waves generated continuously within a preset time span. Meanwhile, the zero-time sequence is used to determine the target number of the current analysis window, and discrete fixed-point spectrum analysis is performed on the full-band waveform data to obtain the amplitude of each harmonic component.

[0120] In this embodiment, the system uses a preset clock controller to wake up the indicator data layer operator every 200 milliseconds.

[0121] This layer operator reads the ten consecutive full-cycle root mean square values ​​accumulated in the underlying register and performs cross-cycle macroscopic energy equivalent aggregation.

[0122] U 10cyc =sqrt((1 / 10)*sum(U rms_full_m 2 )); Among them, U 10cyc To characterize the multi-cycle effective value of the 10-cycle convergence result, m is the full-cycle index, taking integer values ​​from 0 to 9, and U... rms_full_m Let m be the root mean square value of the full cycle participating in the aggregation.

[0123] Furthermore, the system constructs a queue containing fifteen consecutive sliding units over a 3-second time span and calculates its arithmetic average output.

[0124] U 3s_avg =(1 / 15)*sum(U 10cyc_j ); Among them, U 3s_avg U is the moving average, j is the index of the effective value sequence, and its value is an integer ranging from 0 to 14. 10cyc_j It represents the effective value of the j-th multi-cycle within a continuous statistical time span.

[0125] This moving statistical mean smooths out short-term energy oscillations in the power grid, providing data support for steady-state voltage assessment. Simultaneously, based on the frequency parameters mapped from the zero-crossing time sequence transmitted from the underlying layer, the system performs a discrete spectrum transformation with dynamic grid scaling on the full-band waveform data, outputting the amplitudes of the fundamental and multiple harmonic components.

[0126] Step 503: In the third layer of the hierarchical computing and scheduling architecture, the application results are triggered to output according to the standard statistical cycle of each indicator. Among them, the voltage deviation indicator calculation module, the three-phase unbalance indicator calculation module, and the voltage harmonic indicator calculation module jointly call the multi-cycle effective value output by the second layer as a shared input source. The voltage deviation indicator calculation module and the three-phase unbalance indicator calculation module reuse the sliding statistical mean, and the three-phase unbalance indicator calculation module and the voltage harmonic indicator calculation module reuse the amplitude of each harmonic component, thereby synchronously generating a set of power quality indicators.

[0127] In this step, the different power quality indicator logic branches at the top level no longer directly request the original waveform from memory to perform independent calculations starting from scratch. Instead, they access the registers at the bottom and intermediate levels using pointer references. Specifically, the voltage deviation calculation module calculates the relative deviation ratio by calling the sliding statistical mean and comparing it with the nominal voltage; the voltage harmonic indicator calculation module calls the amplitude values ​​of each harmonic component generated by the second layer to calculate the content rate.

[0128] For the three-phase unbalance index calculation module, the system uses a symmetrical component matrix to decouple the positive-sequence, negative-sequence, and zero-sequence components. In some optional implementations, when the power smart terminal is connected to a three-wire, zero-sequence-free physical system, the unbalance index calculation module provides an alternative linear accelerated calculation model that directly reuses the multi-cycle RMS values ​​of the line voltage between each phase.

[0129] β=(U AB 4 +U BC 4 +U CA 4 ) / (U AB 2 +U BC 2 +U CA 2 ) 2 ; Where β is the line voltage characteristic mapping parameter, U AB U BC U CA These are the multi-cycle RMS values ​​of the line voltage between each phase.

[0130] ε U2 =sqrt((1-sqrt(3-6*β)) / (1+sqrt(3-6*β)))*100%; Where, ε U2 is the negative order imbalance under the condition of no zero-order component, and sqrt is the square root operation.

[0131] In addition, the application output layer includes a voltage short-time flicker evaluation module. This module reuses the half-cycle RMS array from the first layer. After dividing it by the reference voltage to perform envelope normalization and square demodulation, the data is input to a bandpass weighted filter. This filter consists of a cascaded first-order high-pass filter and a sixth-order Butterworth low-pass filter, whose mathematical transfer function curve maps the visual perception characteristics of the human eye to 8.8Hz voltage fluctuations. After low-pass smoothing to obtain the transient flicker visual perception data, the system performs a cumulative probability distribution operation.

[0132] P st =sqrt(0.0314*P 0.1 +0.0525*P1+0.0657*P3+0.28*P 10 +0.08*P 50 ); Among them, P st For calculating the output value of short-time flicker, P 0.1 P1, P3, P 10 P 50 These are the instantaneous flicker assessment values ​​mapped to the time exceedance probabilities of 0.1%, 1%, 3%, 10%, and 50% on the cumulative probability distribution function curve, respectively.

[0133] The terminal index results of the above-mentioned operators are packaged together to form a set of power quality indicators that characterize the overall operational quality of the electrical network.

[0134] Through the three-layer operator reuse architecture described above, compared to the approach of needing to perform waveform traversal and root mean square calculation separately in the independent calculation mode of each index, the three application modules of voltage deviation, three-phase unbalance and voltage harmonics share the multi-cycle effective value calculation results of the second layer.

[0135] Taking the 10-cycle effective value as an example, in independent mode, each of the three modules needs to execute a complete N-point square-accumulation-square root process once. However, in this layered architecture, the process only needs to be executed once, and its output is consumed in parallel by the three modules through pointer references, thereby reducing the total number of floating-point operations at this level to one-third of that in independent mode.

[0136] The superposition effect of this reuse mechanism at each level enables the system to maintain the synchronous real-time output of all power quality indicators even under the constraint of limited processor clock frequency.

[0137] Example 6: Based on Example 5 above, this example further describes the specific steps of calculating the local fundamental frequency based on narrowband fundamental waveform data, and dynamically adjusting the number of sampling points in the analysis window for the full-band waveform data according to the local fundamental frequency. In one possible implementation, the steps include: Step 601: Monitor the sign variation of the narrowband fundamental waveform data to identify the zero-crossing point, and use linear interpolation between two adjacent sampling points to locate the precise zero-crossing time.

[0138] Specifically, after receiving the narrowband fundamental waveform data, the main control core unit calls the status monitoring operator to capture the numerical sign transformation of the time-domain sequence in real time.

[0139] For example, when two adjacent time-domain sampling points satisfy the condition that the value of the former point is negative and the value of the latter point is positive, the system determines that a positive zero-crossing event is generated, and locks these two sampling points as zero-crossing adjacent points.

[0140] Since there is a time quantization interval in discrete sampling, the actual zero physical intersection point is located between these two sampling points. The system uses an interpolation algorithm to fit the zero point position.

[0141] t zc =(n0+(abs(x b (n0)) / (abs(x b (n0))+abs(x b (n0+1)))))*(1 / f s ); Among them, t zc To pinpoint the exact zero-crossing time, n0 is the time-domain index of the discrete sampling point preceding the detected sign flip, abs is the absolute value operation, and x... b (n0) represents the narrowband fundamental voltage value at the previous discrete sampling point, x b (n0+1) represents the narrowband fundamental voltage value at the next discrete sampling point, f s The reference sampling rate for the path is set, for example, fixed at 12800Hz. This interpolation reduces the time axis discretization error caused by the sampling rate limitation, enabling the timing accuracy of a single zero-crossing event to reach sub-microsecond levels.

[0142] Step 602: Count the number of complete cycles defined by the precise zero-crossing time within the preset observation window, and obtain the local fundamental frequency based on the ratio of the number of complete cycles to the corresponding total time span.

[0143] In this embodiment, the system establishes a sliding time-domain queue in memory as a preset observation window, and the clock span of the preset observation window is set to 1 second.

[0144] The main control core unit accumulates consecutive zero-crossing events in the same direction within the time-domain queue and calculates the complete cycle number within the interval. The system obtains the total time span by reading the precise zero-crossing time of the last trigger in the queue and subtracting the precise zero-crossing time of the first trigger.

[0145] Local fundamental frequency flocal =N zc / (t zc_last -t zc_first ); Where, N zc t is the number of complete cycles within the preset observation window. zc_last t represents the precise zero-crossing time of the last zero-crossing point in the same direction within the window. zc_first This is the precise zero-crossing time of the first zero-crossing point in the same direction within the window. This frequency result smooths out instantaneous noise disturbances and can dynamically track the microscopic drift of the power frequency in the range of 49.5Hz to 50.5Hz.

[0146] Step 603: Based on the ratio of the reference sampling rate to the local fundamental frequency of the full-band waveform data, adaptively determine the number of target points corresponding to the current calculation window, and use the number of target points as the number of sampling points in the updated analysis window.

[0147] The main control core unit converts the fundamental frequency change into the physical point update of the spectrum truncation window in real time. Since national standards require harmonic analysis to cover ten complete fundamental frequency cycles, the system dynamically adjusts the data reading length based on the measured local fundamental frequency.

[0148] Number of sampling points N in the analysis window w =round(10*f s / f local ); Where round is the integer operation, f s The reference sampling rate for the entire frequency band is 12800Hz. When the local fundamental frequency deviates from the nominal value of 50Hz due to load variations, the number of sampling points in the analysis window is adaptively updated between 2535 and 2586 points to ensure that the edge of the truncated window always coincides with the zero-crossing boundary of the actual power frequency cycle.

[0149] Step 604: Within the truncated window defined by the number of sampling points in the analysis window, a windowing function is applied to the full-band waveform data to perform sidelobe suppression processing.

[0150] The main control core unit extracts full-band waveform data of the corresponding number of sampling points from the local shared buffer based on the number of sampling points in the currently updated analysis window, forming an independent analysis sequence.

[0151] To suppress spectral leakage caused by asymmetry at both ends of the window, the system calls the time-domain Hanning window array to perform element-level dot multiplication on the analysis sequence, reducing the signal weight at the truncation boundary and obtaining the windowed data sequence.

[0152] Step 605: Determine the precise fundamental frequency deviation harmonic frequency point based on the product of the local fundamental frequency and the target harmonic order.

[0153] Specifically, in order to avoid the conventional fast Fourier transform algorithm's requirement that the number of sampling points must meet the power of 2 limit and the problem of non-integer index alignment caused by power grid frequency drift, the system constructs a discrete fixed-point decoupled grid.

[0154] The main control core unit directly uses the real-time measured local fundamental frequency and the target harmonic order to perform multiplication operations.

[0155] f h =h*f local ; Among them, f h The value represents the point where the fundamental frequency deviates from the harmonic frequency, and h represents the target harmonic order, which is an integer ranging from 2 to 19. This frequency point is no longer bound to the fixed frequency range derived from the nominal 50Hz, but shifts synchronously with the actual power grid frequency trend.

[0156] Step 606: Using a recursive integral network, the discrete spectral amplitude of the windowed data is directly recursively calculated at the corresponding fundamental frequency deviation harmonic frequency points to obtain the amplitude of each harmonic component, thereby reducing spectral leakage caused by asynchronous sampling.

[0157] In this embodiment, the recursive integral network is implemented using an improved Gosser algorithm operator structure. The large kernel unit does not need to perform multi-point complex matrix multiplication, but instead takes the windowed data sequence as input and performs iterative recursion within the number of sampling points in the analysis window determined in step 603.

[0158] s(n)=x win (n)+2*cos(2*π*f h / f s )*s(n-1)-s(n-2); Where s(n) is the state sequence at the current time, x win (n) represents the full-band waveform data after windowing processing, cos is the cosine function, π is pi, and f h f is the point where the fundamental frequency deviates from the harmonic frequency in the current calculation. s The baseline sampling rate is s(n-1), the state sequence of the previous time step is s(n-2), and the state sequence of the second time step before that is s(n-2).

[0159] The initial boundary conditions s(-1) and s(-2) are both 0. The process starts from time index 0 and proceeds to the target point, triggering complex magnitude mapping at the endpoint.

[0160] Complex spectrum result X at the target harmonic h =s(N w )-e (-j*2*π*fh / fs) *s(N w -1); Where e is the base of the natural logarithm, j is the imaginary unit, and s(N) w ) represents the final state value after the iteration is completed, s(N) w -1) represents the state value at the penultimate time step. X is calculated... h The magnitude of each harmonic component is calculated and injected into the window function gain compensation coefficient, and finally the amplitude of each harmonic component is output.

[0161] Because the computational grid points of the recursive network achieve geometric overlap with the actual frequency conversion trajectory through parameter injection, spectral leakage is suppressed.

[0162] In some embodiments, it is assumed that the reference sampling rate of the full-band path is normalized to 1.0. Under the abrupt change in the power grid frequency, the normalized local fundamental frequency variation measured by linear interpolation is 0.00392.

[0163] Substituting this value into the formula, the number of target points N in the analysis window is calculated. w =round(10*1.0 / 0.00392)=2551. If the system needs to extract the 3rd harmonic at this time, the corresponding precise fundamental frequency deviation from the harmonic frequency is calculated as f. h =3 * 0.00392 = 0.01176. Let N... w =2551 and f h With 0.01176 input to the recursive integral network, the cosine characteristic coefficients are updated to 2*cos(2*π*0.01176 / 1.0)=1.9945. The state sequence s(n) is recursively processed for 2551 steps without relying on the power of 2 constraint. The signal energy after windowing is concentrated at the frequency offset grid point, and the amplitude ratio of the residual leakage term is suppressed, verifying the correctness of the closed-loop adaptive adjustment method.

[0164] Step 607: Monitor the variation difference between two consecutively updated local fundamental frequencies in real time.

[0165] The main control core unit introduces a differential comparison operator in the computing loop, which subtracts the local fundamental frequency value calculated and output in the current cycle from the local fundamental frequency value of the previous cycle latched in the local high-speed register and takes the absolute value to generate the variation difference.

[0166] Step 608: Based on the comparison results between the variation difference and the set threshold, control the statistical span of the preset observation window to perform adaptive mode switching.

[0167] The large core unit controls the response delay of data parsing through conditional branch instructions to cope with different steady-state and transient power grid conditions.

[0168] In the first execution path, when the variation difference does not exceed the set threshold, the statistical span of the preset observation window is maintained.

[0169] Specifically, the threshold is pre-configured to 0.1Hz. When the variation difference calculated by the system is less than or equal to 0.1Hz, it is determined that the current power grid operation is in the steady-state frequency small fluctuation range. The large core unit maintains a regular time domain queue with a span of 1 second to perform frequency statistics to ensure that the output results have a high signal-to-noise ratio and a frequency measurement resolution better than ±0.005Hz.

[0170] In the second execution path, when the variation difference exceeds the set threshold, it is determined that the power grid has experienced a sudden load change. The number of cycles used for frequency statistics is actively reduced, the preset observation window is switched to a fast frequency estimation window, and the response delay time of the number of sampling points in the analysis window fluctuating with frequency is shortened.

[0171] Specifically, when the variation difference exceeds 0.1Hz, the system detects a large-capacity impulsive load connection or a transient fault in the power grid. If the 1-second sliding statistical window is maintained at this time, the time integration effect will cause a significant backward delay in frequency adjustment, leading to distortion of the harmonic analysis window during the transient process. The main control core unit then cuts off the regular polling, reduces the number of statistical cycles to 3 complete cycles, and activates the fast frequency estimation window.

[0172] Fast frequency estimate f local_fast =3 / (t zc_3rd -t zc_0th ); Among them, t zc_3rd t represents the precise moment of the last zero-crossing point in the same direction within the current 3-cycle cutoff interval. zc_0th This is the precise moment of the first zero-crossing point in the same direction within this interval. This alternative mechanism dynamically reduces the overall response delay of window adjustment from 200 milliseconds to approximately 60 milliseconds, improving the full-band data tracking and analysis capability of power smart terminals under transient disturbance conditions.

[0173] Example 7: In one possible implementation, after obtaining the set of power quality indicators, the process of performing real-time fault recording based on a sliding benchmark, multi-timescale data freezing, and data interaction feedback to the power station includes the following steps: Step 701: Calculate the root mean square value of half-cycle for each channel of the full-band waveform data according to the half-cycle time scale, and monitor the root mean square value of half-cycle for each channel in real time.

[0174] Specifically, when the main control core unit runs in the first layer of the hierarchical computing scheduling architecture, it establishes an independent anomaly monitoring thread. This thread accesses the half-cycle root mean square value arrays continuously output by each voltage and current channel in parallel through a memory mapping mechanism.

[0175] In order to establish a reference benchmark for judging transient fluctuations in the power grid, the system maintains a sliding window in memory with a length that includes the first three complete waveform cycles, and calculates the average effective value of the corresponding phase sampling points within the window, which is used as a dynamically updated fault-free steady-state reference voltage.

[0176] Step 702: When the root mean square value of half-cycle of any channel continuously exceeds the set threshold number of points, and the instantaneous sampling value of waveform data of the corresponding channel exceeds the limit, a bidirectional transient event alarm is triggered, and a waveform recording task is started to extract and package the waveform data of the preset cycle before the trigger time and the preset cycle after the trigger time to generate a real-time fault waveform recording file.

[0177] In this embodiment, the system employs a bidirectional triggering mechanism of voltage sag and voltage swell to assess the grid fault status.

[0178] Specifically, when the monitoring logic determines that the instantaneous voltage values ​​of five consecutive sampling points are all lower than 80% of the average value of the sampling points corresponding to the previous three cycles, the system identifies a voltage sag event. Conversely, when the instantaneous voltage values ​​of five consecutive sampling points are all higher than 120% of the average value of the corresponding phase sampling points of the previous three cycles, the system identifies a voltage spurt event.

[0179] When any of the above boundary conditions are met, the system determines that the combined constraints of the number of consecutive points exceeding the set threshold and the instantaneous value exceeding the limit are satisfied, and then triggers a bidirectional transient event alarm and activates the background waveform recording task. Regarding the range of waveform data extraction, the system extracts waveform data from the ring buffer for the five cycles preceding the fault occurrence as the preceding preset cycles, extracts waveform data for up to 50 cycles during the fault occurrence process, and extracts waveform data for the 20 cycles after the fault state ends and recovers to the steady-state range as the subsequent preset cycles.

[0180] When the fault duration exceeds 50 cycles, the system performs a data pruning operation, retaining the first 25 cycles and the last 25 cycles of data segments. The extracted broadband waveform segments, along with the event timestamps, are packaged and encapsulated to generate a real-time fault waveform file for easy post-incident traceability.

[0181] In some embodiments, it is first determined whether the root mean square value of half-cycle of any channel exceeds the preset deviation threshold of the sliding reference (e.g., deviation ±20%) for N consecutive calculation cycles. If the condition is met, a pre-alarm state is entered. In the pre-alarm state, it is further determined whether the instantaneous value exceeds the limit.

[0182] Step 703: According to the preset statistical clocks at the second, minute, hour, day, and month levels, periodically extract the basic statistical items from the power quality index set.

[0183] The main control core unit maintains multiple independently running hardware timers, corresponding to timed trigger interrupts at the second, minute, hour, day, and month levels, respectively.

[0184] When any timer reaches its set count value, the system extracts the basic statistical items from the set of power quality indicators such as voltage deviation, frequency deviation, three-phase voltage imbalance, short-term voltage flicker, and long-term voltage flicker that have been calculated in the local register according to the interrupt service routine of that timer, and uses them as the data to be solidified for the corresponding time scale.

[0185] Step 704: Obtain the standard timestamp corresponding to the current system real-time clock, associate and encapsulate the extracted basic statistical items with the corresponding standard timestamp, generate a multi-timescale frozen dataset and store it in flash memory storage medium.

[0186] After obtaining the basic statistical items of each dimension, the system retrieves the current real-time clock register value, appends the standard timestamp containing year, month, day, hour, minute, and second information to the header of the data packet, performs memory serialization processing, and generates the corresponding multi-timescale frozen dataset.

[0187] By calling the external memory interface peripheral, the multi-timescale frozen dataset is written to the specified file allocation table sector in the terminal's built-in flash memory storage medium through a non-volatile storage protocol, thus achieving physical-level persistent data freezing.

[0188] Step 705: Receive the waveform reading command sent by the power master station through the communication network.

[0189] Specifically, the power smart terminal is equipped with an uplink communication module. When the terminal is in listening mode, it receives application layer data packets transmitted from the remote power master station via carrier wave, fiber optic, or wireless communication networks.

[0190] The communication protocol stack parses the received data packets, stripping away the network and transport layer headers to obtain the application layer payload containing specific control codes. When the parsed control code corresponds to file system access permissions and the instruction content is a request to retrieve abnormal waveform records, the system recognizes it as a read waveform recording instruction.

[0191] Step 706: In response to the read recording command, retrieve the corresponding real-time fault recording file from the preset storage path, and extract the name, file size, and global checksum of the real-time fault recording file.

[0192] First, extract the name and file size of the real-time fault recording file, and then perform a verification operation on the data content of the real-time fault recording file to obtain a global checksum.

[0193] In response to the aforementioned network interaction event, the main control core unit activates its internal file management subsystem. Based on the search criteria provided by the command parameters, the file management subsystem traverses the file directory tree within the preset storage path of the flash memory storage medium, locating the real-time fault recording file that matches the query time range. Upon successful location, the system executes a file attribute read operation, extracting the filename and file size (in bytes) from the file header control block, and performs a cyclic redundancy check (CRC) operation on the entire file data to generate the corresponding global checksum.

[0194] Step 707: Based on the standard communication protocol, organize the extracted name, file size, and global checksum into a response message and send the response message back to the power master station.

[0195] During the data backhaul phase, the main control core unit establishes a transmission buffer based on the standard communication protocol framework of the power grid specifications.

[0196] The system uses the name, file size, and global checksum extracted in step 706 as payloads to fill the data area of ​​the message, and automatically calculates the frame check sequence and appends it to the end of the frame.

[0197] After message assembly is complete, the system drives the uplink communication module to send the encapsulated response message to the physical link, confirming the response and providing data feedback to the power master station. Once the master station verifies the message, it can initiate a batch retrieval operation of the offset addresses of the waveform recording files based on the information provided in the message.

[0198] In summary, this application addresses the issues of bus blocking and latency accumulation that can easily occur when concurrently reading and writing low-level sampled data across multiple cores. It introduces a lock-free communication mechanism with dual serial numbers and memory barrier constraints. The reading end avoids pipeline suspension caused by traditional mutex locks by comparing the first and last serial numbers and supplementing with jump backtracking retrieval, thereby reducing the pipeline suspension overhead caused by traditional mutex locks and reducing cross-core data transfer latency.

[0199] In addition, to reduce the computational redundancy bottleneck caused by independent calculation of multiple time scale indicators, this application constructs a hierarchical computation directed acyclic graph scheduling architecture from the basic data layer to the application layer. By cross-module cross-reuse of basic operators such as half-cycle, multi-cycle effective values ​​and harmonic components, the total concurrency of floating-point operations is reduced, ensuring the real-time synchronous output of high-density electrical indicators.

[0200] In addition, the parallel separation filtering mechanism of the heterogeneous dual-path front end decouples the physical contradiction between broadband signal preservation and narrowband fundamental wave extraction, laying a clean data foundation for subsequent frequency tracking and multi-dimensional index diagnosis.

Claims

1. A method for calculating power quality using a smart power terminal, characterized in that, include: The original waveform data of the power grid multi-channels collected in real time by the cross-collection metering unit is obtained, downsampled and extracted, and the extracted data is input into the parallel full-band channel and narrowband fundamental channel for digital filtering to obtain full-band waveform data and narrowband fundamental waveform data. A dual-serial-number writing protocol is used to write full-band waveform data and narrowband fundamental waveform data into a shared memory queue, generating buffered waveform data frames. Read the buffered waveform data frames that have passed the consistency test from the shared memory queue, and parse out the full-band waveform data and narrowband fundamental waveform data in the buffered waveform data frames; Calculate the local fundamental frequency based on narrowband fundamental waveform data; The number of sampling points in the analysis window for the full-band waveform data is dynamically adjusted based on the local fundamental frequency, and the operator multiplexing calculation is performed on the full-band waveform data based on the pre-configured hierarchical computing and scheduling architecture to obtain a set of power quality indicators; A dual-sequence-number writing protocol is used to write full-band waveform data and narrowband fundamental waveform data into a shared memory queue, generating buffered waveform data frames, including: Get the global write sequence number of the current write operation; In the shared memory queue, the global write sequence number is written to the first preset field at the head of the current queue member as the pre-write sequence number; The full-band waveform data and narrow-band fundamental waveform data are sequentially stored into the data area of ​​the current queue member; Write the global write sequence number as the write sequence number in the second preset field at the end of the current queue member, update the queue head write pointer of the shared memory queue, and generate a buffered waveform data frame. Read buffered waveform data frames that have passed consistency checks from the shared memory queue, including: Read the queue head write pointer of the shared memory queue to determine the position of the target read frame; Obtain the pre-write sequence number and post-write sequence number of the data frame corresponding to the target read frame position; Compare the sequence number before and after the write operation to determine consistency. If the sequence number before and after writing are the same, the data frame is determined to be complete and is used as a buffered waveform data frame that passes the consistency test. If the sequence number before writing is inconsistent with the sequence number after writing, it is determined that the current data frame is in the middle of the writing process. The current data frame is skipped and the search is performed backtracking in the direction of the historical frame index until the complete historical data frame is obtained. Calculating local fundamental frequencies based on narrowband fundamental waveform data; and dynamically adjusting the number of sampling points in the analysis window for full-band waveform data based on the local fundamental frequencies, including: Sign variation monitoring is performed on narrowband fundamental waveform data to identify zero-crossing points, and linear interpolation is used between two adjacent sampling points to pinpoint the precise zero-crossing time; The number of complete cycles defined by the precise zero-crossing time within the preset observation window is counted, and the local fundamental frequency is obtained based on the ratio of the number of complete cycles to the corresponding total time span. Based on the ratio of the reference sampling rate to the local fundamental frequency of the full-band waveform data, the number of target points corresponding to the current calculation window is adaptively determined, and the number of target points is used as the number of sampling points in the updated analysis window.

2. The method according to claim 1, characterized in that, The original waveform data from multiple channels is downsampled and extracted. The extracted data is then input into parallel full-band and narrowband fundamental wave paths for digital filtering to obtain full-band waveform data and narrowband fundamental wave waveform data, including: Integer decimation and anti-aliasing low-pass filtering are performed on the multi-channel raw waveform data to obtain downsampled waveform data; The downsampled waveform data is processed by bandwidth-limited filtering in the first frequency band through a full-band path to obtain full-band waveform data; The downsampled waveform data is processed by bandpass filtering in the second frequency band through a narrowband fundamental wave path to extract the power frequency fundamental wave component and obtain narrowband fundamental wave waveform data.

3. The method according to claim 1, characterized in that, The original waveform data from multiple channels is downsampled and extracted. The extracted data is then input into parallel full-band and narrowband fundamental wave paths for digital filtering to obtain full-band waveform data and narrowband fundamental wave waveform data, specifically: Synchronous initial filtering and extraction processing are performed using hardware on the cross-sampling side to obtain hardware-filtered data. On the software side, the initial filtered waveform data from the hardware is split, and one of the branch data is used as the full-band waveform data. A software splitting algorithm was used to extract the fundamental component from the data of another branch and reconstruct the narrowband fundamental waveform data.

4. The method according to claim 1, characterized in that, It also includes the step of performing spectral analysis on the full-band waveform data using the number of sampling points in the analysis window to extract harmonic components, specifically: Within a truncated window defined by the number of sampling points in the analysis window, a windowing function is applied to the full-band waveform data to suppress sidelobes. The precise point of fundamental frequency deviation from harmonic frequency is determined by the product of the local fundamental frequency and the target harmonic order. By using a recursive integral network, the discrete spectral amplitude of the windowed data is directly recursively calculated at the corresponding fundamental frequency deviation from the harmonic frequency, so as to obtain the amplitude of each harmonic component and eliminate the spectral leakage caused by asynchronous sampling.

5. The method according to claim 1, characterized in that, The process of dynamically adjusting the number of sampling points in the analysis window for full-band waveform data based on the local fundamental frequency also includes a transient response switching step, specifically: Real-time monitoring of the variation difference between two consecutive updates of the local fundamental frequency; When the variation difference does not exceed the set threshold, the statistical span of the preset observation window is maintained; When the variation exceeds the set threshold, it is determined that a sudden load change has occurred in the power grid. The number of cycles used for frequency statistics is actively reduced, the preset observation window is switched to a fast frequency estimation window, and the response delay time of the number of sampling points in the analysis window fluctuating with frequency is shortened.

6. The method according to claim 1, characterized in that, During the process of writing the pre-write sequence number at the head of the current queue member, writing the full-band waveform data and the narrowband fundamental waveform data, and writing the post-write sequence number at the tail, instruction flow control is executed, specifically as follows: After writing the pre-write sequence number, a first memory barrier instruction is injected into the execution pipeline of the processor core performing the write operation to force the write operation of the global write sequence number to precede the memory write operation of subsequent waveform data. After the full-band waveform data and narrow-band fundamental waveform data are stored sequentially, a second memory barrier instruction is injected into the execution pipeline to force the write operation of the write sequence number to lag behind the memory write operation of the data area.

7. The method according to claim 1, characterized in that, After obtaining the set of power quality indicators, a multi-timescale data freezing step is also included, specifically: According to the preset statistical clocks at the second, minute, hour, day, and month levels, the basic statistical items in the power quality index set are periodically extracted; The extracted basic statistical items are associated and encapsulated with the corresponding standard timestamps to generate a multi-timescale frozen dataset, which is then stored in a flash memory storage medium.

Images