pull-down switch

Abstract

The pull-down switch includes a first NMOS transistor and a second NMOS transistor. A first current terminal and a body terminal of the first NMOS transistor are coupled to a power supply voltage rail. A second current terminal of the first NMOS transistor is coupled to a first current terminal of the second NMOS transistor. A second current terminal and a body terminal of the second NMOS transistor are coupled to an external IC terminal of an integrated circuit. A gate of both the first NMOS transistor and the second NMOS transistor is coupled to a control line.

Description

Technical Field

[0001] This invention relates to pull-down switches. Background Technology

[0002] Some semiconductor devices use pull-down switches to selectively bias external integrated circuit (IC) terminals (e.g., external IC pins, pads, bumps, or balls) to the power supply voltage rail. Summary of the Invention

[0003] In some embodiments, an integrated circuit (IC) includes an external IC terminal, a power voltage rail configured to provide a power supply voltage to the IC, and a first NMOS transistor. The first NMOS transistor includes a first current terminal coupled to the power voltage rail, a second current terminal coupled to the power voltage rail, a gate coupled to a control line, and a body terminal coupled to the power voltage rail. The integrated circuit also includes a second NMOS transistor, which includes a first current terminal coupled to the second current terminal of the first NMOS transistor, a second current terminal coupled to the external IC terminal, a gate coupled to the control line, and a body terminal coupled to the external IC terminal.

[0004] In another embodiment of the integrated circuit, the control line is set to an on-state voltage to turn on the first NMOS transistor and the second NMOS transistor, thereby biasing the external IC terminal through the power supply voltage rail via the first NMOS transistor and the second NMOS transistor.

[0005] In another embodiment of the integrated circuit, the control line is placed at an on-state voltage during operating conditions to disable other circuitry of the integrated circuit during operation.

[0006] In another embodiment of the integrated circuit, other circuit systems include test circuit systems coupled to an external IC terminal.

[0007] In another embodiment of the integrated circuit, the first NMOS transistor includes a first body region in the substrate of the integrated circuit, the first body region being biased by a power supply voltage rail through the body terminal of the first NMOS transistor, and the second NMOS transistor includes a second body region in the substrate, the second body region being biased by an external IC terminal through the body terminal of the second NMOS transistor, wherein the second body region is electrically isolated from the substrate of the first body region.

[0008] In another embodiment of the integrated circuit, the substrate includes at least one isolation structure for electrically isolating the second body region from other active regions of the substrate.

[0009] In another embodiment of the integrated circuit, at least one of the isolation structures is biased by a second power supply voltage rail, which is configured to provide a higher power supply voltage than the power supply voltage rail.

[0010] In another embodiment of the integrated circuit, the power supply voltage rail is the ground rail.

[0011] In another embodiment of the integrated circuit, an external IC terminal is configured to transmit a signal whose voltage may drop below the power supply voltage rail under at least some operating conditions.

[0012] In another embodiment of the integrated circuit, the first current terminal and body terminal of the first NMOS transistor are connected to the power supply voltage rail, the second current terminal of the first NMOS transistor is connected to the first current terminal of the second NMOS transistor, and the second current terminal and body terminal of the second NMOS transistor are connected to an external IC terminal.

[0013] In another embodiment of the integrated circuit, the second NMOS transistor has a different channel width than the first NMOS transistor.

[0014] In another embodiment of the integrated circuit, the first NMOS transistor and the second NMOS transistor are implemented in a driver circuit system of the integrated circuit, the driver circuit system including a pull-up transistor coupled to an external IC terminal.

[0015] In another embodiment of the integrated circuit, the second NMOS transistor includes an internal diode, wherein the body region of the second NMOS transistor serves as the anode region of the internal diode and the source region of the second NMOS transistor serves as the cathode of the internal diode, and the internal diode suppresses reverse current from the body terminal of the second NMOS transistor to the external IC terminal during reverse current conditions.

[0016] In another embodiment of the integrated circuit, during at least some reverse current conditions between the external IC terminal and the power supply voltage rail, the second NMOS transistor has a lower reverse current capacity than the first NMOS transistor, such that the second NMOS transistor limits the amount of reverse current passing through the first NMOS transistor.

[0017] In another embodiment of the integrated circuit, the power supply voltage rail is a low power supply voltage rail.

[0018] In other embodiments, the integrated circuit (IC) includes an external IC terminal, a power voltage rail configured to provide a power supply voltage to the IC, and a first NMOS transistor. The first NMOS transistor includes a first current terminal connected to the power voltage rail, a second current terminal connected to the power voltage rail, and a gate coupled to a control line. The integrated circuit includes a second NMOS transistor, which includes a first current terminal connected to a second current terminal of the first NMOS transistor, a second current terminal connected to the external IC terminal, and a gate coupled to a control line. The first NMOS transistor includes a first body region in the substrate of the integrated circuit that is biased by the power voltage rail, and the second NMOS transistor includes a second body region in the substrate that is biased by the external IC terminal, wherein the second body region is electrically isolated from the first body region substrate.

[0019] In another embodiment of the integrated circuit, the control line is set to an on-state voltage to turn on the first NMOS transistor and the second NMOS transistor, thereby biasing the external IC terminal through the power supply voltage rail via the first NMOS transistor and the second NMOS transistor.

[0020] In another embodiment of the integrated circuit, the second NMOS transistor includes an internal diode, wherein a second body region of the second NMOS transistor serves as the anode of the internal diode and a source region of the second NMOS transistor serves as the cathode of the internal diode, and the internal diode suppresses reverse current from the body terminal of the second NMOS transistor to the external IC terminal during reverse current conditions.

[0021] In another embodiment of the integrated circuit, the power supply voltage rail is the ground rail.

[0022] In another embodiment of the integrated circuit, during at least some reverse current conditions between the external IC terminal and the power supply voltage rail, the second NMOS transistor has a lower reverse current capacity than the first NMOS transistor, such that the second NMOS transistor limits the amount of reverse current passing through the first NMOS transistor.

[0023] Features specifically shown or described in one embodiment set forth herein may be implemented in other embodiments set forth herein. Attached Figure Description

[0024] The invention can be better understood by referring to the accompanying drawings, and many of the objectives, features and advantages of the invention will be apparent to those skilled in the art.

[0025] Figure 1 This is a circuit diagram of a pull-down switch using existing technology.

[0026] Figure 2 This is a partial cross-sectional side view of an existing integrated circuit.

[0027] Figure 3 It is a circuit diagram of existing technology circuits.

[0028] Figure 4 This is a partial cross-sectional side view of an existing integrated circuit.

[0029] Figure 5 This is a circuit diagram of a circuit system including a pull-down switch according to some embodiments of the present invention.

[0030] Figure 6 This is a partial cross-sectional side view of an integrated circuit according to some embodiments of the present invention.

[0031] Figure 7 This is a graph showing a performance comparison between a pull-down switch according to some embodiments of the present invention and a prior art pull-down switch.

[0032] Figure 8 This is a graph illustrating the performance of pull-down switches with different transistor width-to-size ratios according to some embodiments of the present invention.

[0033] Figure 9 This is a circuit diagram of a circuit system including a pull-down switch according to some embodiments of the present invention.

[0034] Unless otherwise specified, the same reference numerals are used to denote the same items in different figures. Figures are not necessarily drawn to scale. Detailed Implementation

[0035] The following provides a detailed description of embodiments of the present invention. This description is intended to illustrate the invention and should not be considered limiting.

[0036] As described herein, the pull-down switch includes a first NMOS transistor and a second NMOS transistor. The first current terminal and body terminal of the first NMOS transistor are coupled to the power supply voltage rail. The second current terminal of the first NMOS transistor is coupled to the first current terminal of the second NMOS transistor. The second current terminal and body terminal of the second NMOS transistor are coupled to external IC terminals of the integrated circuit. The gates of both the first and second NMOS transistors are coupled to control lines.

[0037] In some embodiments using this configuration, the second NMOS transistor has a lower reverse current capacity than the first NMOS transistor, which can make the total reverse current capacity of the pull-down switch lower than that of a pull-down switch that only includes the first NMOS transistor.

[0038] Integrated circuits may include external IC terminals that are coupled to other integrated circuits or electrical devices when implemented in a system. At certain times during the operation of the integrated circuit, at least some of these external IC terminals may be at a negative voltage or a voltage lower than the minimum supply voltage of the integrated circuit.

[0039] In some cases, additional features such as test features or protection features can be implemented using circuitry coupled to an external IC terminal of the integrated circuit. The operability of these features may require a pull-down switch to bias the external IC terminal to a low supply voltage rail. It may be desirable that the pull-down switch does not interfere with the normal operation of the integrated circuit.

[0040] In other cases, pull-down switches can be implemented in circuit systems used to drive output signals on external IC terminals, where the pull-down switch is used to bias the terminal to a low supply voltage to generate a low-voltage status signal. However, pull-down switches can be used in other applications within integrated circuits.

[0041] Figure 1 A circuit diagram of a prior art pull-down switch 101 implemented using an NMOS transistor 103 is shown. The source (S) and body (BT) 113 of transistor 103 are connected to a VSS power supply voltage rail 104, which provides a low supply voltage VSS to the integrated circuit of switch 101. The drain (D) of transistor 103 is connected to an external IC terminal 105. The gate of transistor 103 is connected to a control signal line asserted to turn on transistor 103, thereby biasing terminal 105 to the voltage of rail 104. Diodes 109 and 111 are internal to transistor 103. Diode 109 represents a diode formed by the body and drain regions of transistor 103. Diode 111 represents a diode formed by the body and source regions of transistor 103.

[0042] Figure 2 This is a partial cross-sectional side view of an integrated circuit 201 including an NMOS transistor 103. The integrated circuit 201 includes a substrate 203, which includes a substrate region 205 doped with P-type conductivity. The transistor 103 includes a body region 207 doped with P-type, and includes P-type body contacts 211 and 217 serving as body contacts and connected to a VSS power supply voltage rail 104. An N-type isolation trench 208 electrically isolates the body region 207 from the substrate region 205 for noise suppression. The trench 208 includes an N-type contact region with a higher N-type doping concentration (N+) connected to a VDD power supply voltage rail 221. The transistor 103 includes an N-type source region 213 connected to the VSS rail 104, an N-type drain region 215 connected to a terminal 105, and a gate 219 connected to a control line.

[0043] During certain operating conditions, the voltage at terminal 105 may drop below the voltage of the VSS rail 104. Even if switch 101 is intended to be off, where the control signal is not asserted, reverse current can still flow through transistor 103, particularly when the voltage at terminal 105 drops below the supply voltage VSS by an amount equal to the voltage threshold of transistor 103 (e.g., approximately 0.3 V). For example, refer back to the reference. Figure 1 If the voltage at terminal 105 is lower than the voltage at rail 104 by at least the voltage threshold of transistor 103 (assuming CONTROL is at the non-assertive voltage VSS), then NMOS transistor 103 will become on to conduct reverse current from its source (S) to its drain (D) through its channel region. Furthermore, because the body terminal 113 of transistor 103 is connected to VSS rail 104, reverse current will also flow through the body terminal and through the internal diode 109 to terminal 105.

[0044] This reverse current can cause offset variations, thus affecting the accuracy of terminal parameters and consequently reducing the accuracy of the integrated circuit parameters. In some cases, the amount of reverse current increases with increasing temperature. The amount of reverse current may also increase as the negative value of the voltage at terminal 105 becomes larger. Therefore, under certain operating conditions, the reverse current flowing from the VSS rail 104 through the NMOS transistor 103 to terminal 105 may affect circuit effectiveness. In some cases, excessive reverse current may cause voltage problems with the power supply voltage level and excessive power consumption.

[0045] Figure 3 This is a circuit diagram of a prior art ESD circuit 301 connected between an external IC terminal 305 and the VSS power supply rail 311. Circuit 301 includes two PNP transistors 309 and 307, which are connected in series at their emitters and bases. The collector of transistor 307 is connected to terminal 305, and the collector of transistor 309 is connected to the VSS rail 311.

[0046] Figure 4This is a partial cross-sectional side view of an integrated circuit 401 including circuit 301. Integrated circuit 401 includes a substrate 403. Substrate 403 includes a P-type substrate region 404, a P-well 407, and a P-well 411. P-type regions 413 and 415 serve as the collector and emitter of transistor 309, respectively. N-well 405 serves as the base region of transistor 309, and N-type region 414 serves as the base contact region of transistor 309. P-type regions 418 and 420 serve as the emitter and collector of transistor 307, respectively; N-well 409 serves as the base region of transistor 307, and N-type region 419 serves as the base contact region of transistor 307. P-type region 417 serves as a contact region of P-well 407 and is connected to VSS rail 311. P-type region 421 serves as a contact region of P-well 411 and is connected to VSS rail 311.

[0047] Figure 5 This is a circuit diagram of a pull-down switch 501 and other circuit systems according to some embodiments of the present invention. The pull-down switch 501 includes NMOS transistors 504 and 503 connected in series between an external IC terminal 507 and a VSS power supply rail 505. The source (S) of NMOS transistor 504 is connected to the VSS power supply rail 505. The drain (D) of transistor 504 is connected to the source of transistor 503. The drain of transistor 503 is connected to the external IC terminal 507. The gates (G) of transistors 503 and 504 are connected to a control line. The body (BT) of transistor 503 is connected to terminal 507. The body of transistor 504 is connected to rail 505. The control line provides a signal in an asserted high-voltage state to turn on transistors 503 and 504, thereby biasing terminal 507 to the power supply voltage of the VSS rail 505. In some embodiments, the VSS power supply voltage rail 505 is configured to provide a ground voltage, but in other embodiments, it may be configured to provide another power supply voltage, such as a negative voltage.

[0048] Diodes 508 and 509 are internal diodes of transistor 503, and diodes 511 and 513 are internal diodes of transistor 504. For example... Figure 6 As shown, diode 508 represents a diode formed by the body region 630 and drain region 635 of transistor 503, and diode 509 represents a diode formed by the body region 630 and source region 634 of transistor 503. Diode 511 represents a diode formed by the body region 620 and drain region 625 of transistor 504, and diode 513 represents a diode formed by the body region 620 and source region 624 of transistor 504.

[0049] Figure 5A comparator 521 is shown for testing operations to determine whether external terminal 507 is at a specific voltage. Comparator 521 includes a non-inverting input connected to terminal 507 and an inverting input connected to the VSS rail 505. In other embodiments, the inverting input may be connected to another voltage source, such as a reference voltage source, or may be coupled to an adjustable reference source. The comparator's output (DO) provides an indication of whether terminal 507 is at a voltage higher than VSS. The CONTROL signal is in a low voltage state to enable comparator 521 to perform test operations and in a high voltage state to pull terminal 507 to the voltage of rail 505, thereby disabling the test operation of comparator 521.

[0050] Terminal 507 is also connected to an external test circuit 541 (either via a test lead (not shown) in contact with terminal 507 or via another type of test structure). Circuit 541 is not located on the same integrated circuit as switch 501. In some embodiments, circuit 541 may be implemented in another integrated circuit (not shown), or may be implemented using multiple devices. Circuit 541 includes a resistor 545 and a variable current source 543 connected to each other. Current source 543 is connected to a positive voltage source VDD2. Resistor 545 is connected to a negative voltage source 547.

[0051] During testing, the current of current source 543 is varied to provide an adjustable test voltage at terminal 507. The comparator output DO provides an indication of whether terminal 507 is above the voltage of the inverting input of comparator 521 during testing. If pull-down switch 501 allows a large reverse current to flow from rail 505 to terminal 507 when terminal 507 is at a negative voltage, the voltage at terminal 507 will differ from the expected test voltage because the reverse current may flow through resistor 545, increasing the voltage drop across resistor 545. Therefore, this reverse current may affect the value indicated by DO and may thus be detrimental to the accuracy of the test parameters. However, as will be discussed later, when terminal 507 is at a voltage less than VSS, the configuration of switch 501 limits its reverse current capacity. Other embodiments may include other types of test circuitry systems and / or perform other types of tests.

[0052] Figure 6This is a partial cross-sectional side view of an integrated circuit 601 including transistors 504 and 503 according to some embodiments. In the illustrated embodiments, regions indicated by "N" or "P" indicate that the regions have a net conductivity dopant concentration of N-type dopant (e.g., arsenic, phosphorus) or P-type dopant (e.g., boron), respectively. A "+" next to N or P indicates a relatively high dopant concentration, and a "-" next to N or P indicates a relatively low dopant concentration. The integrated circuit 601 includes a substrate 603 having a P-type semiconductor substrate layer region 605 made of a semiconductor material (e.g., silicon, silicon germanium, silicon carbon, gallium nitride) doped with a P-type conductivity dopant (e.g., boron). In the illustrated embodiment, the substrate 603 has a bulk semiconductor configuration, but in other embodiments, it may have other configurations, such as a semiconductor-on-insulator (SOI) configuration.

[0053] In the illustrated embodiment, transistors 503 and 504 have a planar configuration, but in other embodiments, they may have other configurations, such as a finFET configuration or a gate-all-around configuration. Figure 6 The back-end layer, not shown, includes conductive interconnects separated by a dielectric material. These interconnects are used to interconnect semiconductor devices of integrated circuit 601 and to connect the semiconductor devices to external IC terminals (e.g., 507) or integrated circuit 601. In some embodiments, at least some interconnects (e.g., power supply voltage interconnects) may be located on the back side of substrate 603 (relative to...). Figure 6 The view shown is below substrate region 605. The symbols for internal diodes 508, 509, 511, and 513 are superimposed on... Figure 6 On the view.

[0054] Substrate region 605 includes contact region 607, which utilizes conductive interconnects (not shown, but shown in the diagram) located in the back-end layer of integrated circuit 601. Figure 6 (The symbolic representation) is connected to VSS rail 505.

[0055] Transistor 504 includes a P-type body region 620, which includes P-type body contact regions 623 and 626 connected to a VSS power supply voltage rail 505 for biasing the body region 620. The P-type body contact regions 623 and 626 serve as the body terminals of transistor 504. Contact regions 623 and 626 are connected via conductive interconnects (not shown, but...) located in the back-end layer (not shown) of integrated circuit 601. Figure 6The transistor 504 (symbolically represented in the image) is connected to the VSS rail 505. Rail 505 is connected to one or more external IC terminals (not shown), which are connected to an external VSS voltage source (not shown) when the integrated circuit 601 is implemented in the system. The N-type source region 624 and the N-type drain region 625 serve as the source and drain of transistor 504, respectively. Source region 624 is connected to the VSS power supply voltage rail 505, and drain region 625 is connected via conductive interconnects (not shown, but shown in the image). Figure 6 (symbolically indicated in the image) is connected to the source region 634 of transistor 503. The gate 621 is located above the body region 620 and above the channel region of the body region 620, which is laterally located between the source region 624 and the drain region 625.

[0056] Transistor 503 includes a P-type body region 630, which includes P-type body contact regions 633 and 636. These P-type body contact regions 633 and 636 are connected to an external IC terminal 507 for biasing the body region 630. The P-type body contact regions 633 and 636 serve as the body terminal of transistor 503. Contact regions 633 and 636 are connected to terminal 507 via conductive interconnects located in the back-end layer (not shown) of integrated circuit 601. Terminal 507 may be located on the outer surface (not shown) of integrated circuit 601. An N-type source region 634 and an N-type drain region 635 serve as the source and drain of transistor 503, respectively. Source region 634 is connected to drain region 625 of transistor 504, and drain region 635 is connected to terminal 507 via conductive interconnects (not shown but symbolically represented). The gate 631 is located above the body region 630 and above the channel region of the body region 630, which is laterally located between the source region 634 and the drain region 635.

[0057] The body region 630 of transistor 503 is substrate-isolated from the body region 620 of transistor 504. As used herein, "substrate electrical isolation" means that there is no continuous conduction path in substrates doped with the same conductivity type (e.g., no path between two P-type body regions in the substrate). Figure 6 As shown, body regions 620 and 630 are isolated by an N-type trench region 609, which includes N-type contact regions 610, 611, and 612 for applying bias voltage to the trench 609 via a VDD power supply voltage rail 641. The VDD power supply voltage rail 641 can be connected to one or more external VDD IC terminals (not shown) or to an internal power supply voltage source (not shown). In some embodiments, the trench 609 is formed by a horizontal N-type buried layer and a layer extending from the top surface of the substrate 603 (relative to the top surface of the substrate 603). Figure 6The view shown extends to contact the vertical N-type region formed by the buried N-type layer. However, other types of isolation structures can be utilized in other embodiments. For example, the body region can be isolated by dielectric vias and / or buried dielectric layers (not shown), or the isolation structure may include a combination of dielectric structures and oppositely doped regions.

[0058] The isolation structure, such as trench 609, allows body regions 620 and 630 to be substrate-isolated from each other, so that the body regions can be biased by two different sources without current flowing between the body regions. The isolation structure also electrically isolates body regions 620 and 630 from the substrate of other active regions of the integrated circuit.

[0059] The integrated circuit in other embodiments may have as Figure 6 Other alternatives and / or supplementary structures, features, and / or arrangements to the structures, features, and / or arrangements shown. For example, an integrated circuit may include silicide structures, extended regions, sidewall spacers, dielectric vias, and other buried layers. Furthermore, these regions may have, in addition to... Figure 6 Other shapes besides those shown. Also in some embodiments, body region 620 may not be electrically isolated from substrate region 605.

[0060] In other embodiments, integrated circuit 601 may include other semiconductor devices, such as other transistors, diodes, resistors, capacitors, etc., to implement other circuits (not shown). In some embodiments, integrated circuit 601 may include other pull-down switches (not shown) similar to switch 501 for other external IC terminals (not shown) of IC 601.

[0061] Return to reference Figure 5 External IC terminal 507 can be connected to signal or power lines from another integrated circuit or electrical device for implementation in the system. Other ICs or electrical devices may be located in the same IC package (not shown) as integrated circuit 601, or in other IC packages. Terminal 507 can carry communication signals, sensor signals, data signals, test signals, or other types of signals that are typically at a voltage equal to or higher than voltage VSS during operation. Terminal 507 can carry input signals, output signals, or both input and output signals. Integrated circuit 601 can be used in many different applications, such as communication systems, automotive electronics, industrial control systems, and data processing systems.

[0062] During operation, when the control signal is at a low voltage, the voltage at terminal 507 may drop below VSS, which could result in a reverse current condition where current flows from rail 505 to terminal 507. As discussed in the prior art, such a reverse current condition can adversely affect the performance of integrated circuit operation (e.g., test operation), or affect power supply voltage integrity or power consumption.

[0063] The addition of transistor 503 significantly reduces the amount of reverse current flowing through switch 501 under these conditions. With the body (BT) of transistor 503 connected to terminal 507 but not to the VSS rail 505, the amount of reverse current flowing through the source (S) of transistor 503 is reduced. Because the cathode of internal diode 509 is connected to the drain of transistor 504, current from the drain of transistor 504 is prevented from flowing through the body of transistor 503 to terminal 507. Therefore, even during reverse current conditions when transistor 503 is in a conducting state with current flowing from its source to its drain and then to terminal 507, the amount of reverse current flowing through transistor 503 to terminal 507 is reduced. Consequently, the amount of reverse current flowing from rail 505 to terminal 507 through switch 501 is reduced.

[0064] Furthermore, NMOS transistor 503 provides a secondary reverse current reduction effect for the pull-down switch. Because the internal diode 509 blocks the reverse current from flowing from the source of transistor 503 through the body of transistor 503 to the external IC terminal 507, the source-to-drain voltage drop across transistor 503 increases. Therefore, under reverse current conditions, the voltage at the drain of transistor 504 will be higher (i.e., less negative) than the voltage at terminal 507 (and for similar reverse current conditions, it may be higher (i.e., less negative) than the drain voltage of transistor 103). Consequently, the drain-to-gate voltage of transistor 504 will be lower than the drain-to-gate voltage of transistor 103. Because the drain of the NMOS transistor effectively becomes the source under reverse voltage conditions, the reduction in the drain-to-gate voltage of NMOS transistor 504 reduces the conductivity of transistor 504.

[0065] Figure 7 It is a graph based on simulation, showing the relationship with... Figure 5 The 501-like pull-down switch and Figure 1 The graph 701 shows the difference in reverse current between pull-down switches similar to switch 101 at various temperatures. The X-axis of graph 701 represents the voltage difference between the VSS rails (104, 505) and the external IC terminals (105, 507), where the voltage at the external IC terminals is lower than the voltage at the VSS rails in the range from 0V to -600 mV. Graph 701 includes a set of four lines 703 showing the amount of reverse current for pull-down switches similar to switch 501 at temperatures of -25°C, 25°C, 75°C, and 125°C within the voltage range. Graph 701 also includes a set of four lines 705 showing the difference in reverse current between the pull-down switches similar to switch 501 at temperatures of -25°C, 25°C, 75°C, and 125°C. Figure 1 The reverse current of switch 101 is similar to that of existing pull-down switches in the same voltage range and at the same four temperatures.

[0066] like Figure 7 As shown, for voltage differences smaller than the threshold voltage of the NMOS transistor (approximately 0.3 V), the reverse current is negligible at all temperatures. As the magnitude of the voltage difference increases (more negative values), the transistor in the pull-down switch begins to conduct reverse current. As the graph shows, the reverse current increases with increasing temperature, where for the same voltage difference, higher temperatures produce a larger reverse current.

[0067] like Figure 7 As shown, compared to a prior art pull-down switch (similar to switch 101), adding an NMOS transistor (similar to transistor 503) in addition to a pull-down switch similar to switch 501 significantly reduces the reverse current capacity of the switch at four given temperatures. For example, at -25 °C with a voltage difference of -600 mV, the pull-down switch similar to switch 501 conducts approximately -0.045 mA of reverse current, while the prior art switch similar to switch 101 conducts approximately -1.4 mA of reverse current. At 125 °C with a voltage difference of -600 mV, the pull-down switch similar to switch 501 conducts approximately -0.575 mA of reverse current, while the prior art pull-down switch similar to switch 101 conducts approximately -3.5 mA of reverse current. Other embodiments may provide different amounts of reverse current capacity reduction at similar temperatures and similar voltage differences.

[0068] Figure 8 It is a graph showing the percentage reduction in reverse current of switch 501 compared to that of prior art switch 101 over a temperature range, the switch 501 being based on the ratio (R) of the channel width (W503) of transistor 503 to the channel width (W504) of transistor 504. Figure 8 The values ​​in the curve are generated from a simulation of the -600 mV voltage difference between voltage VSS and terminal 507. For example... Figure 8 As shown, compared to prior art switches, the narrower the width of transistor 503 relative to the width of transistor 504, the greater the reduction in reverse current. For example, at 75 °C, with a ratio R of 10, the reverse current can be reduced by approximately 30%. However, at the same temperature, for R=1, a reduction of approximately 90% is achieved. Other embodiments may produce other results. Therefore, the width ratio of the NMOS transistors in the pull-down switch can be varied to achieve the desired reduction in reverse current.

[0069] In some embodiments, reducing the width of transistor 503 relative to the width of transistor 504 may affect the effectiveness of the pull-down switch pulling down the voltage of the external IC terminal during normal operation when there is no reverse current condition.

[0070] In other embodiments, the pull-down circuit may have other configurations and / or operate in different ways. For example, refer back to the reference. Figure 5 A pull-down circuit may include resistors or diodes in at least some of the current paths. For example, a pull-up circuit may include resistors or diodes in the path from the body of transistor 503 to terminal 507, or in the path from the body of transistor 504 to VSS rail 505.

[0071] Figure 9 A circuit diagram of a driver circuit 901 according to some embodiments of the present invention is shown. The driver circuit 901 includes a pull-up PMOS transistor 905 connected to the VDD power supply rail and an external IC terminal 907, and a pull-down switch 903 connected to the VSS power supply rail and terminal 907. The pull-down switch 903 includes two NMOS transistors (not shown) connected in series, and... Figure 5 The pull-down switch 501 is similar. The control signals CONTROLPU and CONTROLPD are used to pull terminal 907 to VDD (when CONTROLPU and CONTROLPD are low), pull terminal 907 to VSS (when CONTROLPU and CONTROLPD are high), or disable driver circuit 901 (when CONTROLPU is high and CONTROLPD is low).

[0072] In some embodiments, when driver circuitry 901 is disabled (when CONTROLPU is high and CONTROLPD is low), there may be a moment when terminal 907 is coupled to external circuitry that may be at a negative voltage. If pull-down switch 903 allows a large amount of reverse current at this time, it may affect voltage VSS and / or undesirably consume power in the integrated circuit of circuitry 901. Therefore, by providing a pull-down switch with reduced reverse current capacity, the integrated circuit can consume less power and / or have better voltage regulation. In other embodiments, other driver circuitry may have other configurations.

[0073] As described herein, a pull-down circuit that conducts significantly less reverse current under reverse current conditions can be provided by providing a pull-down circuit with two NMOS transistors series-coupled between the power supply voltage rail and an external IC terminal, wherein the body terminal of one NMOS transistor is coupled to the power supply voltage rail and the body terminal of the other NMOS transistor is coupled to the external IC terminal. This feature can improve the efficiency and parameter accuracy of integrated circuit operation, improve power supply voltage integrity, and / or reduce power consumption during reverse current conditions.

[0074] The drain and source are the current terminals of a MOSFET, and the gate is the control terminal. As used herein, two devices are coupled to each other by means of interconnection or by means of coupling through at least one other device in the current path. For example, see reference... Figure 5 The drain of NMOS transistor 504 is coupled to the source of NMOS transistor 503 by means of being connected to the source of NMOS transistor 503. The drain of NMOS transistor 504 is coupled to terminal 507 through NMOS transistor 503.

[0075] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that further changes and modifications can be made based on the teachings herein without departing from the invention and its broader aspects, and therefore, the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. An integrated circuit IC, characterized in that, include: External IC terminal; A power supply voltage rail, configured to provide a power supply voltage to the IC; A first NMOS transistor, the first NMOS transistor including a first current terminal coupled to the power supply voltage rail, a second current terminal, a gate coupled to a control line, and a body terminal coupled to the power supply voltage rail; The second NMOS transistor includes a first current terminal coupled to the second current terminal of the first NMOS transistor, a second current terminal coupled to the external IC terminal, a gate coupled to the control line, and a body terminal coupled to the external IC terminal.

2. The integrated circuit according to claim 1, characterized in that, The control line is set to an on-state voltage to turn on the first NMOS transistor and the second NMOS transistor, thereby applying a bias voltage to the external IC terminal through the power supply voltage rail via the first NMOS transistor and the second NMOS transistor.

3. The integrated circuit according to claim 2, characterized in that, The control line is placed at an on-state voltage during operating conditions to disable other circuitry of the integrated circuit during operation.

4. The integrated circuit according to claim 3, characterized in that, The other circuit systems include test circuit systems coupled to the external IC.

5. The integrated circuit according to claim 1, characterized in that, The first NMOS transistor includes a first body region in the substrate of the integrated circuit, the first body region being biased by the power supply voltage rail through the body terminal of the first NMOS transistor, the second NMOS transistor includes a second body region in the substrate, the second body region being biased by the external IC terminal through the body terminal of the second NMOS transistor, wherein the second body region is electrically isolated from the substrate of the first body region.

6. The integrated circuit according to claim 5, characterized in that, The substrate includes at least one isolation structure for electrically isolating the second body region from other active regions of the substrate.

7. The integrated circuit according to claim 6, characterized in that, At least one of the isolation structures is biased by a second power supply voltage rail, which is configured to provide a higher power supply voltage than the power supply voltage rail.

8. The integrated circuit according to claim 1, characterized in that, The power supply voltage rail is the ground rail.

9. The integrated circuit according to claim 1, characterized in that, The external IC terminal is configured to transmit a signal whose voltage may drop below the power supply voltage rail under at least some operating conditions.

10. An integrated circuit IC, characterized in that, include: External IC terminal; A power supply voltage rail, configured to provide a power supply voltage to the IC; A first NMOS transistor, the first NMOS transistor including a first current terminal connected to the power supply voltage rail, a second current terminal and a gate coupled to a control line; The second NMOS transistor includes a first current terminal connected to the second current terminal of the first NMOS transistor, a second current terminal connected to the external IC terminal, and a gate coupled to the control line. The first NMOS transistor includes a first body region in the substrate of the integrated circuit that is biased by the power supply voltage rail, and the second NMOS transistor includes a second body region in the substrate that is biased by the external IC terminal, wherein the second body region is electrically isolated from the substrate of the first body region.

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