Novel rail-to-rail comparator circuit
By adopting a combination design of P-type and N-type differential pairs in the comparator, the problem of limited input common mode range of the traditional comparator is solved, effective operation at any input level is achieved, and the input range is expanded.
Patent Information
- Application Number
- CN202420221429.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-30
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-01-30
AI Technical Summary
The input common mode range of traditional comparators is limited and cannot operate at any input level, especially when the input common mode level is lower than the transistor turn-on voltage.
A new rail-to-rail comparator circuit is designed, using a combination of P-type differential pairs and N-type differential pairs to control the working states of both based on the input signal, ensuring that they can work effectively at different input common mode levels, thereby enlarging the Enter range.
The comparator's working ability at any input level is realized, and the input common mode range is expanded, so that the comparator can operate effectively at low and high input levels.
Smart Images
Figure CN222321501U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a novel rail-to-rail comparator circuit. Background Art
[0002] Comparators are widely used in the conversion process of analog signals to digital signals. In the analog-to-digital conversion process, the input must first be sampled. Then, the sampled signal is used to determine the digital value of the analog signal through the comparator. In order to be able to set the reference voltage arbitrarily, the comparator is required to have a rail-to-rail input common-mode range. Most comparators are designed based on high-gain op amps, and the input stage is an N-type differential pair or a P-type differential pair, which results in a limited input common-mode range.
[0003] Traditional comparators using N-type differential pair input stages are Figure 1 As shown in the figure, the N-type differential pair allows the input common-mode level to work only when it is greater than the turn-on voltage of the transistor. The disadvantage of this method is that when the input common-mode level is lower than the turn-on voltage of the transistor, the comparator cannot function and the input range is limited. Utility Model Content
[0004] In order to achieve the above objectives, this application adopts the following technical solutions:
[0005] The present application provides a novel rail-to-rail comparator circuit, comprising: an input stage circuit and an output stage circuit, wherein the input stage circuit is connected to the output stage circuit; the input stage circuit comprises a P-type differential pair and an N-type differential pair; the input stage circuit controls the operation of the P-type differential pair and the N-type differential pair according to a received input signal, and outputs a comparison result through the output stage circuit.
[0006] Through the above technical solution, the N-type differential pair and the P-type differential pair are used at the same time. When the input common mode level is low, the P-type differential pair works, when the input common mode level is high, the N-type differential pair works, and when the input common mode level is medium, the two pairs of differential pairs work together, thereby achieving a rail-to-rail input common mode range of the comparator.
[0007] Specifically, the input stage circuit includes a non-inverting input terminal and an inverting input terminal.
[0008] Specifically, the P-type differential pair includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6; the source of MOS tube M1 is connected to the source of MOS tube M2, the source of MOS tube M3 and the source of MOS tube M4 at the same time, the gate of MOS tube M1 is connected to the gate of MOS tube M3, and the drain of MOS tube M1 is connected to the drain of MOS tube M5 and the output stage circuit at the same time; the gate of MOS tube M2 is connected to the gate of MOS tube M4, and the drain of MOS tube M2 is connected to the drain of MOS tube M6 and the output stage circuit at the same time; the drain of MOS tube M3 is connected to the drain of MOS tube M4 and the N-type differential pair at the same time; the source of MOS tube M5 is connected to the source of MOS tube M6 and the N-type differential pair at the same time; the gate of MOS tube M1, the gate of MOS tube M3 and the gate of MOS tube M5 are respectively connected to the same direction input terminal; the gate of MOS tube M2, the gate of MOS tube M4 and the gate of MOS tube M6 are respectively connected to the reverse input terminal.
[0009] Specifically, the N-type differential pair includes: MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M 10 、MOS tube M 11 And MOS tube M 12 The gate of MOS tube M7 is connected to the gate of MOS tube M9, and the drain of MOS tube M8 is connected to the gate of MOS tube M9. 11 The drain and output stage circuit of MOS tube M7 is connected to the source of MOS tube M9 and the source of MOS tube M 10 The source of the MOS tube M8 and the output stage circuit; the gate of the MOS tube M8 is connected to the MOS tube M 10 The gate of MOS tube M8 is connected to the drain of MOS tube M 12 The drain of MOS tube M9 is also connected to the output stage circuit; the drain of MOS tube M 10 The drain of MOS tube M5 and the drain of MOS tube M6; MOS tube M 11 The source of MOS tube M is connected to 12 The source of the MOS tube M3, the drain of the MOS tube M4, the gate of the MOS tube M7, the gate of the MOS tube M9 and the gate of the MOS tube M 11 The gates of the MOS tube M8 and the MOS tube M 10 The gate and MOS tube M 12 The gates of are connected to the reverse input terminals respectively.
[0010] Specifically, the output stage circuit includes: MOS tube M 13 、MOS tube M 14 、MOS tube M 15 、MOS tube M 16、MOS tube M 17 、MOS tube M 18 、MOS tube M 19 And MOS tube M 20 ;MOS tube M 13 The gate of the MOS tube M is connected 14 The gate of MOS tube M 13 The drain of MOS tube M is connected to 15 The source of the MOS tube M7, the drain of the MOS tube M 11 The drain of MOS tube M 13 The source of MOS tube M1, the source of MOS tube M2, the source of MOS tube M3, the source of MOS tube M4, the source of MOS tube M5, the source of MOS tube M6, the drain of MOS tube M9 and the drain of MOS tube M 10 The drain of MOS tube M 14 The drain of MOS tube M is connected to 16 The source of the MOS tube M8, the drain of the MOS tube M 12 The drain of MOS tube M 15 The gate of the MOS tube M is connected 16 The gate of MOS tube M 15 The drain of MOS tube M is connected to 17 The drain of MOS tube M 19 The gate and MOS tube M 20 Gate of MOS tube M 16 The drain of MOS tube M is connected to 18 The drain and output end of MOS tube M 17 The gate of the MOS tube M is connected 18 The gate of MOS tube M 17 The source of MOS tube M is connected to 19 The drain of MOS tube M1 and the drain of MOS tube M5; MOS tube M 19 The source of the MOS tube M7 is connected to the source of the MOS tube M8, the source of the MOS tube M9, and the source of the MOS tube M 10 The source of MOS tube M 11 The source of MOS tube M 12 The source and MOS tube M 20 The source.
[0011] Specifically, MOS tube M 17 The gate and MOS tube M 18 The gates are biased by a voltage V b1 ;MOS tube M 15 The gate and MOS tube M 16 The gates are biased by a voltage V b2;MOS tube M 13 The gate and MOS tube M 14 The gates are biased by a voltage V b3 .
[0012] Through the above technical solutions, V b1 、V b2 、V b3 is an externally generated fixed voltage, V b1 As MOS tube M 17 , MOS tube M 18 The gate input voltage, V b2 As MOS tube M 15 , MOS tube M 16 The gate input voltage, V b3 As MOS tube M 13 , MOS tube M 14 The gate input voltage of MOS tube M 13 -M 18 Working in saturation region.
[0013] Specifically, it also includes a first ammeter, a second ammeter, a third ammeter, a fourth ammeter, a fifth ammeter and a sixth ammeter; one end of the first ammeter is simultaneously connected to the source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4 and one end of the second ammeter, and the other end of the first ammeter is simultaneously connected to the other end of the second ammeter, one end of the third ammeter, the source of the MOS tube M4 and the other end of the first ammeter. 13 The source and MOS tube M 14 The other end of the third ammeter is connected to the source of the MOS tube M5, the source of the MOS tube M6, the drain of the MOS tube M9 and the MOS tube M 10 One end of the fourth ammeter is simultaneously connected to the source of the MOS tube M7, the source of the MOS tube M8, the source of the MOS tube M9, the source of the MOS tube M 10 The source of the fourth ammeter and one end of the fifth ammeter, and the other end of the fourth ammeter is connected to the other end of the fifth ammeter, one end of the sixth ammeter, and the MOS tube M 19 The source and MOS tube M 20 One end of the sixth current meter is connected to the MOS tube M 11 The source of MOS tube M 12 The other end of the sixth ammeter is connected to the source of the MOS tube M3, the drain of the MOS tube M4, and the drain of the MOS tube M5. 19 The source of MOS tube M 20 The source.
[0014] The beneficial effects of this application are as follows:
[0015] By using an N-type differential pair and a P-type differential pair, when the input common-mode level is low, the P-type differential pair works, when the input common-mode level is high, the N-type differential pair works, and when the input common-mode level is medium, the two pairs of differential pairs work together. By using a rail-to-rail input stage, the input range is expanded, allowing the comparator to work at any input level. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present application. It will be easy to recognize other embodiments and many expected advantages of the embodiments because they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with each other. The same reference numerals refer to corresponding similar parts.
[0017] Figure 1 is a circuit diagram of a novel rail-to-rail comparator circuit according to an embodiment of the present application. DETAILED DESCRIPTION
[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and are shown by illustrative specific embodiments in which the present application can be practiced. To this end, directional terms, such as "top", "bottom", "left", "right", "up", "down", etc., are used with reference to the orientation of the figures described. Because the components of the embodiments can be positioned in several different orientations, directional terms are used for the purpose of illustration and are by no means limiting. It should be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be adopted in a limiting sense, and the scope of the present application is defined by the appended claims.
[0019] Figure 1 is a schematic diagram of a novel rail-to-rail comparator circuit according to an embodiment of the present application, such as Figure 1 As shown, a novel rail-to-rail comparator circuit includes: an input stage circuit and an output stage circuit, the input stage circuit is connected to the output stage circuit; the input stage circuit includes a P-type differential pair and an N-type differential pair; the input stage circuit controls the P-type differential pair and the N-type differential pair to work according to the received input signal, and outputs the comparison result through the output stage circuit.
[0020] Through the above technical solution, the N-type differential pair and the P-type differential pair are used at the same time. When the input common mode level is low, the P-type differential pair works, when the input common mode level is high, the N-type differential pair works, and when the input common mode level is medium, the two pairs of differential pairs work together, thereby achieving a rail-to-rail input common mode range of the comparator.
[0021] Specifically, the input stage circuit includes a non-inverting input terminal and an inverting input terminal.
[0022] Specifically, the P-type differential pair includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6; the source of MOS tube M1 is connected to the source of MOS tube M2, the source of MOS tube M3 and the source of MOS tube M4 at the same time, the gate of MOS tube M1 is connected to the gate of MOS tube M3, and the drain of MOS tube M1 is connected to the drain of MOS tube M5 and the output stage circuit at the same time; the gate of MOS tube M2 is connected to the gate of MOS tube M4, and the drain of MOS tube M2 is connected to the drain of MOS tube M6 and the output stage circuit at the same time; the drain of MOS tube M3 is connected to the drain of MOS tube M4 and the N-type differential pair at the same time; the source of MOS tube M5 is connected to the source of MOS tube M6 and the N-type differential pair at the same time; the gate of MOS tube M1, the gate of MOS tube M3 and the gate of MOS tube M5 are respectively connected to the same direction input terminal; the gate of MOS tube M2, the gate of MOS tube M4 and the gate of MOS tube M6 are respectively connected to the reverse input terminal.
[0023] Specifically, the N-type differential pair includes: MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M 10 、MOS tube M 11 And MOS tube M 12 The gate of MOS tube M7 is connected to the gate of MOS tube M9, and the drain of MOS tube M8 is connected to the gate of MOS tube M9. 11 The drain and output stage circuit of MOS tube M7 is connected to the source of MOS tube M9 and the source of MOS tube M 10 The source of the MOS tube M8 and the output stage circuit; the gate of the MOS tube M8 is connected to the MOS tube M 10 The gate of MOS tube M8 is connected to the drain of MOS tube M 12 The drain of MOS tube M9 is also connected to the output stage circuit; the drain of MOS tube M 10 The drain of MOS tube M5 and the drain of MOS tube M6; MOS tube M 11 The source of MOS tube M is connected to 12 The source of the MOS tube M3, the drain of the MOS tube M4, the gate of the MOS tube M7, the gate of the MOS tube M9 and the gate of the MOS tube M 11 The gates of the MOS tube M8 and the MOS tube M 10 The gate and MOS tube M 12 The gates of are connected to the reverse input terminals respectively.
[0024] Specifically, the output stage circuit includes: MOS tube M 13 、MOS tube M14 、MOS tube M 15 、MOS tube M 16 、MOS tube M 17 、MOS tube M 18 、MOS tube M 19 And MOS tube M 20 ;MOS tube M 13 The gate of the MOS tube M is connected 14 The gate of MOS tube M 13 The drain of MOS tube M is connected to 15 The source of the MOS tube M7, the drain of the MOS tube M 11 The drain of MOS tube M 13 The source of MOS tube M1, the source of MOS tube M2, the source of MOS tube M3, the source of MOS tube M4, the source of MOS tube M5, the source of MOS tube M6, the drain of MOS tube M9 and the drain of MOS tube M 10 The drain of MOS tube M 14 The drain of MOS tube M is connected to 16 The source of the MOS tube M8, the drain of the MOS tube M 12 The drain of MOS tube M 15 The gate of the MOS tube M is connected 16 The gate of MOS tube M 15 The drain of MOS tube M is connected to 17 The drain of MOS tube M 19 The gate and MOS tube M 20 Gate of MOS tube M 16 The drain of MOS tube M is connected to 18 The drain and output end of MOS tube M 17 The gate of the MOS tube M is connected 18 The gate of MOS tube M 17 The source of MOS tube M is connected to 19 The drain of MOS tube M1 and the drain of MOS tube M5; MOS tube M 19 The source of the MOS tube M7 is connected to the source of the MOS tube M8, the source of the MOS tube M9, and the source of the MOS tube M 10 The source of MOS tube M 11 The source of MOS tube M 12 The source and MOS tube M 20 The source.
[0025] Specifically, MOS tube M 17 The gate and MOS tube M 18 The gates are biased by a voltage V b1 ;MOS tube M 15The gate and MOS tube M 16 The gates are biased by a voltage V b2 ;MOS tube M 13 The gate and MOS tube M 14 The gates are biased by a voltage V b3 .
[0026] Through the above technical solutions, V b1 、V b2 、V b3 is an externally generated fixed voltage, V b1 As MOS tube M 17 , MOS tube M 18 The gate input voltage, V b2 As MOS tube M 15 , MOS tube M 16 The gate input voltage, V b3 As MOS tube M 13 , MOS tube M 14 The gate input voltage of MOS tube M 13 -M 18 Working in saturation region.
[0027] Specifically, it also includes a first ammeter, a second ammeter, a third ammeter, a fourth ammeter, a fifth ammeter and a sixth ammeter; one end of the first ammeter is simultaneously connected to the source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4 and one end of the second ammeter, and the other end of the first ammeter is simultaneously connected to the other end of the second ammeter, one end of the third ammeter, the source of the MOS tube M4 and the other end of the first ammeter. 13 The source and MOS tube M 14 The other end of the third ammeter is connected to the source of the MOS tube M5, the source of the MOS tube M6, the drain of the MOS tube M9 and the MOS tube M 10 One end of the fourth ammeter is simultaneously connected to the source of the MOS tube M7, the source of the MOS tube M8, the source of the MOS tube M9, the source of the MOS tube M 10 The source of the fourth ammeter and one end of the fifth ammeter, and the other end of the fourth ammeter is connected to the other end of the fifth ammeter, one end of the sixth ammeter, and the MOS tube M 19 The source and MOS tube M 20 One end of the sixth current meter is connected to the MOS tube M 11 The source of MOS tube M 12 The other end of the sixth ammeter is connected to the source of the MOS tube M3, the drain of the MOS tube M4, and the drain of the MOS tube M5. 19 The source of MOS tube M 20 The source.
[0028] During use, there may be three states: high, medium, and low input common-mode levels;
[0029] State 1: When the input common-mode level is high, the N-type differential pair operates, and MOS transistors M7, M8, M9, M 10 , M 11 , M 12 conduct; MOS transistors M1, M2, M3, M4, M5, and M6 are cutoff; at this time, only MOS transistors M1, M2, M5, and M6 contribute signal current; at this time, if V + > V - , then MOS transistors M8 and M 12 conduct less current, resulting in an increase in the current of MOS transistor M 16 , then the source voltage of MOS transistor M 16 rises, causing the output voltage to rise. If V+ <V-, then MOS transistors M8 and M 12 conduct more current, resulting in a decrease in the current of MOS transistor M 16 , then the source voltage of M 16 drops, causing the output voltage to drop.
[0030] State 2: When the input common-mode level is medium, both the p-type and N-type differential pairs operate, and MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M 10 , M 11 , M 12 all conduct. At this time, MOS transistors M1, M2, M5, M7, M8, M 11 , M 12 contribute signal current; at this time, if V + > V - , then MOS transistors M2 and M6 conduct more current, resulting in the current of MOS transistor M 20 being greater than that of MOS transistor M 19 , then the drain voltage of MOS transistor M 20 rises, causing the output voltage to rise. MOS transistors M8 and M 12 conduct less current, resulting in an increase in the current of MOS transistor M 16 , then the source voltage of MOS transistor M 16 rises, causing the output voltage to rise. If V + < V -, more current flows through MOS tube M1 and MOS tube M5, causing MOS tube M 19 The current is greater than that of MOS tube M 20 , then MOS tube M 20 The drain voltage of MOS tube M8 is reduced, resulting in a decrease in output voltage. 12 More current flows through the MOS tube, causing 16 The current of MOS tube M 16 The source voltage decreases, causing the output voltage to decrease.
[0031] State 3: When the input common mode level is low, the P-type differential pair works, then MOS tubes M7, M8, M9, and M 10 、MOS tube M 11 、MOS tube M 12 MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6 are turned on; at this time, only MOS tube M7, MOS tube M8, MOS tube M 11 、MOS tube M 12 Contribute signal current; at this time if V + >V - , more current flows through MOS tube M2 and MOS tube M6, causing MOS tube M 20 The current is greater than that of MOS tube M 19 , then MOS tube M 20 The drain voltage of the MOSFET increases, resulting in an increase in the output voltage. + <V - , more current flows through MOS tube M1 and MOS tube M5, causing MOS tube M 19 The current is greater than that of MOS tube M 20 , then MOS tube M 20 The drain voltage decreases, causing the output voltage to decrease.
[0032] Obviously, those skilled in the art can make various modifications and changes to the embodiments of the present application without departing from the spirit and scope of the present application. In this way, if these modifications and changes are within the scope of the claims of the present application and their equivalents, the present application is also intended to cover these modifications and changes. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are recorded in mutually different dependent claims does not indicate that the combination of these measures cannot be used to profit. Any figure mark in the claims should not be considered to limit the scope.
Claims
1. A novel rail-to-rail comparator circuit, characterized in that: include: An input stage circuit and an output stage circuit, wherein the input stage circuit is connected to the output stage circuit; the input stage circuit comprises a P-type differential pair and an N-type differential pair; The input stage circuit controls the operation of the P-type differential pair and the N-type differential pair according to the received input signal, and outputs the comparison result through the output stage circuit.
2. A novel rail-to-rail comparator circuit according to claim 1, characterized in that: The input stage circuit comprises a non-inverting input terminal and a reverse input terminal.
3. A novel rail-to-rail comparator circuit according to claim 2, characterized in that: The P-type differential pair includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6; the source of the MOS tube M1 is connected to the source of the MOS tube M2, the source of the MOS tube M3 and the source of the MOS tube M4, the gate of the MOS tube M1 is connected to the gate of the MOS tube M3, the drain of the MOS tube M1 is connected to the drain of the MOS tube M5 and the output stage circuit; the gate of the MOS tube M2 is connected to the gate of the MOS tube M4, the gate of the MOS tube M5 ... The drain of the MOS tube M2 is simultaneously connected to the drain of the MOS tube M6 and the output stage circuit; the drain of the MOS tube M3 is simultaneously connected to the drain of the MOS tube M4 and the N-type differential pair; the source of the MOS tube M5 is simultaneously connected to the source of the MOS tube M6 and the N-type differential pair; the gate of the MOS tube M1, the gate of the MOS tube M3 and the gate of the MOS tube M5 are respectively connected to the same-direction input terminal; the gate of the MOS tube M2, the gate of the MOS tube M4 and the gate of the MOS tube M6 are respectively connected to the reverse input terminal.
4. A novel rail-to-rail comparator circuit according to claim 3, characterized in that: The N-type differential pair includes: MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M 10 、MOS tube M 11 And MOS tube M 12 The gate of the MOS tube M7 is connected to the gate of the MOS tube M9, and the drain of the MOS tube M8 is also connected to the gate of the MOS tube M9. 11 The drain of the MOS tube M7 is connected to the source of the MOS tube M9, the source of the MOS tube M 10 The source of the MOS tube M8 and the output stage circuit; the gate of the MOS tube M8 is connected to the MOS tube M 10 The gate of the MOS tube M8 is connected to the drain of the MOS tube M 12 The drain of the MOS tube M9 is also connected to the drain of the MOS tube M 10 The drain of the MOS tube M5 and the drain of the MOS tube M6; the MOS tube M 11 The source of the MOS tube M is connected to 12 The source electrode of the MOS tube M7, the gate electrode of the MOS tube M9 and the gate electrode of the MOS tube M 11 The gates of the MOS tube M8 and the MOS tube M 10 The gate and the MOS tube M 12 The gates are respectively connected to the inverting input terminals.
5. A novel rail-to-rail comparator circuit according to claim 4, characterized in that: The output stage circuit includes: MOS tube M 13 、MOS tube M 14 、MOS tube M 15 、MOS tube M 16 、MOS tube M 17 、MOS tube M 18 、MOS tube M 19 And MOS tube M 20 ; The MOS tube M 13 The gate of the MOS tube M is connected 14 The gate of the MOS tube M 13 The drain of the MOS tube M is connected to 15 The source of the MOS tube M7, the drain of the MOS tube M 11 The drain of the MOS tube M 13 The source of the MOS tube M1 is connected to the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M5, the source of the MOS tube M6, the drain of the MOS tube M9 and the drain of the MOS tube M 10 The drain of the MOS tube M 14 The drain of the MOS tube M is connected to 16 The source of the MOS tube M8, the drain of the MOS tube M 12 The drain of the MOS tube M 15 The gate of the MOS tube M is connected 16 The gate of the MOS tube M 15 The drain of the MOS tube M is connected to 17 The drain of the MOS tube M 19 The gate and the MOS tube M 20 The gate of the MOS tube M 16 The drain of the MOS tube M is connected to 18 The drain and output end of the MOS tube M 17 The gate of the MOS tube M is connected 18 The gate of the MOS tube M 17 The source of the MOS tube M is connected to 19 The drain of the MOS tube M1 and the drain of the MOS tube M5; the MOS tube M 19 The source of the MOS tube M7 is connected to the source of the MOS tube M8, the source of the MOS tube M9, the source of the MOS tube M 10 The source of the MOS tube M 11 The source of the MOS tube M 12 The source and the MOS tube M 20 The source.
6. A novel rail-to-rail comparator circuit according to claim 5, characterized in that: MOS tube M 17 The gate and the MOS tube M 18 The gates are biased by a voltage V b1 ; The MOS tube M 15 The gate and the MOS tube M 16 The gates are biased by a voltage V b2 ;The MOS tube M 13 The gate and the MOS tube M 14 The gates are biased by a voltage V b3 .
7. A novel rail-to-rail comparator circuit according to claim 5, characterized in that: The invention also includes a first ammeter, a second ammeter, a third ammeter, a fourth ammeter, a fifth ammeter and a sixth ammeter; one end of the first ammeter is simultaneously connected to the source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4 and one end of the second ammeter, and the other end of the first ammeter is simultaneously connected to the other end of the second ammeter, one end of the third ammeter, the source of the MOS tube M4 and one end of the second ammeter. 13 The source and the MOS tube M 14 The other end of the third ammeter is simultaneously connected to the source of the MOS tube M5, the source of the MOS tube M6, the drain of the MOS tube M9 and the drain of the MOS tube M 10 One end of the fourth ammeter is simultaneously connected to the source of the MOS tube M7, the source of the MOS tube M8, the source of the MOS tube M9, the source of the MOS tube M 10 The source of the fourth ammeter and one end of the fifth ammeter, and the other end of the fourth ammeter is connected to the other end of the fifth ammeter, one end of the sixth ammeter, the MOS tube M 19 The source and the MOS tube M 20 The source of One end of the sixth ammeter is connected to the MOS tube M 11 The source of the MOS tube M 12 The other end of the sixth ammeter is connected to the source of the MOS tube M3, the drain of the MOS tube M4, and the other end of the sixth ammeter is connected to the source of the MOS tube M3, the drain of the MOS tube M4. 19 The source of the MOS tube M 20 The source.