Charging and discharging circuit applied to display panel and display panel

Abstract

The utility model relates to a charging and discharging circuit applied to a display panel and the display panel, and the charging and discharging circuit comprises a first diode, a second diode, a third diode, a resistor and a first capacitor. The first diode, the second diode and the third diode are sequentially connected in series, and the resistor is connected between the first diode and the second diode in series; the common end of the second diode and the third diode is connected with one end of a first capacitor, and the other end of the capacitor is grounded; the common end, connected with the first diode, of the resistor is connected with one end of a power management integrated circuit in the display panel, and the common end, connected with the first diode, of the third diode is connected with one end of a source display chip in the display panel. According to the charging and discharging circuit provided by the embodiment of the invention, the Source IC is loaded in time when the Source IC is pumped, and the Source IC is recovered to normal voltage in a short time, so that the problem of abnormal display of the Source IC caused by too long pumping time is avoided.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to a charging and discharging circuit applied to a display panel and a display panel. Background Art

[0002] The current display screen will cause the Source IC (source display chip) to be abnormal during the electrostatic discharge (ESD) test and then perform a self-recovery reset. A normal restart requires a millisecond-level response to not affect the viewing of the screen display.

[0003] like Figure 1 The connection circuit between the power management integrated circuit (Power Management IC, PMIC) and the Source IC shown in the figure, Vin supplies power to the PMIC, and then the PMIC generates positive voltage AVDD and negative voltage AVEE through Boost and buck respectively; due to the excessive pumping current, AVDD and AVEE are abnormal and cannot be powered normally. It takes nearly 1s to restore the normal voltage. The specific AVDD and AVEE waveforms are as follows Figure 2 As shown. It can be seen that there is a momentary high current when the Source IC restarts, that is, a transient high current when the power is on. The Source IC will be unloaded, and the front-end supply voltage PMIC cannot meet the instantaneous unloading of the Source IC, resulting in the Source IC being unable to restart in a short time, causing a black screen. Utility Model Content

[0004] The present application provides a charging and discharging circuit and a display panel applied to a display panel, so as to solve the problem in the prior art that the Source IC displays abnormally due to a long draw time.

[0005] In a first aspect, the present application provides a charging and discharging circuit applied to a display panel, the charging and discharging circuit comprising: a first diode, a second diode, a third diode, a resistor and a first capacitor; wherein the first diode, the second diode, and the third diode are connected in series in sequence, and the resistor is connected in series between the first diode and the second diode; a common end of the second diode and the third diode is connected to one end of the first capacitor, and the other end of the capacitor is grounded; a common end of the resistor connected to the first diode is connected to one end of a power management integrated circuit in the display panel, and a common end of the third diode connected to the first diode is connected to one end of a source display chip in the display panel.

[0006] Optionally, the number of the charging and discharging circuits is 2; one of the charging and discharging circuits is connected in series on a link between the power management integrated circuit and the source display chip for transmitting a positive voltage, and the other of the charging and discharging circuits is connected in series on a link between the power management integrated circuit and the source display chip for transmitting a negative voltage.

[0007] Optionally, when the charging and discharging circuit is connected in series on a link for transmitting a positive voltage, the common end of the resistor connected to the anode of the first diode is connected to one end of the power management integrated circuit, and the common end of the cathode of the third diode connected to the cathode of the first diode is connected to one end of the source display chip.

[0008] Optionally, when the charging and discharging circuit is connected in series on a link for transmitting a negative voltage, the common end of the resistor connected to the cathode of the first diode is connected to one end of the power management integrated circuit, and the common end of the third diode anode connected to the anode of the first diode is connected to one end of the source display chip.

[0009] Optionally, the display panel includes a second capacitor connected to the positive voltage transmission link and a third capacitor connected to the negative voltage transmission link; the capacitance values ​​of the second capacitor and the third capacitor are equal, and the capacitance value of the first capacitor is at least 10 times the capacitance value of the second capacitor.

[0010] Optionally, the resistance of the resistor is greater than the resistance of the source display chip.

[0011] In a second aspect, the present application provides a display panel including the charging and discharging circuit described in the first aspect.

[0012] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: through the charging and discharging circuit of the embodiment of the present application, when the power management integrated circuit has an input voltage Vin, C1 in the charging and discharging circuit will be charged, and when the Source IC is unloaded, the Source IC can be discharged based on C1, that is, the charging and discharging circuit of the embodiment of the present application can supply load to the Source IC in time when the Source IC is unloaded, and restore the normal voltage in a relatively short time, thereby avoiding the problem of abnormal display of the Source IC due to too long unloading time. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present utility model, and together with the description, are used to explain the principles of the present utility model.

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0015] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0016] Figure 1 A schematic diagram of a circuit for connecting a PMIC and a Source IC in the prior art;

[0017] Figure 2 A waveform diagram of a Source IC when it is unloaded in the prior art;

[0018] Figure 3 A schematic diagram of a charging and discharging circuit provided in an embodiment of the present application;

[0019] Figure 4 An optional schematic diagram of a charging and discharging circuit provided in an embodiment of the present application;

[0020] Figure 5 A flow chart of an anti-load extraction method based on a charge and discharge circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0023] Figure 3A schematic diagram of a charging and discharging circuit applied to a display panel provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the charge and discharge circuit includes: a first diode D1, a second diode D2, a third diode D3, a resistor R1 and a first capacitor C1;

[0024] The first diode D1, the second diode D2, and the third diode D3 are connected in series in sequence, and a resistor R1 is connected in series between the first diode D1 and the second diode D2; a common end of the second diode D2 and the third diode D3 is connected to one end of the first capacitor C1, and the other end of the capacitor C1 is grounded;

[0025] The common end of the resistor R1 and the first diode D1 is connected to one end of the PMIC in the display panel, and the common end of the third diode D3 and the first diode D1 is connected to one end of the source display chip (Source IC) in the display panel.

[0026] Through the charge and discharge circuit of the embodiment of the present application, when the PMIC has an input voltage Vin, C1 in the charge and discharge circuit will be charged, and when the Source IC is unloaded, the Source IC can be discharged based on C1, that is, the charge and discharge circuit of the embodiment of the present application can supply load to the Source IC in time when the Source IC is unloaded, and restore the normal voltage in a relatively short time, thereby avoiding the problem of abnormal display of the Source IC due to too long unloading time.

[0027] In an optional implementation of the embodiment of the present application, the number of the charge and discharge circuits in the embodiment of the present application is 2; one charge and discharge circuit is connected in series to the link between the PMIC and the source display chip for transmitting the positive voltage, and the other charge and discharge circuit is connected in series to the link between the PMIC and the source display chip for transmitting the negative voltage. It can be seen that in the embodiment of the present application, both AVDD and AVEE can be charged based on the charge and discharge circuit, and then the Source IC can be loaded in time when the Source IC is unloaded. The two charge and discharge circuits discharge the Source IC at the same time when the Source IC is unloaded, which can further shorten the time to restore the normal voltage.

[0028] like Figure 4As shown, when the charge-discharge circuit is connected in series to the link for transmitting the positive voltage, the common end connected to the anode of the resistor R1 and the first diode D1 is connected to one end of the PMIC, and the common end connected to the cathode of the third diode D3 and the cathode of the first diode D1 is connected to one end of the source display chip. When the charge-discharge circuit is connected in series to the link for transmitting the negative voltage, the common end connected to the cathode of the resistor R1 and the first diode D1 is connected to one end of the PMIC, and the common end connected to the anode of the third diode D3 and the anode of the first diode D1 is connected to one end of the source display chip.

[0029] It should be noted that the common terminal in the embodiment of the present application is as follows Figure 4 Black dots in the.

[0030] In the embodiment of the present application, during the charging and discharging process, the first diode D1 is used to prevent the first capacitor C1 from discharging to the PMIC during normal operation to ensure that C1 can only flow in one direction to the Source IC for use, and to supply load in time to ensure that the Source IC can restore the normal voltage in a short time during the unloading process, so as not to affect its display effect. The second diode D2 prevents the current flowing through the third diode D3 from flowing to the first capacitor C1 first, causing abnormal power-on timing. The third diode D3 is used to prevent the original circuit from causing a phase short, that is, the current does not pass through the resistor R1, the first transistor D1, and the first capacitor C1, and can also prevent the first capacitor C1 from back-injecting current from the original circuit.

[0031] Furthermore, in the embodiment of the present application, the display panel includes a second capacitor C2 connected to the positive voltage transmission link and a third capacitor C3 connected to the negative voltage transmission link; the capacitance values ​​of the second capacitor C2 and the third capacitor C3 are equal, and the capacitance value of the first capacitor C1 is at least 10 times the capacitance value of the second capacitor C2.

[0032] In a specific example, the values ​​of the second capacitor C2 and the third capacitor C3 can be 4.7uf, and the value of the first capacitor C1 is at least 10 times the value of the second capacitor C2, so the specific value can be 47uf or more. It can be seen that the capacitance of the first capacitor C1 in the embodiment of the present application is several times (more than 10 times) the energy storage capacitor of the original circuit (C2, C3) for energy storage, so that when the Source IC is restarted and unloaded when it is subjected to ESD, it can be supplied in time to ensure the normal operation of the Source IC.

[0033] In an optional implementation of the embodiment of the present application, the resistance of the resistor R1 in the embodiment of the present application is greater than the resistance of the source display chip. In the specific example, the resistance of the source display chip can be 10Ω, then the value of the resistor R1 can be greater than 10Ω, such as 12Ω, and the specific value can be set accordingly according to actual needs. Since the impedance of the RC circuit in the charging and discharging circuit is greater than the original circuit, based on this, at the moment of power-on, the voltage still passes through the original low-impedance path to reach the Source IC, thereby solving the abnormal electrical timing and the slow rise of AVDD and AVEE. In addition, when the power-on is completed and the load is supplied normally, the resistor can limit the current to slowly charge the first capacitor C1 to avoid excessive current in the display panel, resulting in saturation and failure to start.

[0034] The anti-load removal method in the implementation of the present application is explained below in conjunction with the charging and discharging circuit in the above-mentioned embodiment of the present application. Figure 5 As shown, the steps of the method include:

[0035] Step 501, supplying power to the source display chip and charging the first capacitor C1 when supplying power to the PMIC;

[0036] In this regard, when power is supplied to the PMIC, the resistance of the resistor R1 is greater than the resistance of the source display chip, so the current first flows from the PMIC to the source display chip Source IC, and after the source display chip is powered on and normally supplied, the current flows to the first capacitor C1 through the resistor R1 and the second diode D2 for slow charging. After the first capacitor C1 is saturated, since the first diode D1 and the third diode D3 limit the discharge of C1, only the first capacitor C1 can be charged when power is supplied to the PMIC.

[0037] Step 502 : When the source display chip is drawing current, the first capacitor C1 discharges to the source display chip.

[0038] When the Source IC is unloaded indiscriminately, the first capacitor C1 can be discharged unidirectionally and quickly, that is, the large-capacitance capacitor (C1) can be used to supply the load in time, thus solving the problem of abnormal display when the Source IC is unloaded in the prior art.

[0039] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0040] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0041] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0042] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features applied herein.

Claims

1. A charging and discharging circuit applied to a display panel, characterized in that: The charging and discharging circuit comprises: a first diode, a second diode, a third diode, a resistor and a first capacitor; The first diode, the second diode, and the third diode are connected in series in sequence, and the resistor is connected in series between the first diode and the second diode; a common end of the second diode and the third diode is connected to one end of the first capacitor, and the other end of the capacitor is grounded; The common end of the resistor and the first diode is connected to one end of a power management integrated circuit in the display panel, and the common end of the third diode and the first diode is connected to one end of a source display chip in the display panel.

2. The charge and discharge circuit according to claim 1, characterized in that: The number of the charging and discharging circuits is 2; one of the charging and discharging circuits is connected in series on a link between the power management integrated circuit and the source display chip for transmitting a positive voltage, and the other of the charging and discharging circuits is connected in series on a link between the power management integrated circuit and the source display chip for transmitting a negative voltage.

3. The charge and discharge circuit according to claim 2, characterized in that: When the charging and discharging circuit is connected in series on a link for transmitting a positive voltage, the common end of the resistor connected to the anode of the first diode is connected to one end of the power management integrated circuit, and the common end of the cathode of the third diode connected to the cathode of the first diode is connected to one end of the source display chip.

4. The charge and discharge circuit according to claim 2, characterized in that: When the charge and discharge circuit is connected in series on a link for transmitting a negative voltage, the common end of the resistor connected to the cathode of the first diode is connected to one end of the power management integrated circuit, and the common end of the third diode anode connected to the anode of the first diode is connected to one end of the source display chip.

5. The charge and discharge circuit according to claim 2, characterized in that: The display panel includes a second capacitor connected to a positive voltage transmission link and a third capacitor connected to a negative voltage transmission link; the capacitance values ​​of the second capacitor and the third capacitor are equal, and the capacitance value of the first capacitor is at least 10 times the capacitance value of the second capacitor.

6. The charge and discharge circuit according to claim 1, characterized in that: The resistance of the resistor is greater than the resistance of the source display chip.

7. A display panel, characterized in that: The charging and discharging circuit comprises the charging and discharging circuit according to any one of claims 1 to 6.

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