Analog-to-digital conversion circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides an analog-to-digital conversion circuit, a chip and electronic equipment, the analog-to-digital conversion circuit comprises a first analog-to-digital conversion module, the first analog-to-digital conversion module comprises an adjustable sampling capacitor, and the adjustable sampling capacitor is connected with a to-be-measured module to sample to-be-measured voltage output by the to-be-measured module; the input end of the capacitance control module is connected with the module to be measured, and the output end of the capacitance control module is connected with the adjustable sampling capacitor; when the voltage to be measured is located in any set voltage interval, the capacitance control module corrects the capacitance value of the adjustable sampling capacitor to a standard set threshold value based on the set voltage interval where the voltage to be measured is located. The non-linear problem of an adjustable sampling capacitor of the first analog-to-digital conversion module is avoided, and finally high-precision measurement of the electric quantity of the battery is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an analog-to-digital conversion circuit, a chip and an electronic device. Background Art

[0002] At present, batteries are widely used in new energy vehicles, power tools, electric vehicles, drones, industrial robots, mobile phones, notebooks, wearable devices and other fields. In these application scenarios, it is necessary to accurately monitor the battery power to display the battery usage status. In related technologies, the battery power can be measured by a Sigma-Delta ADC (abbreviated as SDADC). The sampling capacitor of the Sigma-Delta ADC is charged in the sampling phase to obtain a charge signal, and then the Sigma-Delta ADC measures the charge signal in the integration phase, and finally calculates the battery power.

[0003] However, when the battery voltage is different, the sampling capacitor will be subject to nonlinear limitations. For example, the ideal capacitance value of the sampling capacitor is 1pF. When the battery voltage is 80V, the actual capacitance value of the sampling capacitor may be 1.003pF; and when the battery voltage is 70V, the actual capacitance value of the sampling capacitor may be 1.002pF. This leads to capacitance distortion, which in turn causes errors in the charge signal obtained by charging the sampling capacitor of the Σ-Δ analog-to-digital converter during the sampling phase, ultimately leading to errors in the measurement of the battery charge. Utility Model Content

[0004] In view of the above problems, the embodiments of the present application provide an analog-to-digital conversion circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides an analog-to-digital conversion circuit, including a first analog-to-digital conversion module, the first analog-to-digital conversion module including an adjustable sampling capacitor, the adjustable sampling capacitor being connected to the module to be measured to sample the voltage to be measured output by the module to be measured; a capacitance control module, the input end of the capacitance control module being connected to the module to be measured, and the output end of the capacitance control module being connected to the adjustable sampling capacitor; wherein, when the voltage to be measured is located in any set voltage interval, the capacitance control module corrects the capacitance value of the adjustable sampling capacitor to a standard set threshold value based on the set voltage interval in which the voltage to be measured is located.

[0006] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned analog-to-digital conversion circuit.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or analog-to-digital conversion circuit.

[0008] The present application connects the input end of the capacitance control module to the module to be measured, and connects the output end of the capacitance control module to the adjustable sampling capacitor. When the voltage to be measured is in any set voltage interval, the capacitance control module can correct the capacitance value of the adjustable sampling capacitor to the standard set threshold value according to the set voltage interval in which the voltage to be measured is located. That is to say, no matter how the measured voltage changes, the capacitance value of the adjustable sampling capacitor can be guaranteed to be within the standard set threshold value, thereby avoiding the nonlinear problem of the adjustable sampling capacitor of the first analog-to-digital conversion module, and ultimately ensuring high-precision measurement of the battery power.

[0009] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of a delta-sigma analog-to-digital converter in the related art is shown.

[0012] Figure 2 A schematic diagram showing how the capacitance of the sampling capacitor varies with voltage.

[0013] Figure 3 A schematic diagram of an analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0014] Figure 4 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0015] Figure 5 A schematic diagram of an adjustable sampling capacitor in an embodiment of the present application is shown.

[0016] Figure 6 Another schematic diagram of an adjustable sampling capacitor in an embodiment of the present application is shown.

[0017] Figure 7 Another schematic diagram of an adjustable sampling capacitor in an embodiment of the present application is shown.

[0018] Figure 8 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0019] Fig. 9 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0020] Fig.10 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0021] Fig.11 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0022] Fig.12 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0023] Fig.13 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0024] Fig.14 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown.

[0025] Fig.15 A schematic diagram of a capacitance control module in an embodiment of the present application is shown.

[0026] Among them, 10 is a first analog-to-digital conversion module, 20 is a capacitance control module, 21 is a second analog-to-digital conversion module, 22 is a numerical comparison module, 221 is a numerical comparator, 23 is a step-down module, and 201 is a threshold comparator unit;

[0027] Module 1 to be measured, voltage Vin to be measured, adjustable sampling capacitor Cs, first comparator COMPa, second comparator COMPb, first XOR gate XORa, first main capacitor Csx, first sub-capacitor Csy, first parallel switch Sp. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0029] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0030] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0031] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0032] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0033] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0034] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0035] At present, the battery capacity is usually measured using a delta-sigma analog-to-digital converter, see Figure 1 , Figure 1A schematic diagram of a Δ-Σ analog-to-digital converter in the related art is shown, wherein the Δ-Σ analog-to-digital converter mainly includes a sampling circuit for sampling the input voltage Vin and outputting a sampled charge signal Vin*C2, a feedback circuit for outputting a feedback charge signal Vdac*C1 according to a reference voltage signal Vdac, an integrator for charge integration of the input voltage signal Vin and the charge signal corresponding to the reference voltage signal Vdac, a comparator for comparing the output voltage of the integrator, and a counter for recording the output result of the comparator. During the measurement process, the output result of the comparator controls the positive and negative of the reference voltage signal Vref, so that the output result of the integrator is near the reference voltage VR during multiple cycles.

[0036] For example, during one cycle, when the output voltage of the integrator is greater than the reference voltage VR, the comparator controls the feedback circuit to output a feedback charge signal according to the negative reference voltage signal -Vdac during the next cycle, so that the output voltage of the integrator decreases; conversely, during one cycle, when the output voltage of the integrator is less than the reference voltage VR, the comparator controls the feedback circuit to output a feedback charge signal according to the positive reference voltage signal +Vdac during the next cycle, so that the output voltage of the integrator increases.

[0037] During the operation of the Δ-Σ analog-to-digital converter, the integrator performs charge integration on the input voltage signal Vin and the reference voltage signal Vdac in each cycle. Since the output result of the integrator is close to the reference voltage VR after multiple cycles and can be ignored, the input voltage signal Vin, the reference voltage signal Vdac, the number of times the positive reference voltage signal +Vdac is fed back, and the number of times the negative reference voltage signal -Vdac is fed back satisfy the following relationship:

[0038] Vin*(X1+X2)*C2=(Vdac*X1*C1)-(Vdac*X2*C1)

[0039] Among them, X1 is the number of times the positive reference voltage signal +Vdac is fed back, X2 is the number of times the negative reference voltage signal -Vdac is fed back, C1 is the capacitor corresponding to the output feedback charge signal in the feedback circuit, and C2 is the capacitor corresponding to the output sampling charge signal in the sampling capacitor.

[0040] Therefore, the input voltage signal Vin can be calculated according to the following formula:

[0041]

[0042] It can be seen from the above formula that the size of the input voltage signal Vin can be quantified according to the difference between the positive and negative times of the feedback reference voltage, the size of the reference voltage Vdac, the sampling circuit and the capacitance of the feedback circuit, and finally the conversion code of the input voltage signal Vin can be obtained from the counter.

[0043] However, when the battery voltages are different, the sampling capacitor is limited by nonlinearity, for example, see Figure 2 , Figure 2 A schematic diagram showing the variation of the capacitance value of the sampling capacitor with voltage in the related art is shown. The ideal capacitance value of the sampling capacitor is 1pF. When the battery voltage is 80V, the actual capacitance value of the sampling capacitor may be 1.003pF; and when the battery voltage is 70V, the actual capacitance value of the sampling capacitor may be 1.002pF, which leads to the distortion of the sampling capacitor, and thus causes errors in the charge signal obtained by charging the sampling capacitor of the Σ-Δ analog-to-digital converter during the sampling phase, which ultimately leads to the measurement error of the battery power.

[0044] To this end, the present application provides an analog-to-digital conversion circuit, a chip, and an electronic device, which are described in detail below.

[0045] First, see Figure 3 , Figure 3 A schematic diagram of an analog-to-digital conversion circuit in an embodiment of the present application is shown, wherein the analog-to-digital conversion circuit includes:

[0046] A first analog-to-digital conversion module 10, the first analog-to-digital conversion module 10 comprises an adjustable sampling capacitor Cs, the adjustable sampling capacitor Cs is connected to the module to be measured 1 to sample the voltage to be measured Vin output by the module to be measured 1;

[0047] A capacitance control module 20, wherein the input end of the capacitance control module 20 is connected to the module to be measured 1, and the output end of the capacitance control module 20 is connected to the adjustable sampling capacitor Cs;

[0048] When the voltage to be measured Vin is in any set voltage interval, the capacitance control module 20 corrects the capacitance value of the adjustable sampling capacitor Cs to a standard set threshold value based on the set voltage interval where the voltage to be measured Vin is located.

[0049] Specifically, the first analog-to-digital conversion module 10 is used to convert the voltage to be measured Vin output by the module to be measured 1 into a digital signal, so as to realize the voltage measurement of the module to be measured 1. Wherein, the module to be measured 1 refers to a module that can output the voltage to be measured Vin. For example, the module to be measured 1 can be a battery module of a new energy vehicle, a power tool, an electric vehicle, a drone, an industrial robot, a mobile phone, a notebook, or a wearable device; for another example, the module to be measured 1 can be an analog circuit (such as a temperature sensing circuit) that outputs an analog voltage signal, so as to measure the voltage signals of various analog circuits. In some embodiments of the present application, the voltage to be measured Vin can be a single-ended signal, that is, the voltage to be measured Vin refers to a voltage signal relative to the ground terminal. In some embodiments of the present application, the voltage to be measured Vin can be a differential voltage signal, that is, the voltage to be measured Vin includes two differential voltage signals.

[0050] The first analog-to-digital conversion module 10 includes an adjustable sampling capacitor Cs, and the adjustable sampling capacitor Cs is connected to the module to be measured 1 to sample the voltage Vin to be measured output by the module to be measured 1 through switch control. Exemplarily, the first analog-to-digital conversion module 10 may be a Δ-Σ analog-to-digital converter including the adjustable sampling capacitor Cs, or the first analog-to-digital conversion module 10 may be a hybrid analog-to-digital converter consisting of a Δ-Σ analog-to-digital converter including the adjustable sampling capacitor Cs and a successive approximation analog-to-digital converter.

[0051] In some embodiments of the present application, for example, for an embodiment in which the voltage Vin to be measured is a single-ended signal, the adjustable sampling capacitor Cs may refer to a capacitor set with a single adjustable capacitance value, for example, Figure 3 The first analog-to-digital conversion module 10 may include an adjustable sampling capacitor Cs, a switch s1, a switch s2, a switch s3 and a switch s4. In the sampling phase of the first analog-to-digital conversion module 10, when switches s1 and s4 are closed and switches s2 and s3 are disconnected, the voltage to be measured Vin charges the adjustable sampling capacitor Cs, and the amount of charge charged is: Vin*Cs; in the integration phase of the first analog-to-digital conversion module 10, when switches s1 and s4 are disconnected and switches s2 and s3 are closed, the amount of charge of the sampled charge signal output by the adjustable sampling capacitor Cs is: -Vin*Cs, so that the integrator of the first analog-to-digital conversion module 10 receives the sampled charge signal and integrates it.

[0052] In some embodiments of the present application, for example, for an embodiment in which the voltage to be measured Vin is a differential voltage signal, the adjustable sampling capacitor Cs may refer to a plurality of capacitors with adjustable capacitance values, for example, Figure 4 , Figure 4Another schematic diagram of the analog-to-digital conversion circuit in the embodiment of the present application is shown, wherein the first analog-to-digital conversion module 10 may include a first adjustable sampling capacitor Cs1, a second adjustable sampling capacitor Cs2, and switches S01 to S08. In the sampling phase of the first analog-to-digital conversion module 10, when switches S01, S03, S05, and S07 are closed, and switches S02, S04, S06, and S08 are opened, the amount of charge accumulated in the first adjustable sampling capacitor Cs1 is (Vp-VCM)*C, and the amount of charge accumulated in the second adjustable sampling capacitor Cs2 is (Vn-VCM)*C.

[0053] On the contrary, in the integration stage of the first analog-to-digital conversion module 10, when the switches S01, S03, S05 and S07 are opened and the switches S02, S04, S06 and S08 are closed, the charge accumulated in the first adjustable sampling capacitor Cs1 is (Vn-VCM)*C, and the charge accumulated in the second adjustable sampling capacitor Cs2 is (Vp-VCM)*C.

[0054] Therefore, in the above switch switching process, the amount of charge released by the first adjustable sampling capacitor Cs1 and the amount of charge released by the second adjustable sampling capacitor Cs2 are:

[0055] Qin1=(Vp-VCM)*C-(Vn-VCM)*C=(Vp-Vn)*C=Vin*C

[0056] Qin2=(Vn-VCM)*C-(Vp-VCM)*C=(Vn-Vp)*C=-Vin*C

[0057] Therefore, by switching the above switches, the purpose of the adjustable sampling capacitor Cs outputting the corresponding sampling charge signal can be finally achieved.

[0058] The capacitance control module 20 can correct the capacitance value of the adjustable sampling capacitor Cs to the standard setting threshold value according to the set voltage interval of the voltage Vin to be measured. For example, when the voltage of the voltage Vin to be measured is 80V, the actual capacitance value of the adjustable sampling capacitor Cs before correction may be 1.003pF, and the capacitance control module 20 can correct the capacitance value of the adjustable sampling capacitor Cs to within the standard setting threshold value of 1pF±0.0005pF; for another example, when the voltage of the battery is 70V, the actual capacitance value of the sampling capacitor may be 1.002pF, and the capacitance control module 20 can correct the capacitance value of the adjustable sampling capacitor Cs to within the standard setting threshold value of 1pF±0.0005pF, thereby ensuring that the capacitance value of the adjustable sampling capacitor Cs does not change with the magnitude of the voltage Vin to be measured and is always within the standard setting threshold value.

[0059] In some embodiments of the present application, the adjustable sampling capacitor Cs may include multiple capacitors connected in parallel and / or in series, and the capacitance control module 20 controls the capacitance value of the adjustable sampling capacitor Cs by controlling the number of capacitors connected in parallel and / or in series. Figure 5 , Figure 5 A schematic diagram of an adjustable sampling capacitor Cs in an embodiment of the present application is shown, wherein the adjustable sampling capacitor Cs includes a first main capacitor Csx, a plurality of first sub-capacitors Csy and a first parallel switch Sp; the first sub-capacitor Csy corresponds to the first parallel switch Sp one by one, the first plate of the first sub-capacitor Csy is connected to the first plate of the first main capacitor Csx; the second plate of the first sub-capacitor Csy is connected to the first end of the first parallel switch Sp, the second end of the first parallel switch Sp is connected to the second plate of the first main capacitor Csx, and the control end of the first parallel switch Sp is connected to the output end of the capacitance control module 20. When the capacitance control module 20 controls a closed first parallel switch Sp to be opened again, the number of first sub-capacitors Csy connected in parallel with the first main capacitor Csx is reduced by one, thereby reducing the capacitance value of the adjustable sampling capacitor Cs; and when the capacitance control module 20 controls a disconnected first parallel switch Sp to be closed again, the number of first sub-capacitors Csy connected in parallel with the first main capacitor Csx is increased by one, thereby increasing the capacitance value of the adjustable sampling capacitor Cs.

[0060] For example, see Figure 6 , Figure 6 Another schematic diagram of the adjustable sampling capacitor Cs in the embodiment of the present application is shown. The adjustable sampling capacitor Cs includes a first main capacitor Csx, a plurality of first series capacitors Ca, a switch Sa and a switch Sb for controlling whether the series capacitors are connected in series with the first main capacitor Csx. The capacitor control module 20 controls the switch Sa and the switch Sb to control the number of first series capacitors Ca connected in series with the first main capacitor Csx, thereby changing the capacitance value of the adjustable sampling capacitor Cs. For another example, see Figure 7 , Figure 7 Another schematic diagram of the adjustable sampling capacitor Cs in an embodiment of the present application is shown. The adjustable sampling capacitor Cs includes a first main capacitor Csx, a first sub-capacitor Csy connected in parallel with the first main capacitor Csx, a first series capacitor connected in series with the first main capacitor Csx, and corresponding first parallel switches Sp, Sa, and Sb. The capacitance control module 20 controls the first parallel switch Sp, Sa, and Sb to control the number of parallel connections of the first main capacitor Csx, the first series capacitor Ca, and the first sub-capacitor Csy, thereby changing the capacitance value of the adjustable sampling capacitor Cs.

[0061] In some embodiments of the present application, the capacitance control module 20 may include a digital circuit to determine the voltage interval of the voltage to be measured Vin and control the capacitance value of the adjustable sampling capacitor Cs by means of a digital circuit. For example, the capacitance control module 20 may include a numerical comparator for determining the binary digital signal corresponding to the voltage to be measured Vin to determine the voltage interval of the voltage to be measured Vin. In some embodiments of the present application, the capacitance control module 20 may include an analog circuit to determine the voltage interval of the voltage to be measured Vin and control the capacitance value of the adjustable sampling capacitor Cs by means of an analog circuit. For example, the capacitance control module 20 may include a threshold comparator for determining the voltage to be measured Vin to determine the voltage interval of the voltage to be measured Vin.

[0062] As an example, see Figure 8 , Figure 8 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown, wherein the capacitance control module 20 includes multiple comparators COMP and multiple XOR gates XOR1, XOR2...XOR7, the non-inverting input terminals of the multiple comparators COMP1, COMP2...COMP8 are connected to 10V, 20V...80V reference voltages in sequence, the inverting input terminal of each comparator COMP is connected to the voltage Vin signal to be measured, and the first input terminal and the second input terminal of each XOR gate XOR are connected to the output terminals of two adjacent comparators. For example, when the voltage Vin to be measured is 15V, the comparator COMP1 with a 10V voltage connected to its in-phase input terminal outputs a low-level signal, and the other comparators COMP all output high-level signals. Therefore, the XOR gate XOR1 connected to the output terminals of comparators COMP1 and COMP2 outputs a high-level signal, while the other XOR gates XOR1 output low-level signals. Therefore, the capacitance control module 20 can use the XOR gate XOR1 to output a high-level signal to control the number of parallel and / or series capacitors in the adjustable sampling capacitor Cs, and finally correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold.

[0063] For example, Figure 5For example, the capacitance value of the first main capacitor Csx is 0.995pF, and the capacitance value of the parallel first sub-capacitor Csy is 0.001pF. Ideally, the first main capacitor Csx can reach the standard capacitance value of 1pF by connecting five first sub-capacitors Csy in parallel. However, since the voltage value of the voltage to be measured is 80V, the actual total capacitance value of the first main capacitor Csx and the five first sub-capacitors Csy is 1.003pF. At this time, the high-level signal output by the XOR gate XOR1 can control only two of the multiple first parallel switches Sp (such as NMOS tubes) to close. For other first parallel switches Sp, the XOR gate XOR1 outputs a low-level signal to the control end of the other first parallel switches Sp through an inverter, so that the other first parallel switches Sp are in a disconnected state. Therefore, the capacitance value of the adjustable sampling capacitor Cs can be corrected to the standard set threshold value in the end.

[0064] In the embodiment of the present application, the present application connects the input end of the capacitance control module 20 to the module to be measured 1, and connects the output end of the capacitance control module 20 to the adjustable sampling capacitor Cs. When the voltage Vin to be measured is in any set voltage interval, the capacitance control module 20 can correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold value according to the set voltage interval in which the voltage Vin to be measured is located. That is to say, no matter how the measurement voltage changes, the capacitance value of the adjustable sampling capacitor Cs can be guaranteed to be within the standard set threshold value, thereby avoiding the nonlinear problem of the adjustable sampling capacitor Cs of the first analog-to-digital conversion module 10, and ultimately ensuring high-precision measurement of the battery power.

[0065] In some embodiments of the present application, for example, for an embodiment in which the capacitance control module 20 includes a digital circuit, continue to refer to Fig. 9 , Fig. 9 Another schematic diagram of the analog-to-digital conversion circuit in the embodiment of the present application is shown, wherein the capacitance control module 20 includes a second analog-to-digital conversion module 21 and a numerical comparison module 22, the input end of the second analog-to-digital conversion module 21 is connected to the module to be measured 1; the input end of the numerical comparison module 22 is connected to the output end of the second analog-to-digital conversion module 21 to receive a digital signal corresponding to the voltage to be measured Vin and determine the set voltage interval in which the voltage to be measured Vin is located, and the output end of the numerical comparison module 22 is connected to the adjustable sampling capacitor Cs to correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold. Exemplarily, the second analog-to-digital conversion module 21 may include at least one of a successive approximation analog-to-digital converter, a Flash ADC, or a Piepline ADC.

[0066] It should be noted that the numerical comparison module 22 in the present application refers to a digital circuit composed of gate circuits, registers, triggers, latches, etc. After the second analog-to-digital conversion module 21 converts the voltage to be measured Vin into a digital signal, the numerical comparison module 22 determines the set voltage range of the voltage to be measured Vin according to the digital signal, and controls the capacitance value of the adjustable sampling capacitor Cs by outputting high and low level signals. For example, the magnitude of the voltage Vin to be measured is 65V, and the digital signal output by the second analog-to-digital conversion module 21 corresponds to 01000001, that is, the second analog-to-digital conversion module 21 outputs a binary digital signal, and the number of bits of the digital signal is 8. The numerical comparison module 22 is connected to the binary digital signals corresponding to 10V (digital signal is 00001010), 20V (digital signal is 00010010), 30V (digital signal is 00011110), 40V (digital signal is 00101000), 50V (digital signal is 00110010), 60V (digital signal is 00111100), 70V (digital signal is 01000110), and 80V (digital signal is 01010000). The numerical comparison module 22 can determine that the voltage Vin to be measured is between 60V and 70V, and finally correct the capacitance value of the adjustable sampling capacitor Cs to be within the standard set threshold.

[0067] As an example, see Fig.10 , Fig.10 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown, wherein the numerical comparison module 22 includes multiple numerical comparators 221; the first input end of each numerical comparator 221 is connected to the output end of the second analog-to-digital conversion module 21, and the second input end of each numerical comparator 221 is connected to a preset digital signal, the preset digital signal corresponds to a preset voltage, and any two preset voltages correspond to a set voltage range.

[0068] For example, there are eight numerical comparators 221, and the second input terminals of the eight numerical comparators 221 are connected to binary digital signals corresponding to 10V (digital signal is 00001010), 20V (digital signal is 00010010), 30V (digital signal is 00011110), 40V (digital signal is 00101000), 50V (digital signal is 00110010), 60V (digital signal is 00111100), 70V (digital signal is 01000110), and 80V (digital signal is 01010000). Then, the two numerical comparators 221 connected to the 10V and 20V digital signals can determine whether the voltage Vin to be measured is between 10V and 20V, and the two numerical comparators 221 connected to the 20V and 30V digital signals can determine whether the voltage Vin to be measured is between 20V and 30V, and so on. Each interval of 10V is taken as a set voltage interval. Finally, the numerical comparison module 22 can determine in which set voltage interval the voltage Vin to be measured is located, and finally correct the capacitance value of the adjustable sampling capacitor Cs through the electrical signal output by the gate circuit (such as an XOR gate) to be within the standard set threshold.

[0069] It can be understood that the above embodiment uses the set voltage interval defined every 10V as an exemplary embodiment only. In fact, a set voltage interval can also be defined every 5V or 3V. The smaller the voltage interval is divided into, the more accurately the capacitance value of the adjustable sampling capacitor Cs can be corrected. However, the corresponding circuit structure is more complex, for example, there are more numerical comparators 221 in the above embodiment. Therefore, those skilled in the art can define the set voltage interval according to actual needs, and this application does not make specific limitations.

[0070] In some embodiments of the present application, see Fig.11 , Fig.11 Another schematic diagram of the analog-to-digital conversion circuit in the implementation of the present application is shown, wherein the capacitance control module 20 further includes a step-down module 23; the input end of the step-down module 23 is connected to the module to be measured 1, and the output end of the step-down module 23 is connected to the input end of the second analog-to-digital conversion module 21 to provide the actual measured voltage after the voltage Vin to be measured is stepped down to the second analog-to-digital conversion module 21. In other words, the second analog-to-digital conversion module 21 measures the actual measured voltage after the step-down, and after measuring the voltage value of the actual measured voltage, reversely calculates the voltage value of the voltage Vin to be measured, thereby avoiding the high-voltage design requirement of the second analog-to-digital conversion module 21 in the high-voltage measurement scenario.

[0071] As an example, see Fig.12 , Fig.12Another schematic diagram of the analog-to-digital conversion circuit in the embodiment of the present application is shown, the buck module 23 may include multiple transistors connected in series, the drain and gate of the transistor are short-circuited so as to be used as a resistor, and the input end of the second analog-to-digital conversion module 21 may be connected to the drain of the transistor close to the ground terminal. For example, if it is assumed that each transistor has the same size and the number of multiple transistors is six, the actual measured voltage is one-sixth of the voltage to be measured, so that the second analog-to-digital conversion module 21 measures the actual measured voltage with a lower voltage. It can be understood that the implementation of the buck module 23 is not limited to this. For example, the buck module 23 may also be composed of a diode and / or a resistor.

[0072] In some other embodiments of the present application, see Fig.13 , Fig.13 Another schematic diagram of the analog-to-digital conversion circuit in the embodiment of the present application is shown, wherein the capacitance control module 20 includes a numerical comparison module 22; the input end of the numerical comparison module 22 is connected to the output end of the first analog-to-digital conversion module 10 to receive a digital signal corresponding to the voltage to be measured Vin and determine the set voltage interval in which the voltage to be measured Vin is located, and the output end of the numerical comparison module 22 is connected to the adjustable sampling capacitor Cs to correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold value. In other words, the first analog-to-digital conversion module 10 in which the adjustable sampling capacitor Cs is not calibrated can also be used to output a digital signal corresponding to the voltage to be measured Vin, and then the numerical comparison module 22 is used to determine the set voltage interval corresponding to the voltage to be measured Vin, and finally the capacitance value of the adjustable sampling capacitor Cs is calibrated according to the set voltage interval in which the voltage to be measured Vin is located, so that the second analog-to-digital conversion module 21 can be omitted and it is conducive to simplifying the circuit structure of the analog-to-digital conversion circuit.

[0073] In some embodiments of the present application, for example, for an embodiment in which the capacitance control module 20 includes an analog circuit, see Fig.14 , Fig.14 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown, wherein the capacitance control module 20 includes multiple threshold comparator units 201, each threshold comparator unit 201 corresponds to a set voltage interval, and the input end of each threshold comparator unit 201 is connected to the module to be measured 1 to determine whether the voltage Vin to be measured is within the corresponding set voltage interval and correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold.

[0074] For example, the threshold comparator unit 201 connected to the analog voltage of 10V and 20V can determine whether the voltage to be measured Vin is between 10V and 20V. When the voltage to be measured Vin is between 10V and 20V, the threshold comparator can output an electrical signal and correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold. For another example, the threshold comparator unit 201 connected to 20V and 30V can determine whether the voltage to be measured Vin is between 20V and 30V. When the voltage to be measured Vin is between 20V and 30V, the threshold comparator can output an electrical signal and correct the capacitance value of the adjustable sampling capacitor Cs to the standard set threshold, and so on, so that the capacitance control module 20 can finally determine the set voltage interval of the voltage to be measured Vin and correct its capacitance value.

[0075] As an example, see Fig.15 , Fig.15 Another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application is shown, wherein each threshold comparator unit 201 includes a first comparator COMPa, a second comparator COMPb and a first XOR gate XORa; the non-inverting input terminal of the first comparator COMPa is connected to a first reference voltage (e.g., 10V), and the inverting input terminal of the second comparator COMPb is connected to a second reference voltage (e.g., 20V), the first reference voltage corresponds to an upper limit value of a set voltage interval, and the second reference voltage corresponds to a lower limit value of a set voltage interval; the inverting input terminal of the first comparator COMPa and the non-inverting input terminal of the second comparator COMPb are connected to the module to be measured 1, the output terminal of the first comparator COMPa is connected to the first input terminal of the first XOR gate XORa, the output terminal of the second comparator COMPb is connected to the second input terminal of the first XOR gate XORa, and the output terminal of the first XOR gate XORa is connected to the adjustable sampling capacitor Cs.

[0076] For example, when the voltage Vin to be measured is 25V, for the threshold comparator unit 201 connected to the 20V reference voltage and the 30V reference voltage, the first comparator COMPa and the second comparator COMPb of the threshold comparator unit 201 both output low-level signals, so the first XOR gate XORa of the threshold comparator unit 201 also outputs a low-level signal; and for other threshold comparator units 201, one of the first comparator COMPa and the second comparator COMPb of other threshold comparator units 201 outputs a high-level signal, and the other outputs a low-level signal, so the first XOR gate XORa of other threshold comparator units 201 outputs a high-level signal, so it can be determined through which first XOR gate XORa outputs a low-level signal, in which set voltage range the voltage Vin to be measured is located, and at the same time, the capacitance value of the adjustable sampling capacitor Cs is corrected to the standard set threshold through the low-level signal output by the first XOR gate XORa.

[0077] The embodiment of the present application also provides a chip, which includes the above-mentioned analog-to-digital conversion circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip, chip-level system) chip or a SIP (system in package, system-level packaging) chip. Since the chip in the embodiment of the present application is provided with the analog-to-digital conversion circuit of the above-mentioned embodiment, it has all the beneficial effects of the above-mentioned analog-to-digital conversion circuit, which will not be repeated here.

[0078] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car console, a car, a smart wearable device, a mobile terminal, a smart home device, a power tool, a drone, and an industrial robot. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0079] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that: include: A first analog-to-digital conversion module, wherein the first analog-to-digital conversion module comprises an adjustable sampling capacitor, wherein the adjustable sampling capacitor is connected to the module to be measured to sample the voltage to be measured output by the module to be measured; A capacitance control module, wherein an input end of the capacitance control module is connected to the module to be measured, and an output end of the capacitance control module is connected to the adjustable sampling capacitor; When the voltage to be measured is in any set voltage interval, the capacitance control module corrects the capacitance value of the adjustable sampling capacitor to a standard set threshold value based on the set voltage interval in which the voltage to be measured is located.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The capacitance control module includes a second analog-to-digital conversion module and a numerical comparison module, and the input end of the second analog-to-digital conversion module is connected to the module to be measured; The input end of the numerical comparison module is connected to the output end of the second analog-to-digital conversion module to receive a digital signal corresponding to the voltage to be measured and determine the set voltage interval in which the voltage to be measured is located. The output end of the numerical comparison module is connected to the adjustable sampling capacitor to correct the capacitance value of the adjustable sampling capacitor to a standard set threshold value.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The numerical comparison module includes a plurality of numerical comparators; The first input terminal of each numerical comparator is connected to the output terminal of the second analog-to-digital conversion module, and the second input terminal of each numerical comparator is connected to a preset digital signal, the preset digital signal corresponds to a preset voltage, and any two preset voltages correspond to a set voltage range.

4. The analog-to-digital conversion circuit according to claim 2, characterized in that: The capacitance control module also includes a voltage reduction module; The input end of the step-down module is connected to the module to be measured, and the output end of the step-down module is connected to the input end of the second analog-to-digital conversion module to provide the second analog-to-digital conversion module with an actual measurement voltage after the voltage to be measured is stepped down.

5. The analog-to-digital conversion circuit according to claim 1, characterized in that: The capacitance control module includes a numerical comparison module; The input end of the numerical comparison module is connected to the output end of the first analog-to-digital conversion module to receive a digital signal corresponding to the voltage to be measured and determine the set voltage interval in which the voltage to be measured is located. The output end of the numerical comparison module is connected to the adjustable sampling capacitor to correct the capacitance value of the adjustable sampling capacitor to a standard set threshold value.

6. The analog-to-digital conversion circuit according to claim 1, characterized in that: The capacitance control module includes a plurality of threshold comparator units; Each of the threshold comparator units corresponds to a set voltage interval, and an input end of each of the threshold comparator units is connected to the module to be measured to determine whether the voltage to be measured is within the corresponding set voltage interval and to correct the capacitance value of the adjustable sampling capacitor to a standard set threshold.

7. The analog-to-digital conversion circuit according to claim 6, characterized in that: Each of the threshold comparator units includes a first comparator, a second comparator and a first XOR gate; A first reference voltage is connected to the non-inverting input terminal of the first comparator, and a second reference voltage is connected to the inverting input terminal of the second comparator. The first reference voltage corresponds to an upper limit value of the set voltage range, and the second reference voltage corresponds to a lower limit value of the set voltage range. The inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator are connected to the module to be measured, the output terminal of the first comparator is connected to the first input terminal of the first XOR gate, the output terminal of the second comparator is connected to the second input terminal of the first XOR gate, and the output terminal of the first XOR gate is connected to the adjustable sampling capacitor.

8. The analog-to-digital conversion circuit according to any one of claims 1 to 7, characterized in that: The adjustable sampling capacitor includes a first main capacitor, a plurality of first sub-capacitors and a first parallel switch; The first sub-capacitors correspond to the first parallel switches one by one, and the first plates of the first sub-capacitors are connected to the first plates of the first main capacitors; The second electrode plate of the first sub-capacitor is connected to the first end of the first parallel switch, the second end of the first parallel switch is connected to the second electrode plate of the first main capacitor, and the control end of the first parallel switch is connected to the output end of the capacitor control module.

9. A chip, characterized in that: The analog-to-digital conversion circuit comprises the analog-to-digital conversion circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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