Circuit board for thermal imager

Abstract

The utility model provides a circuit board for a thermal imager. The circuit board comprises a connector, a driving circuit, a development board, a clock module and a communication network board. The connector is connected with the output interface of the detector and the input interface of the development board; the driving circuit is used for being connected with an external power supply and providing working levels for the detector and the connector assembly respectively; an output interface of the development board is connected with an external memory and a display device. The clock module is connected with the connector and the development board so as to provide a reference clock signal for data transmission between the development board and the connector; and the communication network board is used for providing a stable channel for data exchange between the upper computer and the development board. According to the utility model, the frame structure of the whole circuit is changed, the connector is used as a data format converter for data exchange between the development board and the detector, and the function of data format conversion of an FPGA (Field Programmable Gate Array) in a common frame is replaced, so that the display rate of an infrared image in an upper computer is accelerated.

Description

Technical Field

[0001] The utility model belongs to the technical field of thermal imaging, and in particular relates to a circuit board used for a thermal imager. Background Art

[0002] FPGA (Programmable Array Logic) + DSP (Digital Signal Processor) dual-core processing architecture is a common way for domestic research units to realize uncooled infrared imaging systems. The FPGA is connected to the DSP through the EM+F interface, and the FPGA is used as an interface device for some logic designs such as driving timing control of the infrared detector and converting the collected data into a form that meets the requirements of the DSP. DSP focuses on image algorithm processing and data communication in infrared imaging systems, such as blind pixel detection and compensation, non-uniformity correction, image pseudo-color coloring, etc. The advantage of using FPGA+DSP dual-core processing architecture is that the system has higher stability and can process more complex image processing algorithms, thereby obtaining high-quality imaging effects. However, this architecture uses two main chips, resulting in low data transmission efficiency and serious lag in image resolution speed. Utility Model Content

[0003] In order to solve the problem that the existing framework described in the background technology uses two main chips, resulting in low data transmission efficiency and serious image analysis speed lag, the utility model proposes the following technical solutions:

[0004] A circuit board for a thermal imager comprises: a connector, a drive circuit, a development board, a clock module and a communication network board; the connector is connected to an output interface of a detector and an input interface of the development board; the drive circuit is used to connect a power supply and provide working levels to the detector and the connector respectively; the output interface of the development board is connected to an external memory and a display device respectively; the clock module is connected to the connector and the development board, thereby providing a reference clock signal for data transmission between the development board and the connector; the communication network board is used to provide a stable channel for data exchange between the host computer and the development board.

[0005] Among them, the development board includes: a central processing unit, an FPGA and a level conversion module; the interactive port of the central processing unit is connected to the FPGA, and the network interface of the central processing unit is connected to the host computer through the communication network board; the input interface of the FPGA is connected to the output port of the connector through the level conversion module, the clock end of the FPGA is connected to the clock module, and the data interface of the FPGA is connected to the external memory; the level conversion module is used to adjust the level conversion standard between the connector and the FPGA.

[0006] Furthermore, the connector includes: a receiving chip, a transmitting chip and an adapter; the input end of the receiving chip is connected to the first signal end of the adapter, and the output end of the receiving chip is connected to the FPGA; the input end of the transmitting chip is connected to the FPGA, and the output end of the transmitting chip is connected to the second signal end of the adapter; the third signal end of the adapter is connected to the detector, and the adapter is used to perform data format conversion to complete the data transmission between the detector and the FPGA.

[0007] Furthermore, the receiving end of the transmitting chip includes a first data interface with twenty-eight channels, and the output end of the receiving chip includes a second data interface with twenty-eight channels.

[0008] Furthermore, the first signal end and the second signal end are respectively provided with eight data channels. When data is exchanged between the FPGA and the detector, each of the data channels in the first signal end or each of the data channels in the second signal end outputs a differential level signal.

[0009] Furthermore, the driving circuit includes: a voltage divider chip and a step-down chip; the input end of the voltage divider chip is connected to the power supply, and the output end of the voltage divider chip is respectively connected to the detector and the connector; the step-down chip is connected to one of the output ports of the voltage divider chip.

[0010] Beneficial effect: The utility model changes the overall framework structure of the circuit and uses the connector as a data format converter for data exchange between the development board and the detector, thereby replacing the function of the FPGA in the common framework for data format conversion, thereby speeding up the display rate of the infrared image in the host computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a frame structure diagram of a circuit board for a thermal imager according to an embodiment of the utility model;

[0012] Figure 2 is a schematic structural diagram of a receiving chip according to an embodiment of the utility model;

[0013] Figure 3 It is a structural schematic diagram of a sending chip according to an embodiment of the utility model;

[0014] Figure 4 is a schematic structural diagram of an adapter according to an embodiment of the utility model;

[0015] Figure 5 Schematic diagram of the driving circuit structure according to an embodiment of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present application clearer, the present invention will be described in further detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] It should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing this patent and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this patent.

[0018] Figure 1 The figure is a frame structure diagram of a circuit board for a thermal imager according to an embodiment of the utility model.

[0019] Reference Figure 1 According to an embodiment of the utility model, a circuit board for a thermal imager includes: a connector 1, a driving circuit 2, a development board 3, a clock module 4 and a communication network board 5. The connector 1 connects the output interface of the detector 6 and the input interface of the development board 3. The driving circuit 2 is used to connect the power supply 7 and provide working levels to the detector 6 and the connector 1 respectively. The output interface of the development board 3 is respectively connected to the external memory 8 and the display device 9. The clock module 4 connects the connector 1 and the development board 3, thereby providing a reference clock signal for data transmission between the development board 3 and the connector 1. The communication network board 5 is used to provide a stable channel for data exchange between the host computer and the development board 3.

[0020] Among them, the development board 3 includes a central processing unit 31, an FPGA (programmable array logic) 32 and a level conversion module 33. The interactive port of the central processing unit 31 is connected to the FPGA 32, and the network interface of the central processing unit 31 is connected to the host computer through the communication network board 5. The input interface of the FPGA 32 is connected to the output port of the connector 1 through the level conversion module 33, and the data interface of the FPGA 32 is connected to the external memory 8. The clock end of the FPGA 32 is connected to the clock module 4, and the FPGA 32 uses the clock signal sent by the clock module 4 as the reference clock to complete the timing synchronization when receiving data. The level conversion module 33 is used to adjust the level conversion standard between the connector 11 and the FPGA 32, so as to meet the input signal requirements of different devices. For example: the signal output by the FPGA 32 may use a low level (such as 0V to 3.3V), while the input level of the detector 6 or other devices may require a high level (such as 0V to 5V). The level conversion module can adjust the input and output signals of the FPGA 32 to meet the level requirements of the receiving device.

[0021] When the operator issues an imaging command to the host computer through the human-computer interaction interface on the display device 9, the central processor 31 sends an image acquisition command to the detector 6 through the connector 1, and the detector 6 starts to run and transmits the collected raw data to the development board 3 through the connector 1. The built-in filter module and image data processing module of FPGA32 filter and reduce noise and optimize data balance on the raw data to form image data stored in the external memory 8. The central processor 31 sends the image data stored in the external memory 8 to the display device 9 through the communication network board 5, and the display device 9 analyzes the image data to generate an infrared video image.

[0022] Figure 2 Schematic diagram of the structure of a receiving chip according to an embodiment of the utility model. Figure 3 Schematic diagram of the structure of a sending chip according to an embodiment of the utility model. Figure 4 It is a schematic structural diagram of an adapter according to an embodiment of the utility model.

[0023] Refer to Figures 2 to 4 Specifically, the connector 1 includes: a receiving chip 11, a transmitting chip 12 and an adapter 13. In this embodiment, the receiving chip 11 and the transmitting chip 12 are both Cameralik transceiver chips. Among them, the input end of the receiving chip 11 is connected to the first signal end of the adapter 13, and the output end of the receiving chip 11 is connected to the FPGA 32. The input end of the transmitting chip 12 is connected to the FPGA 32, the output end of the transmitting chip 12 is connected to the second signal end of the adapter 13, and the third signal end of the adapter 13 is connected to the detector 6. The adapter 13 is used as a data format converter for data exchange between the FPGA 32 and the detector 6. The original data sent by the detector 6 is converted from 28 bits to 8 bits after passing through the adapter 13, and the acquisition instruction sent by the FPGA is converted from 8 bits to 28 bits.

[0024] Specifically, the receiving end of the receiving chip 11 includes a first data interface of 28 channels, and each channel transmits a data frame when transmitting data. The output end of the transmitting chip 12 includes a second data interface of 28 channels, and each data channel transmits a data frame when transmitting data. The first signal end and the second signal end of the adapter 13 are respectively provided with eight data channels, and each data channel transmits a differential level signal when transmitting data.

[0025] Figure 5 Schematic diagram of the driving circuit structure according to an embodiment of the utility model.

[0026] Reference Figure 5Specifically, the driving circuit 2 includes: a voltage divider chip 21 and a voltage step-down chip 22. The input end of the voltage divider chip 21 is connected to the power supply 7, and the output end of the voltage divider chip 21 is respectively connected to the detector 6, the receiving chip 11, the transmitting chip 12 and the adapter 13. Under the action of the voltage divider chip 21, the voltage of the power supply 7 is divided into 1.8V, 3.3V and 1.0V. One end of the voltage step-down chip 22 is connected to the detector 6, and the other end of the voltage step-down chip 22 is connected to the 1.8V output port of the voltage divider chip 21, thereby reducing the voltage of 1.8V to 1.5V again. Under the action of the driving circuit 2, the detector 6, the receiving chip 11, the transmitting chip 12 and the adapter 13 obtain a stable working voltage, thereby starting infrared imaging.

[0027] In summary, the utility model changes the overall framework structure of the circuit and uses the connector as a data format converter for data exchange between the development board and the detector, thereby replacing the function of the FPGA in the commonly used framework for data format conversion, thereby speeding up the display rate of the infrared image in the host computer.

[0028] The above description is of certain embodiments of the invention. Other embodiments are within the scope of the following claims.

[0029] The terms "exemplary," "example," and the like used throughout this specification mean "used as an example, instance, or illustration" and do not mean "preferred" or "advantageous" over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, these techniques can be implemented without these specific details. In some instances, in order to avoid obscuring the concepts of the described embodiments, well-known structures and devices are shown in block diagram form.

[0030] The optional implementation modes of the embodiments of the utility model are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the utility model are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the utility model, the technical scheme of the embodiments of the utility model can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the utility model.

[0031] The above description of the contents of this specification is provided to enable any person of ordinary skill in the art to implement or use the contents of this specification. Various modifications to the contents of this specification will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other variations without departing from the scope of protection of the contents of this specification. Therefore, the contents of this specification are not limited to the examples and designs described herein, but are consistent with the widest range of principles and novel features disclosed herein.

Claims

1. A circuit board for a thermal imager, characterized in that: include: A connector (1), a drive circuit (2), a development board (3), a clock module (4) and a communication network board (5); the connector (1) is connected to an output interface of a detector (6) and an input interface of the development board (3); the drive circuit (2) is used to connect to a power supply (7) and provide working levels to the detector (6) and the connector (1) respectively; the output interface of the development board (3) is connected to an external memory (8) and a display device (9) respectively; the clock module (4) is connected to the connector (1) and the development board (3), thereby providing a reference clock signal for data transmission between the development board (3) and the connector (1); the communication network board (5) is used to provide a stable channel for data exchange between a host computer and the development board (3).

2. A circuit board for a thermal imager according to claim 1, characterized in that: The development board (3) comprises: a central processing unit (31), an FPGA (32) and a level conversion module (33); the interactive port of the central processing unit (31) is connected to the FPGA (32), and the network interface of the central processing unit (31) is connected to the host computer through the communication network board (5); the input interface of the FPGA (32) is connected to the output port of the connector (1) through the level conversion module (33), the clock end of the FPGA (32) is connected to the clock module (4), and the data interface of the FPGA is connected to the external memory (8); the level conversion module (33) is used to adjust the level conversion standard between the connector (1) and the FPGA (32).

3. A circuit board for a thermal imager according to claim 2, characterized in that: The connector (1) comprises: a receiving chip (11), a transmitting chip (12) and an adapter (13); the input end of the receiving chip (11) is connected to the first signal end of the adapter (13), and the output end of the receiving chip (11) is connected to the FPGA (32); the input end of the transmitting chip (12) is connected to the FPGA (32), and the output end of the transmitting chip (12) is connected to the second signal end of the adapter (13); the third signal end of the adapter (13) is connected to the detector (6), and the adapter (13) is used to perform data format conversion to complete data transmission between the detector (6) and the FPGA (32).

4. A circuit board for a thermal imager according to claim 3, characterized in that: The receiving end of the transmitting chip (12) includes a first data interface with twenty-eight channels, and the output end of the receiving chip (11) includes a second data interface with twenty-eight channels.

5. A circuit board for a thermal imager according to claim 3, characterized in that: The first signal end and the second signal end are respectively provided with eight data channels, and when data is exchanged between the FPGA (32) and the detector (6), each of the data channels in the first signal end or each of the data channels in the second signal end outputs a differential level signal.

6. The circuit board for a thermal imager according to claim 1, characterized in that: The driving circuit (2) comprises: a voltage divider chip (21) and a voltage step-down chip (22); the input end of the voltage divider chip (21) is connected to the power supply (7), and the output end of the voltage divider chip (21) is respectively connected to the detector (6) and the connector (1); the voltage step-down chip (22) is connected to one of the output ports of the voltage divider chip (21).

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