Relaxation oscillator, clock generation circuit and electronic device
By adding a release circuit to the charging branch of the relaxation oscillator, the impact of the power supply voltage changes on the output clock frequency is solved, and higher clock signal accuracy and stability are achieved.
Patent Information
- Application Number
- CN202323419007.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-14
- Publication Date
- 2025-02-21
- Estimated Expiration
- 2033-12-14
AI Technical Summary
When the existing relaxation oscillator is actually operating, its output clock frequency will be affected by the change in the power supply voltage, resulting in the accuracy and stability of the clock signal being unable to meet the application requirements.
The release circuit is added in the charging branch of the relaxation oscillator, which is turned on before the first switching element is turned on and turned off after conduction to release the charge stored by the parasitic capacitor at the output node of the charging branch.
By releasing charge, the charge sharing phenomenon is avoided, thus making the charging process close to ideal, reducing the impact of power supply voltage changes on the output clock frequency, and improving the accuracy and stability of the clock signal.
Smart Images
Figure CN222515290U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of integrated circuits, and in particular to a relaxation oscillator, a clock generating circuit and an electronic device. Background Art
[0002] Clock generating circuit is an indispensable component of various electronic devices. There are many types of clock generating circuits according to different application scenarios. Among them, relaxation oscillator generally controls the periodic charging and discharging of the corresponding capacitor through the periodic switching of internal switching elements (such as transistors or MOS tubes, etc.), thereby outputting a periodic oscillating clock signal with a duty cycle of 50%. Relaxation oscillator has the advantages of low cost, low power consumption and simple structure, and has become a widely used solution for designing clock generating circuits in chips.
[0003] However, in the existing relaxation oscillator, due to the presence of parasitic capacitance in the internal switching element used to control the periodic charging and discharging of the capacitor, there is charge sharing at the moment when the switching element switches from off to on, which will raise the voltage of the capacitor from 0 to an initial voltage VL that linearly charges the capacitor, and the magnitude of the initial voltage VL will be affected by the change of the power supply voltage. Therefore, when the relaxation oscillator is actually working, its output clock frequency will be affected by the change of the power supply voltage, which may cause the accuracy and stability of the output clock signal to fail to meet the application requirements. Utility Model Content
[0004] The purpose of the utility model is to provide a relaxation oscillator, a clock generating circuit and an electronic device, which can greatly reduce the influence of power supply voltage changes on the output clock frequency of the relaxation oscillator during actual operation, thereby improving the accuracy and stability of the clock signal output by the relaxation oscillator.
[0005] To achieve the above object, the utility model provides a relaxation oscillator, which comprises:
[0006] A charge-discharge circuit, comprising at least one charging branch and a discharging branch arranged corresponding to the charging branch, wherein the charging branch comprises a first switch element and a capacitor, wherein an input end of the first switch element is coupled to a power supply voltage, an output end of the first switch element is coupled to one end of the capacitor, and the other end of the capacitor is grounded, and the first switch element is periodically switched on and off to control the capacitor to perform periodic charging, and the discharging branch comprises a second switch element, wherein an input end of the second switch element is coupled to one end of the corresponding capacitor, an output end of the second switch element is coupled to the ground, and the second switch element is periodically switched on and off to control the corresponding capacitor to perform periodic discharge;
[0007] a comparison circuit coupled to the output node of each of the charging branches and a corresponding reference voltage, and used to compare the voltage of the output node of each of the charging branches with the corresponding reference voltage;
[0008] a release circuit, comprising a release branch arranged corresponding to the charging branch, an input end of the release branch coupled to an input end of a first switch element of the corresponding charging branch, an output end of the release branch connected to ground, the release branch being turned on before the first switch element is turned on, and being turned off after the first switch element is turned on, so as to release the charge stored in the parasitic capacitor at the corresponding output node to ground;
[0009] A trigger circuit is coupled to the output end of the comparison circuit, the control end of the first switch element and the control end of the release circuit, and is used to control the on and off of the first switch element and the release circuit according to the output of the comparison circuit, and output a clock signal.
[0010] Optionally, the charging branch further includes a first current source, an input end of the first current source is coupled to a power supply voltage, an output end is coupled to an input end of the first switching element, and the first current source is used to charge the capacitor when the first switching element is turned on.
[0011] Optionally, the discharge branch further includes a second current source, an input end of the second current source is coupled to an output end of the second switch element, an output end of the second current source is grounded, and the second current source is used to extract charge from the capacitor when the second switch element is turned on.
[0012] Optionally, the release branch has a third switch element, an input end of the third switch element is coupled to the input end of the corresponding first switch element in the release branch, an output end of the third switch element is grounded, a control end of the third switch element is coupled to the trigger circuit, and the trigger circuit controls the on and off of the third switch element in reverse phase to the on and off of the first switch element.
[0013] Optionally, the relaxation oscillator further comprises a reference voltage generating circuit coupled to a corresponding input terminal of the comparison circuit to provide at least one reference voltage to the comparison circuit.
[0014] Optionally, the reference voltage generating circuit has at least one voltage generating branch, the voltage generating branch includes a third current source and at least one resistor connected in series, and the voltage generating branch has at least one voltage dividing node, and the voltage dividing node outputs a corresponding reference voltage.
[0015] Optionally, the charge and discharge circuit has a first charging branch and a second charging branch, the comparison circuit has a first comparator and a second comparator, the first input terminal of the first comparator is coupled to the output node of the first charging branch, the first input terminal of the second comparator is coupled to the output node of the second charging branch, and the second input terminal of the first comparator and the second input terminal of the second comparator are coupled to the same reference voltage, and the output terminal of the first comparator and the output terminal of the second comparator are respectively coupled to different input terminals of the trigger circuit.
[0016] Optionally, the charge and discharge circuit has a charging branch, and the comparison circuit has a first comparator and a second comparator, the first input terminal of the first comparator is coupled to a first reference voltage, the second input terminal of the first comparator and the first input terminal of the second comparator are both coupled to the output node of the charging branch, the second input terminal of the second comparator is coupled to a second reference voltage lower than the first reference voltage, and the output terminal of the first comparator and the output terminal of the second comparator are respectively coupled to different input terminals of the trigger circuit.
[0017] Optionally, the charge and discharge circuit has a charging branch, the comparison circuit has a comparator, the first input terminal of the comparator is coupled to the output node of the charging branch, the second input terminal of the comparator is coupled to the corresponding reference voltage, and the output terminal of the comparator is coupled to the corresponding input terminal of the trigger circuit.
[0018] Based on the same concept, the utility model also provides a clock generating circuit, which includes the relaxation oscillator as described in the utility model.
[0019] Based on the same concept, the present invention further provides an electronic device, which includes the clock generating circuit as described in the present invention.
[0020] Compared with the prior art, the technical solution of the utility model, based on the structure of a traditional relaxation oscillator, adds a release circuit connected to the ground in front of the input end of the first switch element in each charging branch thereof. When it is necessary to charge the capacitor in the corresponding charging branch, before the first switch element in the charging branch is turned on, the release circuit is turned on first to release the charge stored in the parasitic capacitor at the output node of the charging branch. As a result, at the moment when the first switch element in the charging branch is turned on, there is no charge sharing effect. Therefore, at this time, there is no initial voltage related to the power supply voltage. The entire charging process of the charging branch is close to ideal, thereby greatly reducing the influence of power supply changes on the output frequency of the relaxation oscillator, that is, an improved solution that makes the relaxation oscillator insensitive to changes in the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0022] Figure 1 The invention is a schematic diagram of the circuit structure of an existing relaxation oscillator.
[0023] Figure 2 yes Figure 1 The diagram is a schematic diagram of a charging curve of the capacitor C1 in the relaxation oscillator under different power supply voltages VDD.
[0024] Figure 3 It is a schematic diagram of the structure of a relaxation oscillator according to an embodiment of the present invention.
[0025] Figure 4 This is a schematic diagram of an exemplary circuit structure of a relaxation oscillator according to an embodiment of the utility model.
[0026] Figure 5 yes Figure 4 The diagram is a schematic diagram of a charging curve of the capacitor C1 in the relaxation oscillator under different power supply voltages VDD.
[0027] Figure 6 This is another exemplary circuit structure diagram of a relaxation oscillator according to an embodiment of the utility model. DETAILED DESCRIPTION
[0028] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the utility model. However, it is obvious to those skilled in the art that the utility model can be implemented without one or more of these details. In other examples, in order to avoid confusion with the utility model, some technical features known in the art are not described. It should be understood that the utility model can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the utility model will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0029] Combine the following Figure 1 The mechanism by which the output clock frequency of the conventional relaxation oscillator proposed in the background art is affected by the change of the power supply voltage is described in detail.
[0030] Please refer to Figure 1 , an existing relaxation oscillator circuit structure includes: current sources I1, I2, switch elements SW1, SW2, SW3, SW4, capacitors C1, C2, a comparison circuit COMP and a trigger circuit U0. Among them, the current source I1, the switch element SW1 and the capacitor C1 are connected in series to form a charging branch, the output node A of the charging branch is connected to the first input end of the comparison circuit COMP, the current source I2, the switch element SW2 and the capacitor C2 are connected in series to form another charging branch, the output node B of the charging branch is connected to the second input end of the comparison circuit COMP, the switch element SW3 is connected in parallel to both ends of the capacitor C1 and serves as a discharge branch of the capacitor C1, and can discharge the capacitor C1 under the output control of the trigger circuit U0, the switch element SW4 is connected in parallel to both ends of the capacitor C2 and serves as a discharge branch of the capacitor C2, and can discharge the capacitor C2 under the output control of the trigger circuit U0, the output end of the comparison circuit COMP is connected to the trigger circuit U0, and the reference end of the comparison circuit COMP receives the reference voltage Vref.
[0031] When the relaxation oscillator starts working, the trigger circuit U0 controls the switch elements SW1 and SW4 to be turned on, and the current source I1 charges the capacitor C1 (the size of the charging current is considered to be I1). When the voltage on the capacitor C1 (i.e., the voltage at the node A) is charged to Vref, the comparison circuit COMP flips. At this time, the trigger circuit U0 controls the switch elements SW1 and SW4 to be turned off, and SW2 and SW3 to be turned on, so as to release the charge on the capacitor C1 and start charging the capacitor C2 (the size of the charging current is considered to be I2), until the voltage on the capacitor C2 (i.e., the voltage at the node B) is charged to Vref, the comparison circuit COMP flips again, and the trigger circuit U0 controls the switch elements SW1 and SW4 to be turned on again, and SW2 and SW3 to be turned off, so as to release the charge on the capacitor C2 and start charging the capacitor C1 again. Thus, the trigger circuit U0 can control the switch elements SW1~SW4 to be turned on and off periodically according to the output of the comparison circuit COMP, and periodically charge and discharge the capacitors C1 and C2, and can also generate a clock signal with a periodic oscillation and a duty cycle of 50%.
[0032] Ideally, the charging time T1 of the charging process of capacitor C1 and the charging time T2 of the charging process of capacitor C2 can be expressed as:
[0033]
[0034] That is to say, ideally, the output clock frequency is determined by the size of the capacitor C1, the reference voltage Vref, and the charging currents I1 and I2 for charging the capacitors C1 and C2, and is less affected by changes in the power supply voltage VDD.
[0035] However, due to the existence of parasitic capacitance of the switch element, there is charge sharing at the moment when the switch element SW1 changes from off to on (i.e. closed), which will raise the voltage of the capacitor C1 from 0 to an initial voltage VL. Ignoring the short time of charge sharing, the charging time T1 of the charging process of the capacitor C1 and the charging time T2 of the charging process of the capacitor C2 can be approximately expressed as:
[0036]
[0037] If C1=C2, I1=I2, the output frequency F of the relaxation oscillator is:
[0038]
[0039] That is to say, in actual situations, the magnitude of the initial voltage VL of the linear charging of the two charging branches to the capacitors C1 and C2 will be affected by the change of the power supply voltage VDD. For example, please refer to Figure 2 As shown, when the power supply voltage VDD is equal to 2.6V, 3.0V and 3.6V respectively, the initial voltage VL is different.
[0040] Therefore, in actual operation, according to the formula for calculating F in the above text, in a relaxation oscillator with a traditional structure, the initial voltage VL changes with the power supply voltage VDD, which causes the output clock frequency F to change with the power supply voltage VDD.
[0041] In view of the above problems, the technical solution of the utility model proposes a new relaxation oscillator, which is an improved solution that can make the relaxation oscillator insensitive to changes in the power supply voltage VDD. On the basis of the structure of the traditional relaxation oscillator, a corresponding release branch is added in front of the input end of the first switch element in each charging branch, and the release branch is grounded, and the on-off switching of the release branch is opposite to the on-off switching of the switch element in the charging and discharging branch. Before the first switch element needs to be turned on to charge the capacitor in the charging branch, the release branch is turned on first to release the charge stored in the parasitic capacitance of the first switch element at the output node (i.e., the connection node between the capacitor and the first switch element) in the charging branch through the release branch. As a result, at the moment when the first switch element in the charging branch is turned on, there is no charge sharing effect. Therefore, there is no initial voltage VL related to the power supply voltage at this time. The entire charging process of the capacitor is close to ideal, and ultimately the output frequency of the relaxation oscillator is greatly reduced by the influence of power supply changes.
[0042] The technical solution proposed by the utility model is further described in detail below in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the utility model will be more clear. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0043] Please refer to Figure 3 An embodiment of the utility model provides a relaxation oscillator, which includes a reference voltage generating circuit 10, a charge and discharge circuit, a comparison circuit 13, a trigger circuit 14 and a release circuit 15.
[0044] Among them, the charging and discharging circuit has at least one charging branch 11 and a discharging branch 12 arranged corresponding to the charging branch 11, the charging branch 11 has a first switching element and a capacitor, the input end of the first switching element is coupled to the power supply voltage VDD, the output end of the first switching element is coupled to one end of the capacitor, and the other end of the capacitor is grounded, the first switching element is periodically turned on and off to control the capacitor to perform periodic charging, and the discharging branch 12 has a second switching element, the input end of the second switching element is coupled to one end of the corresponding capacitor, the output end of the second switching element is coupled to the ground, and the second switching element is periodically turned on and off to control the corresponding capacitor to perform periodic discharge.
[0045] The reference voltage generating circuit 10 is used to provide at least one reference voltage Vref. The comparison circuit 13 is coupled to the output node of each charging branch 11 and the corresponding reference voltage Vref, and is used to compare the voltage of the output node of each charging branch 11 with the corresponding reference voltage Vref.
[0046] The release circuit 15 has a release branch arranged corresponding to the charging branch 11, and the input end of the release branch is coupled to the input end of the first switch element of the charging branch 11, and the output end is grounded, so as to release the charge stored in the parasitic capacitance at the corresponding output node to the ground before the first switch element is turned on.
[0047] The trigger circuit 14 is coupled to the output end of the comparison circuit 13, the control end of the first switch element, the control end of the second switch element and the control end of the release branch, and is used to control the on-off of the first switch element, the on-off of the second switch element and the on-off of the release branch according to the output of the comparison circuit 13, and output a clock signal (not shown).
[0048] It should be understood that the reference voltage generating circuit 10 , the charging branch 11 , the discharging branch 12 , the comparison circuit 13 , the trigger circuit 14 and the release circuit 15 can be implemented by any appropriate circuit design.
[0049] For example, please combine Figure 3 and Figure 4 , any one or more charging branches 11i include a first current source I1i, a first switch element SW1i and a capacitor Ci, the input end of the first current source I1i is coupled to the power supply voltage VDD, the output end is coupled to the input end of the first switch element SW1i, and forms an output node of the charging branch 11i, the output end of the first switch element SW1i is coupled to one end of the capacitor Ci, and the other end of the capacitor Ci is grounded. The control end of the first switch element SW1i is coupled to the corresponding output end of the trigger circuit 14, and the first switch element SW1i is connected to the control signal of the trigger circuit 14. The first current source I1i is used to charge the capacitor Ci when the first switch element SW1i is turned on.
[0050] For another example, please combine Figure 3 and Figure 6 Any one or more discharge branches 12i include a second switch element SW2i and a second current source (such as Figure 6 The input end of the second switch element SW2i is coupled to the output node of the discharge branch 11i (i.e., one end of the capacitor Ci), the input end of the second current source is coupled to the output end of the second switch element SW2i in the discharge branch 12i, and the output end of the second current source is grounded. The control end of the second switch element SW2i is coupled to the corresponding output end of the trigger circuit 14. The second switch element SW2i is connected to the output node of the discharge branch 11i (i.e., one end of the capacitor Ci). The second current source is used to extract charge from the capacitor Ci when the second switch element SW2i is turned on.
[0051] For example, please combine Figure 3 and Figure 4 , any one or more release branches 15i have a third switch element SW3i, the input end of the third switch element SW3i is coupled to the input end of the corresponding first switch element SW1i in the charging branch 11i, the output end of the third switch element SW3i is grounded, the control end of the third switch element SW3i is coupled to the corresponding output end of the trigger circuit 14, and the trigger circuit 14 controls the on-off of the third switch element SW3i to be opposite to the on-off of the first switch element SW1i. Among them, the control signal received by the control end of the third switch element SW3i is marked as It can be connected with the control signal received by the discharge branch 12i same.
[0052] For example, the reference voltage generating circuit 10 has at least one voltage generating branch (not shown), which includes a third current source I0 and at least one resistor R connected in series, and has at least one voltage dividing node, which outputs a corresponding reference voltage.
[0053] For another example, the trigger circuit 14 includes a trigger, which may be an RS trigger or a D-type trigger, etc., the corresponding input end of the trigger is coupled to the corresponding output end of the comparison circuit 13, and the output end of the trigger outputs a corresponding control signal, etc. Alternatively, the trigger circuit 14 includes a trigger and an inverter (not shown), and the inverter is disposed at the front end or the back end of the trigger to output a corresponding control signal and a clock signal, etc.
[0054] Combine the following Figures 4 to 6 The circuit structure of the relaxation oscillator of this embodiment is described in detail with reference to the example shown.
[0055] Example 1
[0056] Please refer to Figure 4 The relaxation oscillator of this example includes a reference voltage generating circuit 10 , a charge and discharge circuit, a comparison circuit 13 , a trigger circuit 14 , and a release circuit 15 .
[0057] The charging and discharging circuit has a first charging branch 111 and a second charging branch 112. The first charging branch 111 includes a first current source I11, a first switch element SW11 and a capacitor C1. The input end of the first current source I11 is coupled to the power supply voltage VDD, and the output end is coupled to the input end of the first switch element SW11, and forms an output node A of the charging branch 111. The output end of the first switch element SW11 is coupled to one end of the capacitor C1, and the other end of the capacitor C1 is grounded. The control end of the first switch element SW11 is coupled to the corresponding output end of the trigger circuit 14. The first switch element SW11 outputs a periodic control signal when the trigger circuit 14 outputs the periodic control signal. The first current source I11 is periodically turned on and off under the control of the first switch element SW11. When the first switch element SW11 is turned on, the first current source I11 charges the capacitor C1. The second charging branch 112 includes the first current source I12, the first switch element SW12 and the capacitor C2. The input end of the first current source I12 is coupled to the power supply voltage VDD, and the output end is coupled to the input end of the first switch element SW12, and forms the output node B of the charging branch 112. The output end of the first switch element SW12 is coupled to one end of the capacitor C2, and the other end of the capacitor C2 is grounded. The control end of the first switch element SW12 is coupled to the corresponding output end of the trigger circuit 14. The first switch element SW12 is periodically controlled by the periodic control signal output by the trigger circuit 14. The first current source I12 is periodically turned on and off under the control of , and the first current source I12 charges the capacitor C2 when the first switch element SW12 is turned on.
[0058] The charge and discharge circuit also has a first discharge branch 121 and a second discharge branch 122. The first discharge branch 121 includes a second switch element SW21, which is connected in parallel to both ends of the capacitor C1, that is, the input end of the second switch element SW21 is coupled to the output node A, the output end of the second switch element SW21 is grounded, and the control end of the second switch element SW21 is coupled to the corresponding output end of the trigger circuit 14. The second discharge branch 122 includes a second switch element SW22, which is connected in parallel to both ends of the capacitor C2, that is, the input end of the second switch element SW22 is coupled to the output node B, the output end of the second switch element SW22 is grounded, and the control end of the second switch element SW21 and the control end of the second switch element SW22 are respectively coupled to different output ends of the trigger circuit 14. The second switch element SW21 is periodically controlled when the trigger circuit 14 outputs a control signal. The second switch element SW22 is periodically switched on and off under the control of the periodic control signal output by the trigger circuit 14. It switches on and off periodically under the control of.
[0059] It should be understood that when the first switch element SW11 and the second switch element SW21 are switches of the same type, for example, both are N-type transistors (such as NMOS transistors or NPN transistors, etc.) or both are P-type transistors (such as PMOS transistors or PNP transistors), the periodic control signal With periodic control signal Inverse; when the first switch element SW11 and the second switch element SW21 are switches of opposite types, for example, one is an N-type transistor (such as an NMOS tube or an NPN tube, etc.) and the other is a P-type transistor (such as a PMOS tube or a PNP tube), the periodic control signal With periodic control signal The same phase or the same periodic control signal ensures that the first switch element SW11 and the second switch element SW21 are not turned on at the same time.
[0060] Similarly, when the first switch element SW12 and the second switch element SW22 are switches of the same type, for example, both are N-type transistors (such as NMOS transistors or NPN transistors, etc.) or both are P-type transistors (such as PMOS transistors or PNP transistors), the periodic control signal With periodic control signal Inverse; when the first switch element SW12 and the second switch element SW22 are switches of opposite types, for example, one is an N-type transistor (such as an NMOS tube or an NPN tube, etc.) and the other is a P-type transistor (such as a PMOS tube or a PNP tube), the periodic control signal With periodic control signal The same phase, or the same periodic control signal, ensures that the first switch element SW12 and the second switch element SW22 are not turned on at the same time.
[0061] The release circuit has a first release branch 151 and a second release branch 152. The first release branch 151 is arranged corresponding to the first charging branch 111 and includes a third switch element SW31. The input end of the third switch element SW31 is coupled to the input end of the first switch element SW11. The output end of the third switch element SW31 is grounded. The control end of the third switch element SW31 is coupled to the corresponding output end of the trigger circuit 14 to receive the same control signal as the second switch element SW21. Therefore, in the periodic control signal Under the control of , the third switch element SW31 is synchronously switched on and off with the second switch element SW21. The input end of the third switch element SW32 is coupled to the input end of the first switch element SW12, the output end of the third switch element SW32 is grounded, the control end of the third switch element SW32 is coupled to the corresponding output end of the trigger circuit 14, and receives the same control signal as the second switch element SW22. Therefore, in the periodic control signal Under the control of , the third switch element SW32 is turned on and off synchronously with the second switch element SW22.
[0062] It should be understood that when the first switch element SW11 and the third switch element SW31 are switches of the same type, for example, both are N-type transistors (such as NMOS transistors or NPN transistors, etc.) or both are P-type transistors (such as PMOS transistors or PNP transistors), the periodic control signal With periodic control signal Inverse; when the first switch element SW11 and the third switch element SW31 are switches of opposite types, for example, one is an N-type transistor (such as an NMOS tube or an NPN tube, etc.) and the other is a P-type transistor (such as a PMOS tube or a PNP tube), the periodic control signal With periodic control signal The same phase, or the same periodic control signal, ensures that the first switch element SW11 and the third switch element SW31 are not turned on at the same time.
[0063] Similarly, when the first switch element SW12 and the third switch element SW32 are switches of the same type, for example, both are N-type transistors (such as NMOS transistors or NPN transistors, etc.) or both are P-type transistors (such as PMOS transistors or PNP transistors), the periodic control signal With periodic control signal Inverse; when the first switch element SW12 and the third switch element SW32 are switches of opposite types, for example, one is an N-type transistor (such as an NMOS tube or an NPN tube, etc.) and the other is a P-type transistor (such as a PMOS tube or a PNP tube), the periodic control signal With periodic control signal The same phase, or the same periodic control signal, ensures that the first switch element SW12 and the third switch element SW32 are not turned on at the same time.
[0064] The reference voltage generating circuit 10 comprises a third current source I0 and a resistor R. One end of the third current source I0 is coupled to the power supply voltage VDD, and the other end is coupled to one end of the resistor R, and outputs a constant reference voltage Vref. The other end of the resistor R is grounded.
[0065] The trigger circuit 14 includes an RS trigger, and the comparison circuit 13 has a first comparator COMP1 and a second comparator COMP2. The first input terminal (e.g., the positive input terminal "+") of the first comparator COMP1 is coupled to the output node A, the second input terminal (e.g., the negative input terminal "-") of the first comparator COMP1 is coupled to the reference voltage Vref, and the output terminal of the first comparator COMP1 is coupled to the S input terminal of the RS trigger. The first input terminal (e.g., the positive input terminal "+") of the second comparator COMP2 is coupled to the output node B, the first input terminal (e.g., the negative input terminal "-") of the second comparator COMP2 is coupled to the reference voltage Vref, and the output terminal of the second comparator COMP2 is coupled to the R input terminal of the RS trigger. The RS trigger Output terminal outputs periodic control signal Output terminal outputs periodic control signal
[0066] The working principle of the relaxation oscillator in this example is as follows:
[0067] When the operation starts, SW11, SW22, and SW32 are closed and turned on, and the current source I11 charges the capacitor C1 (i.e., the current source I11 charges the capacitor C1). When the voltage VA on the capacitor C1 is charged to Vref, the first comparator COMP1 flips, and the RS trigger controls SW11, SW22, and SW32 to be disconnected, and SW12, SW21, and SW31 are closed and turned on to discharge the capacitor C1 (i.e., release the charge on the capacitor C1). SW31 is turned on and grounded, and the charge stored in the parasitic capacitance of SW11 is also released to the ground. The current source I12 starts to charge the capacitor C2 (i.e., the current source I12 charges the capacitor C2), until the voltage on the capacitor C2 rises to Vref, and the second comparator COMP2 flips, and the RS trigger controls SW11, SW22, and SW32 to be closed and turned on again to charge the capacitor C1 again. SW32 is turned on and grounded, and the charge stored in the parasitic capacitance of SW12 is also released to the ground. In this cycle, a clock signal with a duty cycle of 50% can be achieved.
[0068] Also, please combine Figure 4 and Figure 5 As shown, in the above process of charging the capacitor C1, before SW11 is turned on, SW31 is in the on state, and the turned-on SW31 is grounded, which can release the charge stored in the parasitic capacitor at the output node A, so that at the moment when SW11 is turned from off to on (i.e. closed), there is no charge sharing phenomenon, so that the initial voltage (almost 0V) of the linear charging of the capacitor C1 is no longer affected by the change of the power supply voltage VDD, and the entire charging process of C1 is close to ideal. Similarly, in the process of charging the capacitor C2, before SW12 is turned on, SW32 is in the on state, and the turned-on SW32 is grounded, which can release the charge stored in the parasitic capacitor at the output node B, so that at the moment when SW12 is turned from off to on (i.e. closed), there is no charge sharing phenomenon, so that the size of the initial voltage VL of the linear charging of the capacitor C2 is no longer affected by the change of the power supply voltage VDD, and the entire charging process of C2 is close to ideal.
[0069] Therefore, the relaxation oscillator of this example can obtain a clock signal that is insensitive to changes in the power supply voltage VDD.
[0070] contrast Figure 1 and Figure 4As shown, it can be seen that the relaxation oscillator of this example actually only adds a grounded third switch element (i.e., SW31, SW32) before the input end of the first switch element (i.e., SW11, SW12) of each charging branch. The improvement cost is low and easy to implement. Before the corresponding charging branch charges the capacitor, the charge stored in the parasitic capacitance of its output node can be released, thereby avoiding the generation of charge sharing effect, thereby greatly reducing the influence of power supply voltage changes on its output clock frequency and improving the accuracy of its output clock signal.
[0071] Example 2
[0072] Please refer to Figure 6 , the relaxation oscillator in this example is Figure 4 Compared with the example shown, its charge and discharge circuit has only one charging branch 11 and one discharging branch 12, its release circuit 15 has only one release branch (not marked), and its reference voltage generating circuit has two voltage generating branches 10a and 10b. The voltage generating branch 10a outputs a higher reference voltage Vref_H, and the voltage generating branch 10b outputs a lower reference voltage Vref_L. The first input terminal of the first comparator COMP1 is coupled to the reference voltage Vref_H, the second input terminal of the second comparator COMP2 is coupled to the reference voltage Vref_L, and the second input terminal of the first comparator COMP1 and the first input terminal of the second comparator COMP2 are both coupled to the output node A.
[0073] It should be understood that the charging branch 11, the discharging branch 12, the release branch in the release circuit 15, and the two voltage generating branches 10a and 10b of this example can all adopt Figure 4 The corresponding circuit structure design in the example shown may also adopt any other suitable circuit design.
[0074] For example, the voltage generating branches 10a and 10b both use Figure 4 In the corresponding circuit structure design in the example shown, the third current source of the two is the same, but the resistance value of the resistor is different, so that the voltage generating branch 10a outputs a higher reference voltage Vref_H, and the voltage generating branch 10b outputs a lower reference voltage Vref_L. The charging branch 11 includes a first current source I1, a first switch element SW11 and a capacitor C1, and the release branch includes a third switch element SW31. The connection relationship between the first current source I1, the first switch element SW11 and the capacitor C1, and the third switch element SW31 can refer to the corresponding content description in the above example 1, and will not be repeated here.
[0075] For example, in Figure 4Based on the reference voltage generation circuit of the illustrated example, another resistor is connected in series between the resistor R and the ground, and the connection node of the third current source I0 and the resistor R serves as the output terminal of the voltage generation branch 10a to output a higher reference voltage Vref_H, and the connection node of the resistor R and the newly added another resistor serves as the output terminal of the voltage generation branch 10b to output a lower reference voltage Vref_L.
[0076] For another example, please refer to Figure 6 , the discharge branch 12 includes a second switching element SW21 and a second current source I21, and the input terminal of the second switching element SW21 is coupled to the output node A, the output terminal of the second switching element SW21 is coupled to one end of the second current source I21, and the other end of the second current source I21 is grounded.
[0077] The working principle of the relaxation oscillator in this example is as follows:
[0078] When power is first applied, the charge stored in the capacitor C1 is 0, VA < Vref_L, SW11 is closed and conducting, SW21 and SW31 are open, the second current source I21 does not work, and the first current source I11 starts to charge the capacitor C1. When the charge reaches VA > Vref_H, the first comparator COMP1 flips, and the RS flip-flop controls SW11 to open, SW21 and SW31 to close and conduct, the first current source I11 stops working, and the second current source I21 starts to extract the charge on the capacitor C1 to discharge the capacitor C1, VA gradually decreases, and the conducting and grounded SW31 also releases the charge stored in the parasitic capacitance of SW11 to the ground. When VA < Vref_L, the second comparator COMP2 flips, the RS flip-flop controls SW11 to close and conduct, SW21 and SW31 to open, the second current source I21 stops working, and the second current source I11 starts to charge the capacitor C1. In this way, by continuously charging and discharging the capacitor C, a clock signal with a duty cycle of 50% can be achieved.
[0079] Moreover, during the process of charging the capacitor C1 described above, before SW11 conducts, SW31 is in the conducting state, and the conducting SW31 is grounded, which can release the charge stored in the parasitic capacitance at the output node A. Thus, at the moment when SW11 changes from open to conducting (i.e., closed), there is no charge sharing phenomenon. Therefore, the initial voltage (almost 0V) of the linear charging of the capacitor C1 is no longer affected by the change of the power supply voltage VDD, and the entire charging process of C1 is close to ideal. Therefore, the relaxation oscillator in this example can also obtain a clock signal that is insensitive to the change of the power supply voltage VDD.
[0080] Based on the same concept, please refer to Figures 3 to 6An embodiment of the present invention further provides a clock generating circuit, which includes the relaxation oscillator as described in any embodiment of the present invention.
[0081] Based on the same idea, please refer to Figures 3 to 6 An embodiment of the present invention further provides an electronic device, which includes a clock generating circuit as described in any embodiment of the present invention. The clock generating circuit can be integrated into a chip inside the electronic device.
[0082] The clock generating circuit and the electronic device of the present invention have the relaxation oscillator of the present invention, so the accuracy and stability of the clock signal are improved, and thus the overall performance and reliability are improved.
[0083] It should be understood that the switching elements in the above examples can be implemented by any suitable conventional switching elements in the art such as MOS tubes and triodes, and the trigger circuit outputs corresponding periodic control signals according to the control requirements of these switching elements. Therefore, the periodic control signals output by the trigger circuit are not limited to the above For example, in other embodiments of the present invention, when Figure 4 When each first switch element and the second switch element in the trigger circuit are of opposite type and each third switch element and the second switch element are of the same type, the trigger circuit can only output a periodic control signal and and At the same time, it is provided to the control terminals of SW11, SW21 and SW31. At the same time, it is provided to the control terminals of SW12, SW22 and SW32. Figure 6 When each first switch element and the second switch element in the trigger circuit are of opposite type and each third switch element and the second switch element are of the same type, the trigger circuit can only output a periodic control signal and It is also provided to the control terminals of SW11, SW21 and SW31.
[0084] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation to the scope of the utility model. Any changes and modifications made by ordinary technicians in the field of the utility model based on the above disclosure shall fall within the protection scope of the technical solution of the utility model.
Claims
1. A relaxation oscillator, characterized in that: include: A charge-discharge circuit, comprising at least one charging branch and a discharging branch arranged corresponding to the charging branch, wherein the charging branch comprises a first switch element and a capacitor, wherein an input end of the first switch element is coupled to a power supply voltage, an output end of the first switch element is coupled to one end of the capacitor, and the other end of the capacitor is grounded, and the first switch element is periodically switched on and off to control the capacitor to perform periodic charging, and the discharging branch comprises a second switch element, wherein an input end of the second switch element is coupled to one end of the corresponding capacitor, an output end of the second switch element is coupled to the ground, and the second switch element is periodically switched on and off to control the corresponding capacitor to perform periodic discharge; A comparison circuit, coupled to the output node of each of the charging branches and a corresponding reference voltage, and used to compare the voltage of the output node of each of the charging branches with the corresponding reference voltage; a release circuit, comprising a release branch arranged corresponding to the charging branch, an input end of the release branch coupled to an input end of a first switch element of the corresponding charging branch, an output end of the release branch connected to ground, the release branch being turned on before the first switch element is turned on, and being turned off after the first switch element is turned on, so as to release the charge stored in the parasitic capacitor at the corresponding output node to ground; A trigger circuit is coupled to the output end of the comparison circuit, the control end of the first switch element and the control end of the release branch, and is used to control the on-off of the first switch element and the on-off of the release branch according to the output of the comparison circuit, and output a clock signal.
2. The relaxation oscillator according to claim 1, characterized in that The charging branch further includes a first current source, an input end of the first current source is coupled to a power supply voltage, an output end of the first current source is coupled to an input end of the first switch element, and the first current source is used to charge the capacitor when the first switch element is turned on.
3. The relaxation oscillator according to claim 1, characterized in that The discharge branch further includes a second current source, an input end of the second current source is coupled to an output end of the second switch element, an output end of the second current source is grounded, and the second current source is used to extract charges from the capacitor when the second switch element is turned on.
4. The relaxation oscillator according to claim 1, characterized in that The release branch has a third switch element, an input end of the third switch element is coupled to the input end of the corresponding first switch element in the charging branch, an output end of the third switch element is grounded, a control end of the third switch element is coupled to the trigger circuit, and the trigger circuit controls the on and off of the third switch element in reverse phase to the on and off of the first switch element.
5. The relaxation oscillator according to any one of claims 1 to 4, characterized in that: The device also includes a reference voltage generating circuit, which is coupled to the corresponding input terminal of the comparison circuit to provide at least one reference voltage to the comparison circuit.
6. The relaxation oscillator according to claim 5, characterized in that The reference voltage generating circuit has at least one voltage generating branch, the voltage generating branch includes a third current source and at least one resistor connected in series, and the voltage generating branch has at least one voltage dividing node, and the voltage dividing node outputs a corresponding reference voltage.
7. The relaxation oscillator according to claim 5, characterized in that The charge and discharge circuit has a first charging branch and a second charging branch, and the comparison circuit has a first comparator and a second comparator, the first input end of the first comparator is coupled to the output node of the first charging branch, the first input end of the second comparator is coupled to the output node of the second charging branch, and the second input end of the first comparator and the second input end of the second comparator are coupled to the same reference voltage, and the output end of the first comparator and the output end of the second comparator are respectively coupled to different input ends of the trigger circuit.
8. The relaxation oscillator according to claim 5, characterized in that The charge and discharge circuit has a charging branch, and the comparison circuit has a first comparator and a second comparator. The first input terminal of the first comparator is coupled to a first reference voltage, the second input terminal of the first comparator and the first input terminal of the second comparator are both coupled to the output node of the charging branch, the second input terminal of the second comparator is coupled to a second reference voltage lower than the first reference voltage, and the output terminal of the first comparator and the output terminal of the second comparator are respectively coupled to different input terminals of the trigger circuit.
9. A clock generating circuit, characterized in that: A relaxation oscillator comprising the relaxation oscillator according to any one of claims 1 to 8.
10. An electronic device, characterized in that: Includes the clock generating circuit as claimed in claim 9.