In-memory computing device with improved current read circuit
By designing word line activation units, memory arrays and digital detectors in in-memory computing devices, using integrated and counter-level sampling iteration techniques, the problems of high occupancy area and slow conversion time of ADCs in the prior art are solved, and low power consumption, low manufacturing cost and high performance in-memory computing devices are realized.
CN222636635UActive Publication Date: 2025-03-18STMICROELECTRONICS SRL
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Patent Information
- Application Number
- CN202323495897.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-18
- Filing Date
- 2023-12-21
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2033-12-21
AI Technical Summary
Technical Problem
The ADCs of existing in-memory computing devices have high die footprint and slow conversion times, resulting in high manufacturing costs and low performance.
Method used
An in-memory computing device is designed, including a word line activation unit, a memory array and a digital detector. The digital detector performs multiple successive sampling iterations through the integration stage and the counter stage, generates a time integral signal indicating the bit line current, and updates the output signal in response to the integration signal reaching the sampling threshold.
Benefits of technology
It realizes low power consumption and low manufacturing cost in-memory computing devices, avoids data transmission bandwidth limitations and improves performance.
✦ Generated by Eureka AI based on patent content.
Abstract
The present disclosure provides an in-memory computing device with an improved current read circuit. A word line activation unit computed in memory generates an activation signal as a function of an input value. An in-memory computing device includes a memory array having a plurality of memory cells (each memory cell stores a computing weight) coupled to a bit line and each coupled to a word line, and a digital detector. A cell current as a function of an activation signal and a calculation weight flows through each memory cell, and a bit line current as a function of a sum of the cell currents is generated. The digital detector performs successive iterations on the bit line current. In each iteration: the integration stage generates an integration signal indicative of a time integration of the bit line current and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integrated signal reaching a threshold.
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