Satellite load detection data transmission system

Abstract

The utility model provides a satellite load detection data transmission system which is characterized in that a detection data receiving antenna sends collected detection signals to a radio frequency data processing unit at the rear end, and the radio frequency data processing unit amplifies the received detection signals and then sends the amplified detection signals to an occultation data processing unit at the rear end for signal processing; the occultation data processing unit carries out level matching on the processed detection data through an isolator and then sends output high-speed parallel data to a gigabit Ethernet PHY transceiver, and the gigabit Ethernet PHY transceiver converts the high-speed parallel data into high-speed differential data and sends the high-speed differential data to a transformer module at the rear end; and the transformer module sends the high-speed differential data to the satellite service processing unit through the load connector. According to the utility model, occultation detection data processing efficiency is greatly improved, the satellite load detection data high-speed transmission development trend at present is better conformed, and great significance is provided for the development of the commercial aerospace field.

Description

Technical Field

[0001] The utility model belongs to the technical field of detection data transmission, in particular to a satellite payload detection data transmission system. Background Art

[0002] The basic principle of occultation detection technology is to receive navigation signals of the Global Navigation and Positioning System (GNSS) through low-orbit payload satellites. When these signals pass through the atmosphere and ionosphere, important parameters such as the frequency, phase, and amplitude of the signal itself will undergo relevant changes. The satellite payload receiver will actively receive these change information and invert it through relevant algorithms to obtain real-time key information such as atmospheric temperature, humidity, air pressure, and ionospheric electron density. This plays a vital role in space environment monitoring, enhancing the positioning accuracy of the navigation system, and improving the accuracy of weather forecasts.

[0003] At present, the occultation satellite payload receiver receives the detection data, and after a series of processing by the internal processor, it mostly uses LVDS data transmission to convert the original detection data into differential LVDS form and send it to the satellite service processing unit of the entire satellite at a transmission speed of about 62Mbps. The differential mode has strong anti-interference ability against common-mode noise, so it is widely used in the field of data transmission; however, with the rapid development of occultation detection technology, the amount of received detection data has further increased, and the LVDS data transmission rate has gradually failed to meet the needs of high-speed data transmission. Utility Model Content

[0004] In view of this, the utility model aims to propose a satellite payload detection data transmission system to solve the problem that the LVDS data transmission method cannot meet the demand for high-speed data transmission.

[0005] In order to achieve the above object, the technical solution of the utility model is implemented as follows:

[0006] The utility model provides a satellite payload detection data transmission system, comprising:

[0007] A detection data receiving antenna, a radio frequency data processing unit, an occultation data processing unit, an isolator, a Gigabit Ethernet PHY transceiver, a transformer module, a payload connector and a satellite service processing unit connected in sequence;

[0008] The detection data receiving antenna is configured to send the collected detection signal to the radio frequency data processing unit at the back end, and the radio frequency data processing unit is configured to amplify the received detection signal and send it to the occultation data processing unit at the back end for signal processing;

[0009] The occultation data processing unit is configured to perform level matching on the processed detection signal through the isolator, and then send the output high-speed parallel data to the Gigabit Ethernet PHY transceiver, and the Gigabit Ethernet PHY transceiver is configured to convert the high-speed parallel data into high-speed differential data and send it to the transformer module at the back end;

[0010] The transformer module is configured to send the high-speed differential data to the satellite service processing unit via the load connector.

[0011] Furthermore, the Gigabit Ethernet PHY transceiver is also configured to receive high-speed differential data from the outside and convert it into high-speed parallel data. The high-speed parallel data is sent to the occultation data processing unit through a parallel data bus and after level matching through the isolator. The occultation data processing unit is also configured to process the high-speed parallel data.

[0012] Furthermore, the occultation data processing unit is an FPGA, and the model of the FPGA is XC7V690T.

[0013] Further, the Gigabit Ethernet PHY transceiver includes an Ethernet PHY chip, and the Ethernet PHY chip is integrated with a high-speed parallel data transmission module and a high-speed differential data transmission module;

[0014] The TXD0-TXD7 pins and the RXD0-RXD7 pins of the high-speed parallel data transmission module are connected to the FPGA through an isolator;

[0015] The MDI0-MDI3 pins of the high-speed differential data transmission module are respectively connected with matching resistors, and the matching resistors are grounded through connected capacitors.

[0016] Furthermore, the Ethernet PHY chip adopts a module chip of model 88E1111-B2-BAB1I000.

[0017] Further, the first pin, the second pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the tenth pin and the twelfth pin of the transformer module are correspondingly connected to the MDI0-MDI3 pins of the high-speed differential data transmission module;

[0018] The third pin, the fourth pin, the ninth pin and the tenth pin of the transformer module are grounded via parallel capacitors;

[0019] The twenty-first pin and the twenty-second pin of the transformer module are respectively connected to a matching resistor, and the other end of the matching resistor is grounded through two series capacitors.

[0020] Furthermore, the transformer module adopts a 749020010A model transformer.

[0021] Furthermore, the first pin, the second pin, the fourth pin, the fifth pin, the seventh pin, the eighth pin, the tenth pin and the eleventh pin of the load connector are correspondingly connected to the twenty-fourth pin, the twenty-third pin, the twentieth pin, the nineteenth pin, the eighteenth pin, the seventeenth pin, the fourteenth pin and the thirteenth pin of the transformer module.

[0022] Furthermore, the load connector adopts a HJ30J-12ZKW model connector.

[0023] Compared with the prior art, the satellite payload detection data transmission system described in the utility model has the following beneficial effects:

[0024] The satellite payload detection data transmission system described in the utility model proposes from the design end to use a Gigabit Ethernet transceiver to convert the detection data into four pairs of differential Ethernet data. The data then passes through a transformer module to improve the data driving capability and increase the ability of differential data transmission to resist external interference. On the payload external connector, a space-grade differential signal transmission connector is used as a data transmission interface. The interface rate reaches 1Gbps, which is 16 times higher than traditional LVDS data transmission, achieving high-speed transmission of differential data and meeting the current trend and demand for high-speed transmission of satellite detection data. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the accompanying drawings:

[0026] Figure 1 A schematic diagram of a satellite payload detection data transmission system according to an embodiment of the utility model;

[0027] Figure 2 A circuit diagram of a high-speed parallel data transmission module according to an embodiment of the utility model;

[0028] Figure 3 A circuit diagram of a high-speed differential data transmission module according to an embodiment of the utility model;

[0029] Figure 4 A circuit diagram of a transformer module according to an embodiment of the utility model;

[0030] Figure 5 This is a circuit diagram of a load connector according to an embodiment of the utility model. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0032] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0033] Traditional occultation detection payloads generally use LVDS differential data transmission, which has strong anti-interference ability and a speed of about 62Mbps. However, with the development of occultation detection technology, the data processing and transmission volume of the detection payload itself are increasing. The traditional LVDS data transmission method has gradually failed to meet the high-speed transmission requirements of large amounts of data. Based on this, this embodiment proposes to use a Gigabit Ethernet transceiver for application in the field of high-speed transmission of satellite payload data, in combination with aerospace-grade transformers and aerospace-grade high-speed signal transmission connectors to meet the high-speed transmission requirements of detection data, which is more in line with the current trend of high-speed transmission of large amounts of data for satellite detection payloads. This embodiment has been actually applied in a certain occultation detection satellite payload.

[0034] See also Figure 1 As shown, this embodiment provides a satellite payload detection data transmission system, including:

[0035] A detection data receiving antenna, a radio frequency data processing unit, an occultation data processing unit, an isolator, a Gigabit Ethernet PHY transceiver, a transformer module, a payload connector and a satellite service processing unit connected in sequence;

[0036] The detection data receiving antenna is configured to send the collected detection signal to the radio frequency data processing unit at the back end, and the radio frequency data processing unit is configured to amplify the received detection signal and send it to the occultation data processing unit at the back end for signal processing;

[0037] The occultation data processing unit is configured to perform level matching on the processed detection signal through an isolator, and then send the output high-speed parallel data to the Gigabit Ethernet PHY transceiver, and the Gigabit Ethernet PHY transceiver is configured to convert the high-speed parallel data into high-speed differential data and send it to the transformer module at the back end;

[0038] The transformer module is configured to send high-speed differential data to the satellite service processing unit via the load connector.

[0039] Specifically, in this embodiment, the outermost part of the system is the detection data receiving antenna, which is generally located on the top of the satellite payload. After collecting the relevant detection signals, the antenna sends them to the back-end RF signal processing unit. After receiving these weak detection signals, the RF signal will be subjected to corresponding frequency selection, filtering and amplification. After that, the amplified signal containing the detection information will be sent to the back-end data processing FPGA for further processing. The FPGA model is Xilinx's V7 series XC7V690T. This model of FPGA has rich processor resources and high-speed communication serial port resources to meet the data processing requirements of conventional detection payloads. After FPGA processes the detection data, it sends the data to the Gigabit Ethernet PHY transceiver after passing through the isolator. The transceiver model is MARVELL's 88E1111-B2-BAB1I000. At this time, the parallel data is converted into four sets of high-speed differential data. A transformer is added at the back end to enhance the driving capability of the data signal, making the transmission distance farther and enhancing the signal's ability to resist external interference. The transformer level is aerospace grade, model Wurth's 749020010A. After the signal passes through the transformer, it is sent to the satellite service processing unit of the entire satellite through the high-speed differential signal connector of the payload to complete the transmission process of the detection data.

[0040] The transmission system described in this embodiment proposes to use a Gigabit Ethernet transceiver to convert the detection data into four pairs of differential Ethernet data from the design end. The data then passes through the transformer module to improve the data driving capability and increase the ability of differential data transmission to resist external interference. On the external connector of the payload, a space-grade differential signal transmission connector is used as the data transmission interface. The interface rate reaches 1Gbps, which is 16 times more than the traditional LVDS data transmission, realizing high-speed transmission of differential data and meeting the current trend and demand for high-speed transmission of satellite detection data. This application greatly improves the processing efficiency of occultation detection data, and is more in line with the current development trend of high-speed transmission of satellite payload detection data, which is of great significance to the development of the commercial aerospace field.

[0041] Specifically, the FPGA sends the detection data to the Ethernet PHY chip, such as Figure 2As shown, the high-speed parallel data transmission module configuration circuit diagram of the Ethernet PHY chip is represented by U262A. The Ethernet PHY chip receives 8-bit high-speed parallel data, clock and control signals sent from the FPGA. The high-speed parallel data includes PHY_TXD0~PHY_TXD7. The data transmission direction of this part is from FPGA to the Ethernet PHY chip, which is unidirectional transmission. PHY_GTXCLK is the high-speed reference clock for FPGA to send parallel data and control signals. The clock is generated by the FPGA inside, and the clock rate is 125MHz. The TX_EN signal is the send enable signal. When the FPGA is ready to send detection data, the pin of the PHY chip will be pulled low, and the chip will enter the sending state.

[0042] Among them, PHY_MDC is the reference clock of the chip serial configuration data. This clock does not need to be configured as a long clock. The maximum rate supports 8.3MHz. This pin needs to be configured with a pull-up resistor, R1914, with a resistance of 4.7KΩ.

[0043] PHY_MDIO is the configuration data pin of the chip. This pin is a bidirectional pin that supports the input of configuration data. After the chip configuration is completed, it will feedback the configuration completion status code to the FPGA. A pull-up resistor needs to be added to this pin. The resistance value of R1915 is 4.7KΩ. PHY_RESET is the hardware reset pin of the chip. This pin is valid at a low level. After being pulled low, the PHY chip hardware will be reset. It is used when data transmission is abnormal. Under normal working conditions, an external pull-up resistor is required to maintain a fixed high level state. The pull-up resistor is R1916 with a resistance value of 4.7KΩ.

[0044] like Figure 3 As shown in the figure, the high-speed differential data transmission module configuration circuit diagram of the Ethernet PHY chip communicating with the transformer is represented by U262B. The high-speed parallel data sent by the FPGA is converted into four groups of high-speed differential data MDI0~MDI3 after being processed by the Ethernet PHY chip, and transmitted to the back-end transformer. In order to achieve impedance matching, matching resistors are added to the differential data transmission terminals to better reduce signal reflections. The resistance value of the matching resistor is 50R, specifically, R1905, R1906, R1907, R1908, R1909, R1910, R1911 and R1912 in the figure below; it is consistent with the impedance of the actual PCB routing.

[0045] In addition, CONFIG[0]~CONFIG[6] are the configuration signals of the Ethernet PHY chip, among which CONFIG[1] is connected to ground, CONFIG[2], CONFIG[3] and CONFIG[6] are connected to 2.5V, and CONFIG[0], CONFIG[4], CONFIG[5] are connected to the FPGA module through hardware to realize the switching and control of specific modes.

[0046] In addition, the Ethernet PHY chip requires an external 25MHz clock for normal operation, and the frequency stability of the clock needs to be less than 20ppm to ensure normal and reliable data transmission.

[0047] For Ethernet PHY chip to send high-speed differential data to transformer module, such as Figure 4 As shown in the figure, it is a circuit wiring diagram of the transformer module. The transformer model is WURTH's 749020010A. The transformer module supports four sets of high-speed differential signal transformer outputs and has good isolation to ensure that the internal data transmission of the load will not be interfered by the outside world.

[0048] At the center tap position of the data input end, the four center taps need to be short-circuited together, and two 2.2UF voltage-stabilizing capacitors are added to ensure the level stability of the data conversion process.

[0049] At the center tap position of the data output end, it is necessary to add a 75Ω matching resistor to ensure the impedance matching of the data and reduce signal loss. After that, the four center taps are short-circuited and short-circuited to the internal ground of the load through two 3.9nF capacitors. Such a circuit connection can filter out some high-frequency stray noise and interference and will not affect normal data transmission.

[0050] For transformer modules, high-speed differential data is sent to the load external connector, such as Figure 4 and Figure 5 As shown in the figure, the transformer module transmits the signal after voltage transformation and isolation to the load connector. The connector model adopts the aerospace-grade electrical connector of Guizhou Aerospace Electric, HJ30J-12ZKW connector. This connector is a bent plug printed circuit board with better reliability and stability. The specific connection relationship is as follows Figure 5 As shown, the MDI[0] differential signal is connected to the 1 and 2 pins of J107, the MDI[1] differential signal is connected to the 4 and 5 pins of J107, the MDI[2] differential signal is connected to the 7 and 8 pins of J107, and the MDI[3] differential signal is connected to the 10 and 11 pins of J107. Pins 3, 6, 9, and 12 are the ground pins of the connector, located between the two differential pairs to ensure that there is no interference between them.

[0051] In some embodiments, the Gigabit Ethernet PHY transceiver is also configured to receive high-speed differential data from the outside and convert it into high-speed parallel data. The high-speed parallel data passes through a parallel data bus and is sent to the occultation data processing unit after level matching through an isolator. The occultation data processing unit is also configured to process the high-speed parallel data.

[0052] Specifically, in the embodiment, the Gigabit Ethernet PHY transceiver of the present embodiment is compatible with data receiving functions, such as Figure 2 As shown in the figure, the high-speed differential data from the outside will be converted into 8-way high-speed parallel data PHY_RXD0~PHY_RXD7 after passing through the Ethernet PHY chip. The parallel data passes through the parallel data bus, isolator for level matching, and then is sent to the FPGA for processing. RX_DV (Data Valid) is the valid flag for receiving data. When this pin is enabled, the received data begins to be decoded and transmitted. RX_ER represents the receive error code. During the process of receiving data, if an error occurs in data decoding, this pin will be used as an error flag to indicate that this round of data is abnormal. The receiving end can then consider that this packet data is invalid and proceed to receive the next data.

[0053] RX_CLK is the reference clock for receiving data, with a clock rate of 125MHz. It is used to synchronize 8-bit parallel received data and two control signals. This part of the high-speed data receiving function can generally be used for the payload to receive remote control and telemetry instructions from the satellite service unit. This functional module is a reserved design.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model, and they should all be included in the scope of the claims and specification of the utility model.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A satellite payload detection data transmission system, characterized in that: include: A detection data receiving antenna, a radio frequency data processing unit, an occultation data processing unit, an isolator, a Gigabit Ethernet PHY transceiver, a transformer module, a payload connector and a satellite service processing unit connected in sequence; The detection data receiving antenna is configured to send the collected detection signal to the radio frequency data processing unit at the back end, and the radio frequency data processing unit is configured to amplify the received detection signal and send it to the occultation data processing unit at the back end for signal processing; The occultation data processing unit is configured to perform level matching on the processed detection signal through the isolator, and then send the output high-speed parallel data to the Gigabit Ethernet PHY transceiver, and the Gigabit Ethernet PHY transceiver is configured to convert the high-speed parallel data into high-speed differential data and send it to the transformer module at the back end; The transformer module is configured to send the high-speed differential data to the satellite service processing unit via the load connector.

2. A satellite payload detection data transmission system according to claim 1, characterized in that: The Gigabit Ethernet PHY transceiver is also configured to receive high-speed differential data from the outside and convert it into high-speed parallel data. The high-speed parallel data is sent to the occultation data processing unit through a parallel data bus and after level matching through the isolator. The occultation data processing unit is also configured to process the high-speed parallel data.

3. A satellite payload detection data transmission system according to claim 1, characterized in that: The occultation data processing unit is FPGA, and the model of the FPGA is XC7V690T.

4. A satellite payload detection data transmission system according to claim 3, characterized in that: The Gigabit Ethernet PHY transceiver comprises an Ethernet PHY chip, on which a high-speed parallel data transmission module and a high-speed differential data transmission module are integrated; The TXD0-TXD7 pins and the RXD0-RXD7 pins of the high-speed parallel data transmission module are connected to the FPGA through an isolator; The MDI0-MDI3 pins of the high-speed differential data transmission module are respectively connected with matching resistors, and the matching resistors are grounded through connected capacitors.

5. A satellite payload detection data transmission system according to claim 4, characterized in that: The Ethernet PHY chip adopts the 88E1111-B2-BAB1I000 model module chip.

6. A satellite payload detection data transmission system according to claim 4, characterized in that: The first pin, the second pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the tenth pin and the twelfth pin of the transformer module are correspondingly connected to the MDI0-MDI3 pins of the high-speed differential data transmission module; The third pin, the fourth pin, the ninth pin and the tenth pin of the transformer module are grounded via parallel capacitors; The twenty-first pin and the twenty-second pin of the transformer module are respectively connected to a matching resistor, and the other end of the matching resistor is grounded through two series capacitors.

7. A satellite payload detection data transmission system according to claim 6, characterized in that: The transformer module adopts a 749020010A model transformer.

8. A satellite payload detection data transmission system according to claim 6, characterized in that: The first pin, the second pin, the fourth pin, the fifth pin, the seventh pin, the eighth pin, the tenth pin and the eleventh pin of the load connector are correspondingly connected to the twenty-fourth pin, the twenty-third pin, the twentieth pin, the nineteenth pin, the eighteenth pin, the seventeenth pin, the fourteenth pin and the thirteenth pin of the transformer module.

9. A satellite payload detection data transmission system according to claim 8, characterized in that: The load connector adopts HJ30J-12ZKW model connector.

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