Information processing circuit based on VU9P chip

Abstract

The utility model discloses an information processing circuit based on a VU9P chip, belonging to the field of FPGA data processing technology, the circuit comprises a VU9P chip, a GRBM8548 chip and an AC7Z100 chip, the VU9P chip is connected with the GRBM8548 chip through PCIE and LOCAL BUS, the VU9P chip is connected with the AC7Z100 chip through the LOCAL BUS, the VU9P chip is connected with two paths of external expansion FMC interfaces through IO ports, the VU9P chip is connected with two paths of 100G network ports through GTY ports, the VU9P chip is connected with four paths of 10G network ports through GTY ports, and the VU9P chip is connected with four paths of 10G network ports through GTY ports. The VU9P chip is connected with sixteen paths of gigabit network ports through a GTY port, and the VU9P chip is further connected with multiple paths of DDR4, SRAM and NAND FLASH high-capacity off-chip storage.

Description

Technical Field

[0001] The utility model belongs to the technical field of FPGA data processing, and in particular relates to an information processing circuit based on a VU9P chip. Background Art

[0002] Network information uses different processing platforms to process different information tasks. Common ones are dedicated network switches, network servers, and FPGA special field network information processors. Network switches have the characteristics of stable information processing and fast processing speed. Network servers have the characteristics of complex information processing and complex processing methods.

[0003] FPGA heterogeneous information processing has the characteristics of high flexibility, fast computing speed, and high real-time performance. At present, FPGA heterogeneous information processing is mainly based on gigabit and 10-gigabit. The programming model of FPGA array type in the accelerated computing process has the disadvantages of insufficient heterogeneous resources and high processing speed of FPGA.

[0004] Currently, in order to obtain better performance from heterogeneous computing systems with FPGAs and traditional processors working together, developers need to spend a lot of effort to convert traditional codes into appropriate FPGA architectures and carefully design hardware configurations to achieve overall functionality. The above work requires rich FPGA design expertise and a lot of cost investment, as well as overall strategic experience in inputting and outputting data into and out of these FPGA accelerators, in order to complete the rich peripheral interfaces of the task and the interaction between the two coprocessors.

[0005] However, it is very difficult for technicians in this field to complete the above work. How to design an FPGA information processing circuit that takes into account the characteristics of FPGA heterogeneous information processing and processor processing through hardware design has become a technical problem in this field. Utility Model Content

[0006] In view of the above technical problems, the utility model provides an information processing circuit based on the VU9P chip, which realizes the function of high-speed interconnection between a heterogeneous acceleration FPGA and two CPUs based on high-speed hardware circuit design technology, supports 16-way Gigabit network ports, 4-way 10 Gigabit network cards and 2-way 100G network ports, and also supports PCIE's IPASS interface, 2-way processor configuration interface and two-way external expansion FMC interface, and has the characteristics of fast data processing speed and rich interfaces.

[0007] The utility model solves the above problems through the following technical means:

[0008] An information processing circuit based on the VU9P chip, characterized in that it includes a VU9P chip, a GRBM8548 chip, and an AC7Z100 chip, where: the VU9P chip is connected to the GRBM8548 chip through PCIE and LOCAL BUS; the VU9P chip is connected to the AC7Z100 chip through LOCAL BUS; the VU9P chip is connected to two external expansion FMC interfaces through IO ports; the VU9P chip is connected to two 100G network ports through GTY ports; the VU9P chip is connected to four 10G network ports through GTY ports; the VU9P chip is connected to sixteen gigabit network ports through GTY ports; the VU9P chip is also connected to multiple DDR4, SRAM, and NANDFLASH large-capacity off-chip storages.

[0009] Preferably, it further includes a power supply circuit composed of an LTM4700 chip, an LTM4644 chip, and a TPS51200 chip, where: the 12V input power supply is converted into a 0.85V power supply through a single LTM4700 chip and delivered to the INTVCC pin of the VU9P chip; the 12V input power supply is respectively converted into 1.2V power supply, 1.0V power supply, 1.8V power supply, 1.2V power supply, 1.8V power supply, and 2.5V power supply through the LTM4644 chip and delivered to the MGTAVTT pin, MGTAVCC pin, VCCAUX pin, and VCC_1V8 pin of the VU9P chip respectively.

[0010] Preferably, the BANK42 pin set of the VU9P chip is connected to the LOCAL BUS of the AC7Z100 chip as the LOCAL BUS, and the BNAK125 pin set and BANK126 pin set of the VU9P chip are interconnected with the PCIE interface of the AC7Z100 chip to achieve PCIE communication.

[0011] Preferably, the BANK67 pin set of the VU9P chip is connected to the LOCAL BUS of the GRBM8548 chip as another group of LOCAL BUS.

[0012] Preferably, the BANK227 pin set, BANK228 pin set, BANKk229 pin set, and BANK230 pin set of the VU9P chip achieve the function of sixteen gigabit network ports through the SGMII interface.

[0013] Preferably, the BANK232 pin set and BANK233 pin set of the VU9P chip are externally connected to a 100G Ethernet interface.

[0014] Preferably, the BANK72 pin set, the BANK71 pin set and the BANK70 pin set of the VU9P chip mount a set of 64-bit 4GB DDR4 memory groups.

[0015] Preferably, the BANK65 pin set, the BANK64 pin set and the BANK66 pin set of the VU9P chip mount a set of 1GB SRAM with a 32-bit width.

[0016] Preferably, the BANK42 pin set, the BANK41 pin set, the BANK121 pin set and the BANK10 pin set of the VU9P chip realize the high-speed external expansion FMC interface of two groups of HPCs.

[0017] Preferably, it also includes a heat sink, a cover plate, and a circuit board for welding circuits, wherein: the heat sink is a rectangular structure, a plurality of heat dissipation teeth are evenly cut out of the four sides of the heat sink, a mounting cavity is arranged in the middle of the heat sink, X-shaped connecting arms are arranged at the four corners of the heat sink, connecting holes are arranged at the ends of the X-shaped connecting arms, and arc-shaped tooth roots are formed at the positions where the heat dissipation teeth contact the X-shaped connecting arms; the cover plate is composed of a cover body and a plurality of mounting ears, and the circuit board is installed in a cavity formed by the cover plate and the mounting cavity; a sealing ring is arranged between the cover plate and the mounting cavity; one or more circular bottom cavities are arranged at the bottom of the heat sink, a tooth platform is arranged at the part where the circular bottom cavity overlaps with the heat dissipation teeth to ensure that the bottom of the circular bottom cavity is flat, and a heat dissipation fan is installed in the circular bottom cavity; a side opening is arranged on the side of the heat sink, and a plurality of interfaces are installed on the side opening.

[0018] The information processing circuit based on the VU9P chip of the utility model has the following beneficial effects:

[0019] 1) The circuit can be connected to a non-standard interface board through the FMC HPC connector to achieve the conversion between non-standard interfaces and standard optical / electrical Ethernet interfaces. In addition, the multi-port packet switching function can be completed through FPGA. In actual use, the switch control and management, routing and other functions can be completed through the combination of CPU and FPGA. Finally, the circuit has a variety of large-capacity off-chip storage such as DDR4, SRAM, NANDFLASH, etc.

[0020] 2) The heat sink of this circuit configuration is made of heat-conducting metal material, and heat-dissipating teeth are designed on the entire side. The heat-dissipating teeth around and the heat-dissipating fan at the bottom can effectively reduce the temperature of the accelerator card. In particular, the circular bottom cavity at the bottom and the heat-dissipating teeth adopt a coincident layout scheme, which can accelerate the gas flow between the heat-dissipating teeth as much as possible. The design scheme of the arc-shaped tooth root can greatly reduce the wall thickness and improve the thermal conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solution of the present utility model, the accompanying drawings required for implementation will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0022] Figure 1 is the overall circuit schematic diagram of the present utility model;

[0023] Figure 2 is the power supply circuit schematic diagram of the present utility model;

[0024] Figure 3 is the pin schematic diagram of the VU9P chip connecting to the AC7Z100 chip in the present utility model;

[0025] Figure 4 is the pin schematic diagram of the VU9P chip connecting to the GRBM8548 chip in the present utility model;

[0026] Figure 5 is the schematic diagram of the connection between the BANK227 pin set of the VU9P chip and the gigabit network port in the present utility model;

[0027] Figure 6 is the pin schematic diagram of the VU9P chip connecting to the 100G Ethernet interface in the present utility model;

[0028] Figure 7 is the 100G network port circuit schematic diagram of the present utility model;

[0029] Figure 8 is the FMC interface circuit schematic diagram of the present utility model;

[0030] Figure 9 is the overall schematic diagram of the heat dissipation seat structure of the present utility model;

[0031] Figure 10 is the schematic diagram of the bottom structure of the heat dissipation seat of the present utility model;

[0032] Figure 11 is the schematic diagram of the side structure of the heat dissipation seat of the present utility model.

[0033] In the formula, 1 - heat dissipation seat, 101 - heat dissipation teeth, 102 - installation cavity, 103 - X-shaped connecting arm, 104 - connecting hole, 105 - arc-shaped tooth root, 106 - sealing ring, 107 - circular bottom cavity, 108 - tooth platform, 109 - heat dissipation fan, 110 - side through port, 111 - interface, 2 - cover plate, 201 - cover body, 202 - installation ear, 3 - circuit board. Specific embodiments

[0034] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model. The terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "plurality" is two or more.

[0035] The present utility model will be described in detail below with reference to the drawings.

[0036] As Figures 1 to 8 shown, the information processing circuit based on the VU9P chip includes a VU9P chip, a GRBM8548 chip, and an AC7Z100 chip. In the figure, the VU9P chip is connected to the GRBM8548 chip through PCIE and LOCAL BUS; the VU9P chip is connected to the AC7Z100 chip through LOCAL BUS; the VU9P chip is connected to two externally expanded FMC interfaces through IO ports; the VU9P chip is connected to two 100G network ports through GTY ports; the VU9P chip is connected to four 10G network ports through GTY ports; the VU9P chip is connected to sixteen gigabit network ports through GTY ports; the VU9P chip is also connected to multiple DDR4, SRAM, and NANDFLASH large-capacity off-chip storages.

[0037] It should be noted that the VU9P chip, the GRBM8548 chip, and the AC7Z100 chip form a butterfly interaction circuit. The connection between the VU9P type FPGA and the AC7Z100 and GRBM8548 is realized through the LOCAL BUS and the PCIE bus. Among them, the data pins, clock pins, and control pins of the LOCAL BUS are interconnected.

[0038] In the figure, it also includes a power supply circuit composed of an LTM4700 chip, an LTM4644 chip, and a TPS51200 chip. The power supply circuit is used to supply power to the chips. Among them: the 12V input power supply is converted into a 0.85V power supply through a single LTM4700 chip and delivered to the INTVCC pin of the VU9P chip; the 12V input power supply is respectively converted into 1.2V power supply, 1.0V power supply, 1.8V power supply, 1.2V power supply, 1.8V power supply, and 2.5V power supply through the LTM4644 chip and delivered to the MGTAVTT pin, MGTAVCC pin, VCCAUX pin, and VCC_1V8 pin of the VU9P chip respectively.

[0039] In this embodiment, the BANK42 pin set of the VU9P chip is connected to the LOCAL BUS bus of the AC7Z100 chip as the LOCAL BUS bus, and the BNAK125 pin set and BANK126 pin set of the VU9P chip are interconnected with the PCIE interface of the AC7Z100 chip to achieve PCIE communication. The BANK67 pin set of the VU9P chip is connected to the LOCAL BUS bus of the GRBM8548 chip as another group of LOCAL BUS buses.

[0040] Specifically, the BANK227 pin set, BANK228 pin set, BANKk229 pin set, and BANK230 pin set of the VU9P chip implement the function of 16 gigabit Ethernet ports through the SGMII interface. The BANK232 pin set and BANK233 pin set of the VU9P chip are externally connected to a 100G Ethernet interface to achieve interaction with 100G Ethernet devices.

[0041] Specifically, the BANK72 pin set, BANK71 pin set, and BANK70 pin set of the VU9P chip are mounted with a group of 64-bit 4GB DDR4 memory banks. The DDR4 memory banks are used for data caching when processing network information packets. Its working rate can reach 170Gbit / s. The BANK65 pin set, BANK64 pin set, and BANK66 pin set of the VU9P chip are mounted with a group of 32-bit wide 1GB SRAM. The SRAM is used for high-speed data caching and exchange during the network information processing process. The BANK42 pin set, BANK41 pin set, and BANK121 pin set and BANK10 pin set of the VU9P chip implement two groups of high-speed external expansion FMC interfaces for HPC to facilitate users to expand functions such as network ports or 100G network ports. In addition, the VU9P chip is externally connected with a NAND Flash to facilitate functions such as storing information exchange parameters for network information devices.

[0042] During actual operation, this circuit realizes the function of high-speed interconnection between a heterogeneous acceleration FPGA and two CPUs, supports 16 Gigabit Ethernet ports, 4 10 Gigabit network cards and 2 100 Gigabit Ethernet ports, and also supports the PCIE IPASS interface, 2 processor configuration interfaces and two external expansion FMC interfaces, featuring fast data processing speed and rich interfaces.

[0043] As Figures 9 to 11 shown, it also includes a heat sink 1, a cover plate 2, and a circuit board 3 for welding the circuit. Among them: the heat sink 1 is of a cuboid structure. Multiple heat dissipation teeth 101 are evenly cut out on the four side faces of the heat sink 1. An installation cavity 102 is arranged in the middle of the heat sink 1. X-shaped connecting arms 103 are arranged at the four corners of the heat sink 1. Connection holes 104 are arranged at the ends of the X-shaped connecting arms 103. Arc-shaped tooth roots 105 are formed at the positions where the heat dissipation teeth 101 contact the X-shaped connecting arms 103; the cover plate 2 is composed of a cover body 201 and multiple installation ears 202. The circuit board 3 is installed in the cavity formed by the cover plate 2 and the installation cavity 102.

[0044] Specifically, a sealing ring 106 is arranged between the cover plate 2 and the installation cavity 102. One or more circular bottom cavities 107 are arranged at the bottom of the heat sink 1. Tooth platforms 108 are opened at the parts where the circular bottom cavities 107 coincide with the heat dissipation teeth 101 to ensure the flatness of the bottom of the circular bottom cavities 107. Heat dissipation fans 109 are installed in the circular bottom cavities 107. Side through ports 110 are opened on the side faces of the heat sink 1, and multiple interfaces 111 are installed on the side through ports 110.

[0045] During actual application, the heat sink configured for this heterogeneous acceleration card is made of a heat-conducting metal material, and heat dissipation teeth are designed on the entire side face. The heat dissipation teeth around and the heat dissipation fans at the bottom can effectively reduce the temperature of the acceleration card. In particular, the circular bottom cavities at the bottom and the heat dissipation teeth adopt a coincident layout scheme, which can accelerate the gas flow between the heat dissipation teeth as much as possible. The design scheme of the arc-shaped tooth roots can greatly reduce the wall thickness and improve the heat conduction ability.

[0046] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An information processing circuit based on a VU9P chip, characterized in that: Including VU9P chip, GRBM8548 chip and AC7Z100 chip, among which: The VU9P chip is connected to the GRBM8548 chip via PCIE and LOCAL BUS; The VU9P chip is connected to the AC7Z100 chip via the LOCAL BUS; The VU9P chip is connected to two external expansion FMC interfaces via the IO port; The VU9P chip is connected to two 100G network ports through the GTY port; The VU9P chip is connected to four 10G network ports via the GTY port; The VU9P chip is connected to the sixteen-way Gigabit network port via the GTY port; The VU9P chip is also connected to multiple DDR4, SRAM, and NAND FLASH large-capacity off-chip storages.

2. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: It also includes a power supply circuit composed of an LTM4700 chip, an LTM4644 chip, and a TPS51200 chip, wherein: a 12V input power supply is converted into a 0.85V power supply by a single LTM4700 chip and transmitted to the INTVCC pin of the VU9P chip; the 12V input power supply is converted into 1.2V power supply, 1.0V power supply, 1.8V power supply, 1.2V power supply, 1.8V power supply, and 2.5V power supply by the LTM4644 chip and transmitted to the MGTAVTT pin, MGTAVCC pin, VCCAUX pin, and VCC_1V8 pin of the VU9P chip respectively.

3. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK42 pin set of the VU9P chip is connected to the LOCAL BUS bus of the AC7Z100 chip as the LOCAL BUS bus, and the BNAK125 pin set and the BANK126 pin set of the VU9P chip are interconnected with the PCIE interface of the AC7Z100 chip to realize PCIE communication.

4. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK67 pin set of the VU9P chip is used as another set of LOCAL BUS buses to be connected to the LOCAL BUS bus of the GRBM8548 chip.

5. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK227 pin set, BANK228 pin set, BANKk229 pin set and BANK230 pin set of the VU9P chip realize the 16-channel Gigabit network port function through the SGMII interface.

6. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK232 pin set and the BANK233 pin set of the VU9P chip are externally connected to a 100G Ethernet interface.

7. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK72 pin set, BANK71 pin set and BANK70 pin set of the VU9P chip mount a set of 64-bit 4GB DDR4 memory groups.

8. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK65 pin set, the BANK64 pin set and the BANK66 pin set of the VU9P chip mount a set of 1GB SRAM with a 32-bit width.

9. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: The BANK42 pin set, the BANK41 pin set, the BANK121 pin set and the BANK10 pin set of the VU9P chip realize the high-speed external expansion FMC interface of two groups of HPCs.

10. The information processing circuit based on the VU9P chip according to claim 1, characterized in that: It also includes a heat sink (1), a cover plate (2), and a circuit board (3) for welding circuits, wherein: The heat sink (1) is a rectangular parallelepiped structure, a plurality of heat dissipation teeth (101) are evenly cut out on the four sides of the heat sink (1), a mounting cavity (102) is provided in the middle of the heat sink (1), X-shaped connecting arms (103) are provided at the four corners of the heat sink (1), a connecting hole (104) is provided at the end of the X-shaped connecting arm (103), and an arc-shaped tooth root (105) is formed at the position where the heat dissipation teeth (101) contact the X-shaped connecting arm (103); the cover plate (2) is composed of a cover body (201) and a plurality of mounting ears (202), and the circuit board (3) is installed in a cavity formed by the cover plate (2) and the mounting cavity (102); A sealing ring (106) is provided between the cover plate (2) and the installation cavity (102); The bottom of the heat sink (1) is provided with one or more circular bottom cavities (107), and a tooth platform (108) is provided at the portion where the circular bottom cavity (107) overlaps with the heat dissipation teeth (101) to ensure that the bottom of the circular bottom cavity (107) is flat, and a heat dissipation fan (109) is installed in the circular bottom cavity (107); A side opening (110) is provided on the side of the heat dissipation seat (1), and a plurality of interfaces (111) are installed on the side opening (110).

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