Multifunctional two-disk-position backboard applied to rack-mounted server

Abstract

The utility model discloses a multifunctional two-disk position backboard applied to a rack-mounted server, which is characterized in that a storage module, a voltage monitoring module, an NVMe connector, a temperature monitoring module, a first U.2 connector and a second U.2 connector are all connected with a first CPLD (Complex Programmable Logic Device) chip, and each U.2 connector is also respectively connected with an SAS / SATA (Serial Attached SCSI / Serial Advanced Technology Attachment) connector and an NVMe / SATA / SAS hard disk; the power input end of the slow start module is connected with a power supply and the first CPLD chip, and the power output end of the slow start module is connected with the two U.2 connectors and the first CPLD chip. And the storage module, the voltage monitoring module, the temperature monitoring module, the NVMe connector and the SAS / SATA connector are also connected with a mainboard of the rack-mounted server. According to the technical scheme, module specialization, multifunctionality and compatibility design are achieved, the size is small, debugging is convenient, high efficiency, reliability and data safety of operation can be guaranteed, and the system is suitable for servers of various types.

Description

Technical Field

[0001] The utility model belongs to the technical field of servers, and particularly relates to a multi-functional two-disk-position backplane applied to a rack-mounted server. Background Art

[0002] People's requirements for high-performance servers are getting higher and higher. In particular, data processing capabilities and huge data storage capabilities are one of the key research directions. With the continuous improvement of server performance, there are more and more internal functional components, so the internal space of the chassis is becoming increasingly compact. The modular specialization, miniaturization, and functional diversification of component design are to achieve more functions in a limited space. The server hard disk backplane is a hub of the server storage subsystem dedicated to managing and connecting multiple hard disks and providing a data transmission channel. Common hard disks include solid-state drives (SSDs) and hard disk drives (HDDs). Compared with HDDs, SSDs have faster data transmission capabilities and smaller volumes, and are one of the essential components for high-performance servers.

[0003] Since the hard disk backplane in the prior art has a single function: on the one hand, the interface compatibility is poor and it cannot be compatible with multiple hard disk interfaces at the same time, that is, it only supports SATA interfaces or SAS interfaces or NVME interfaces and cannot adapt to various types of hard disks; on the other hand, it only serves as a bridge for information interaction between the hard disk and the motherboard, with a single function. Therefore, this application proposes a multi-functional two-disk-position backplane applied to a rack-mounted server. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the above problems by proposing a multi-functional two-disk-position backplane applied to a rack-mounted server, which realizes modular specialization, versatility, and compatibility design, has a small volume and is convenient for debugging, helps to ensure the high efficiency, reliability, and data security of the operation of the server storage subsystem, and can be applicable to servers of various models.

[0005] To achieve the above purpose, the technical solution adopted by the utility model is as follows:

[0006] A multi-functional two-disk-position backplane applied to a rack-mounted server proposed by the utility model is installed on the rack-mounted server and includes a storage module, a soft start module, a voltage monitoring module, a first CPLD chip, an NVMe connector, a SAS / SATA connector, a temperature monitoring module, a first U.2 connector, and a second U.2 connector, wherein:

[0007] The storage module, voltage monitoring module, NVMe connector, temperature monitoring module, first U.2 connector and second U.2 connector are all connected to the first CPLD chip. The SAS / SATA connector is respectively connected to the first U.2 connector and the second U.2 connector. The first U.2 connector and the second U.2 connector are also respectively used to connect an NVMe hard disk, a SATA hard disk or a SAS hard disk;

[0008] The power input terminals of the soft start module are respectively connected to the power supply and the first CPLD chip, and the power output terminals are respectively connected to the first U.2 connector, the second U.2 connector and the first CPLD chip;

[0009] The storage module, voltage monitoring module, temperature monitoring module, NVMe connector and SAS / SATA connector are also all connected to the motherboard of the rack-mounted server.

[0010] Preferably, the motherboard of the rack-mounted server is provided with a CPU, a BMC, a second CPLD chip, a SATA controller and a clock chip. The storage module, voltage monitoring module and temperature monitoring module are all connected to the BMC and the CPU. The NVMe connector is also respectively connected to the clock chip, the BMC, the CPU and the second CPLD chip. The SAS / SATA connector is also connected to the SATA controller.

[0011] Preferably, the multifunctional two-disk bay backplane applied to the rack-mounted server further includes a sideband signal connector and a power module. The storage module, voltage monitoring module and temperature monitoring module are all connected to the BMC and the CPU through the sideband signal connector. The power module is a power connector. The rack-mounted server further includes a PSU power supply. The two ends of the power module are respectively connected to the power input terminal of the soft start module and the PSU power supply. The sideband signal connector is also connected to the PSU power supply, and the multifunctional two-disk bay backplane applied to the rack-mounted server is powered by the PSU power supply.

[0012] Preferably, the storage module, soft start module, voltage monitoring module, first CPLD chip, sideband signal connector, NVMe connector, SAS / SATA connector and power module are all located on the TOP surface of the multifunctional two-disk bay backplane applied to the rack-mounted server, and the temperature monitoring module, first U.2 connector and second U.2 connector are all located on the BOT surface of the multifunctional two-disk bay backplane applied to the rack-mounted server.

[0013] Preferably, the sideband signal connector is a low-speed connector, and the NVMe connector, SAS / SATA connector, first U.2 connector and second U.2 connector are all high-speed connectors.

[0014] Preferably, the first CPLD chip includes a hard disk hot-swap module, a power-on management module, and a lighting module. The hard disk hot-swap module, the power-on management module, and the lighting module are respectively connected to an NVMe hard disk, a SATA hard disk, or a SAS hard disk through a first U.2 connector and a second U.2 connector.

[0015] Preferably, the storage module is an EEPROM chip, the soft-start module is an over-current and over-voltage protection chip, the voltage monitoring module is an AD conversion chip, and the temperature monitoring module is a temperature sensor chip.

[0016] Preferably, the CPLD chip is selected from the GD32 series chips, the EEPROM chip is selected as the BL24C64A, the over-current and over-voltage protection chip is selected as the SGM40657, the AD conversion chip is selected as the ADS7828, and the temperature sensor chip is selected as the NST117.

[0017] Preferably, the first CPLD chip further includes a JTAG module for burning program firmware.

[0018] Preferably, the length of the multi-functional two-disk bay backplane applied to a rack-mounted server is 150 mm, the width is 67 mm, and the board layer is 12 layers.

[0019] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0020] This two-disk bay backplane can install and manage two solid-state hard disks with SATA / SAS / NVMe interfaces. Its main structure includes a storage module, a soft-start module, a voltage monitoring module, a first CPLD chip, a sideband signal connector, an NVMe connector, a SAS / SATA connector, a power module, a temperature monitoring module, a first U.2 connector, and a second U.2 connector. The storage module stores the label information of the two-disk bay backplane and the version information of the burned program firmware. The soft-start module realizes the over-current and over-voltage protection function for large currents. The voltage monitoring module realizes the real-time monitoring function of various levels of the two-disk bay backplane. The first CPLD chip realizes the hard disk hot-swap function, the power-on management function, and the lighting control function. The temperature monitoring module realizes the temperature monitoring and alarm function of the two-disk bay backplane. It has carried out module specialization, multi-functionality, and compatibility design, simplified the complexity of the server motherboard, reduced the debugging difficulty of the motherboard and the backplane for the debugger, enabled users to flexibly match hard disks with various interfaces according to their own needs for daily use, and helped to ensure the high efficiency and reliability of the server storage subsystem operation. It also improves data security and the maintainability of the backplane, and has a small volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is the circuit connection diagram of the two-disk bay backplane of the present utility model;

[0022] Figure 2 This is the layout diagram of the TOP surface of the two-disk bay backplane of the present utility model;

[0023] Figure 3 This is the layout diagram of the BOT surface of the two-disk bay backplane of the present utility model;

[0024] Figure 4 This is the working principle diagram of the two-disk bay backplane of the present utility model;

[0025] Figure 5 This is the debugging principle diagram of the two-disk bay backplane of the present utility model.

[0026] Explanation of reference numerals: 1, storage module; 2, soft start module; 3, voltage monitoring module; 4, first CPLD chip; 5, sideband signal connector; 6, NVMe connector; 7, SAS / SATA connector; 8, power supply module; 9, temperature monitoring module; 10, first U.2 connector; 11, second U.2 connector. Detailed implementation manners

[0027] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0028] It should be noted that when a component is referred to as being "connected" to another component, it can be directly connected to the other component or there may also be an intermediate component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field of the present application. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0029] As Figures 1-5 shown, a multifunctional two-disk bay backplane applied to a rack-mounted server is installed on the rack-mounted server, and is characterized in that: the multifunctional two-disk bay backplane applied to the rack-mounted server includes a storage module 1, a soft start module 2, a voltage monitoring module 3, a first CPLD chip 4, an NVMe connector 6, a SAS / SATA connector 7, a temperature monitoring module 9, a first U.2 connector 10 and a second U.2 connector 11, wherein:

[0030] The storage module 1, the voltage monitoring module 3, the NVMe connector 6, the temperature monitoring module 9, the first U.2 connector 10, and the second U.2 connector 11 are all connected to the first CPLD chip 4. The SAS / SATA connector 7 is respectively connected to the first U.2 connector 10 and the second U.2 connector 11. The first U.2 connector 10 and the second U.2 connector 11 are also respectively used to connect an NVMe hard disk, a SATA hard disk, or a SAS hard disk;

[0031] The power input terminals of the soft start module 2 are respectively connected to the power supply and the first CPLD chip 4, and the power output terminals are respectively connected to the first U.2 connector 10, the second U.2 connector 11, and the first CPLD chip 4;

[0032] The storage module 1, the voltage monitoring module 3, the temperature monitoring module 9, the NVMe connector 6, and the SAS / SATA connector 7 are also all connected to the motherboard of the rack-mounted server.

[0033] In one embodiment, the motherboard of the rack-mounted server is provided with a CPU, a BMC, a second CPLD chip, a SATA controller, and a clock chip. The storage module 1, the voltage monitoring module 3, and the temperature monitoring module 9 are all connected to the BMC and the CPU. The NVMe connector 6 is also respectively connected to the clock chip, the BMC, the CPU, and the second CPLD chip. The SAS / SATA connector 7 is also connected to the SATA controller. Among them, the selected model of the SATA controller can be the Feiteng X100 chip, which is a component of the internal structure of the rack-mounted server, that is, the key devices on the motherboard of the rack-mounted server in the prior art, and will not be elaborated here.

[0034] In one embodiment, the multifunctional two-disk position backplane applied to the rack-mounted server further includes a sideband signal connector 5 and a power module 8. The storage module 1, the voltage monitoring module 3, and the temperature monitoring module 9 are all connected to the BMC and the CPU through the sideband signal connector 5. The power module 8 is a power connector. The rack-mounted server further includes a PSU power supply. Both ends of the power module 8 are respectively connected to the power input terminal of the soft start module 2 and the PSU power supply. The sideband signal connector 5 is also connected to the PSU power supply, and the multifunctional two-disk position backplane applied to the rack-mounted server is powered by the PSU power supply. Among them, the PSU power supply is preferably connected to the sideband signal connector through the power management chip at the motherboard end to supply power to the two-disk position backplane.

[0035] In one embodiment, the storage module 1, the soft start module 2, the voltage monitoring module 3, the first CPLD chip 4, the sideband signal connector 5, the NVMe connector 6, the SAS / SATA connector 7, and the power module 8 are all located on the TOP surface of the multi-functional two-disk bay backplane applied to the rack-mounted server, and the temperature monitoring module 9, the first U.2 connector 10, and the second U.2 connector 11 are all located on the BOT surface of the multi-functional two-disk bay backplane applied to the rack-mounted server.

[0036] In one embodiment, the sideband signal connector 5 is a low-speed connector, and the NVMe connector 6, the SAS / SATA connector 7, the first U.2 connector 10, and the second U.2 connector 11 are all high-speed connectors.

[0037] In one embodiment, the first CPLD chip 4 includes a hard disk hot-swap module, a power-on management module, and a lighting module. The hard disk hot-swap module, the power-on management module, and the lighting module are all connected to the NVMe hard disk or the SATA hard disk or the SAS hard disk through the first U.2 connector 10 and the second U.2 connector 11 respectively.

[0038] In one embodiment, the storage module 1 is an EEPROM chip, the soft start module 2 is an over-current over-voltage protection chip, the voltage monitoring module 3 is an AD conversion chip, and the temperature monitoring module 9 is a temperature sensor chip.

[0039] In one embodiment, the selected CPLD chip is a GD32 series chip, the selected EEPROM chip is a BL24C64A, the selected over-current over-voltage protection chip is an SGM40657, the selected AD conversion chip is an ADS7828, and the selected temperature sensor chip is an NST117.

[0040] In one embodiment, the first CPLD chip 4 further includes a JTAG module for burning program firmware. For example, the JTAG module is a pin used to burn program firmware to the first CPLD chip 4.

[0041] In one embodiment, the length of the multi-functional two-disk bay backplane applied to the rack-mounted server is 150 mm, the width is 67 mm, and the board layer is 12 layers.

[0042] Specifically, the present application is applied to a multi-functional two-disk bay backplane (hereinafter referred to as the two-disk bay backplane) of a rack-mounted server, such as Figure 2 、 3As shown in the figure, the TOP surface of the two-drive bay backplane includes a storage module 1, a soft start module 2, a voltage monitoring module 3, a first CPLD chip 4, a sideband signal connector 5, an NVMe connector 6, a SAS / SATA connector 7, and a power module 8; the BOT surface of the two-drive bay backplane includes a temperature monitoring module 9, a first U.2 connector 10, and a second U.2 connector 11. The two-drive bay backplane is 150 mm long and 67 mm wide, and the board layer is 12 layers, which helps to miniaturize. The design of the small board helps the rack-mounted server to achieve diverse functions in a limited space.

[0043] Among them, as Figure 4 shown, the core of the storage module 1 is an EEPROM chip, which is connected to the first CPLD chip 4 and the main board of the rack-mounted server, and performs data interaction through the I2C bus to view the label information of the two-drive bay backplane and burn the program firmware version information.

[0044] The core of the soft start module 2 is a large current overvoltage protection chip. Its power input terminal is connected to the power module 8 and the first CPLD chip 4, and the power output terminal is connected to the first U.2 connector 10, the second U.2 connector 11, and the first CPLD chip 4. The first CPLD chip 4 controls the hard disk input voltage through its EN signal, protecting the hard disk while realizing the control level of the first CPLD chip 4 and avoiding data loss due to overvoltage or large current.

[0045] The voltage monitoring module 3 is an AD conversion chip, which is used to convert the power supply analog signal into a level I2C signal. By connecting to the sideband signal connector 5, the level I2C signal of the two-drive bay backplane is transmitted to the BMC on the main board end of the rack-mounted server in the I2C bus, and the power-on situation of the two-drive bay backplane is monitored on the BMC (such as through the management interface of the BMC).

[0046] The first CPLD chip 4 is the core control unit of the two-drive bay backplane, including a hard disk hot-swap module, a power-on management module, and a lighting module. It realizes the hard disk hot-swap function, the power-on management function of the two-drive bay backplane, and the lighting control function by receiving the data information of each module. The hot-swap function realizes the hot-swap of NVMe hard disks, SATA hard disks, or SAS hard disks at the same time. The power-on management function realizes the hard disk power-on control, and the lighting control function is used to indicate the status of the hard disk (such as the access status and type of the hard disk), which is convenient for debuggers to perform debugging.

[0047] The sideband signal connector 5 is a low-speed connector. On the one hand, it undertakes the I2C information interaction function between the main board of the rack-mounted server and the two-drive bay backplane. On the other hand, it undertakes the power supply function for each module chip of the two-drive bay backplane (such as providing 3.3V auxiliary power).

[0048] The NVMe connector 6 is a high-speed connector that uses an MCIO cable (MCIO connector) to transmit the X4 differential data signals of two NVMe hard drives, and receives the clock signal (CLK) provided by the clock chip on the motherboard side of the rack-mounted server and the lighting signal (LED_CTRL) provided by the BMC. At the same time, the signal supports the PCIe 5.0 rate.

[0049] The SAS / SATA connector 7 is a high-speed connector that uses a slimSAS cable (slimSAS connector) to transmit the X1 differential data signals of two SATA hard drives or SAS hard drives.

[0050] The power supply module 8 is a 4P power connector that supplies power from the 12V and 5V power supplies on the motherboard side of the rack-mounted server to the hard drives on the two-drive bay backplane for normal operation.

[0051] The temperature monitoring module 9 is a temperature sensor chip that is connected to the BMC on the motherboard side of the rack-mounted server through the sideband signal connector 5. The temperature data is exchanged in the I2C bus, and the temperature near the hard drives on the two-drive bay backplane is monitored on the BMC (such as through the management interface of the BMC). Moreover, the temperature monitoring module 9 is connected to the first CPLD chip 4. When the temperature during hard drive operation reaches the threshold, an alarm signal is sent to the first CPLD chip 4, and the first CPLD chip 4 immediately pulls down all the levels on the two-drive bay backplane to activate the high-temperature power-off protection function to protect the security of the hard drive data.

[0052] Both the first U.2 connector 10 and the second U.2 connector 11 are high-speed connectors that use a 68-pin driver interface U.2 / SFF-8639 and are compatible with both the SATA / SAS interface and the NVMe interface protocol specifications, and can achieve the signal transmission function for 2.5-inch NVMe or SATA / SAS hard drives.

[0053] Operating principle of the two-drive bay backplane:

[0054] As Figure 4 shown, when the two-drive bay backplane actually operates, the hardware signal link is mainly divided into the motherboard side (i.e., the motherboard of the rack-mounted server), the two-drive bay backplane side, and the 2.5-inch hard drive side. The first CPLD chip 4 on the two-drive bay backplane serves as the core controller to implement functions such as EEPROM reading, voltage slow start protection, voltage monitoring, hot plugging function for 2.5-inch NVMe / SATA / SAS hard drives, lighting control, and temperature monitoring.

[0055] The power supply scheme of the two-disk bay backplane is that the main 12V power, main 5V power, and auxiliary 3.3V power (3.3VSB) at the motherboard end are introduced into the two-disk bay backplane by the power connector (power module) and the I2C signal connector (sideband signal connector) respectively to ensure the normal operation of each functional module. For example, the power connector introduces the main 12V power and main 5V power, and the I2C signal connector introduces the auxiliary 3.3V power.

[0056] The design of the hardware circuit of the first CPLD chip 4 on the two-disk bay backplane is the core to realize the versatility of the two-disk bay backplane. The voltage for the normal operation of the first CPLD chip 4 is the auxiliary 3.3V power; a passive device crystal (OSC) is set to provide an 8M clock signal for the first CPLD chip 4; the program firmware for controlling the levels of each chip and the lighting logic is burned into the first CPLD chip 4 through the JTAG module; the CPU at the motherboard end judges whether the two-disk bay backplane is in place according to the BP_PRSNT# signal, with a low level indicating in place and a high level indicating not in place; during the power-on stage, the second CPLD chip at the motherboard end issues the PERST# signal, and the PERST# signal is forwarded to the hard disk through the first CPLD chip 4 on the two-disk bay backplane for power-on reset operation to make it start normal operation. The first CPLD chip 4 processes the signals from each functional module on the two-disk bay backplane and communicates with each module at the motherboard end to achieve the purpose of realizing the versatility of the two-disk bay backplane.

[0057] The EEPROM reading function is that the first CPLD chip 4 transfers the label information and the burned program firmware version information data of the two-disk bay backplane to the EEPROM chip for storage through the I2C bus. Subsequently, the BMC at the motherboard end reads the data stored in the EEPROM chip according to the I2C address of the EEPROM chip and finally displays it on the BMC management interface, which is convenient for the debugging personnel to remotely know the label information and the burned program firmware version information of the two-disk bay backplane.

[0058] The voltage slow start protection function is that the first CPLD chip 4 controls the voltage output by the voltage protection chip to the hard disk through the EN signal and the PG signal. When the voltage input signal of the voltage protection chip is between its input voltage VIN and the maximum threshold voltage OVLO, the voltage protection chip outputs voltage normally. When it is higher than the maximum threshold voltage OVLO, the first CPLD chip 4 pulls down the EN signal to block the voltage output, achieving the function of protecting the solid-state drive and ensuring data security.

[0059] The voltage monitoring function connects the 12V main power, 5V main power, and 3.3V auxiliary power of the two-drive bay backplane to the channels of the AD conversion chip. The AD conversion chip converts the three power analog signals into I2C signals. The BMC reads the I2C signals of the 12V, 5V, and 3.3V auxiliary power according to the I2C address of the AD conversion chip, and finally displays the real-time status of each level on the BMC management interface, facilitating the debug personnel to remotely know all the levels of the two-drive bay backplane.

[0060] In the hot-swap function of the hard disk, the first CPLD chip 4 mainly realizes the parsing, reporting, lighting control and level control of the hard disk presence status. The lighting module includes two LED lights, namely the Activity LED light and the Status (Hotplug) LED light. First, when the hard disk is inserted into the corresponding U.2 connector, the first CPLD chip 4 determines whether a hard disk is connected and the type of the hard disk according to the PRSNT# hard disk presence detection signal and the IFDET# signal, and controls the lighting signal (LED_CTRL) (if both PRSNT# and IFDET# are high level, no hard disk is connected, and the Activity LED light and the Status (Hotplug) LED light are turned off; when PRSNT# is high level and IFDET# is low level, the connected hard disk is an NVMe hard disk, and the Activity LED light and the Status (Hotplug) LED light flash; when both PRSNT# and IFDET# are low level, the connected hard disk is a SATA hard disk or a SAS hard disk). When a SATA hard disk or a SAS hard disk is inserted, the first CPLD chip 4 controls the EN signal of the soft start module 2, inputs a 5V power supply signal to the hard disk, and performs lighting control according to the hard disk status (the Activity LED light indicating hard disk health is always on, and the Status LED light is turned off; otherwise, the Activity LED light is turned off and the Status LED light is always on), and the hard disk can directly perform hot-swap operation when it is healthy. When an NVMe hard disk is inserted, the first CPLD chip 4 controls the EN signal of the soft start module 2, inputs a 12V power supply signal to the hard disk, and delays the release of the PERST# reset signal to make the hard disk enter the working state. The first CPLD chip 4 pulls down the PRSNT# signal and sends it to the BMC and the CPU on the motherboard side, indicating that there is a hard disk present. The CPU on the motherboard side establishes a PCIe link, and the OS allocates resources to the hard disk and loads the driver. The BMC on the motherboard side polls and detects the status of the NVMe hard disk through the I2C bus. If the hard disk status is healthy and correct, the BMC on the motherboard side controls the first CPLD chip 4 through the SMBUS to change the Activity LED light from flashing to always on, and the Status (Hotplug) light from flashing to off. When it is necessary to notify the hard disk of hot-swap, the BMC sends an INT# interrupt signal to the first CPLD chip 4 through the SMBUS. The first CPLD chip 4 sets the PRSNT# signal high and sends it to the CPU. At the same time, the Activity LED light changes from always on to flashing, and the Status (Hotplug) light changes from off to flashing. The OS immediately releases the resource operation on the hard disk. After a delay of 5s, the first CPLD chip 4 controls the EN signal to disconnect the 12V power supply. When the first CPLD chip 4 controls the Activity LED light to change from flashing to off, the hard disk is removed.Finally, the first CPLD chip 4 detects that both PRSNT# and IFDET# become high level, changes the Status (Hotplug) light from flashing to off, and the entire hot-plugging process ends. When a violent hot-plugging operation is performed, the hard disk is violently pulled out. The first CPLD chip 4 detects that both PRSNT# and IFDET# become high level, sets the PRSNT# signal high, and sends it to the CPU to release the hard disk resources. The BMC polls the hard disk status through SMBUS, obtains the hard disk absent status, and then controls the first CPLD chip 4 to turn off the EN signal of the 12V power supply and change the Activity LED light from always on to off, and the Status (Hotplug) light remains off.

[0061] The temperature monitoring function is that the temperature sensor chip monitors the temperature condition near the hard disks on the two-disk bay backplane and saves it. The BMC on the motherboard reads the temperature data stored in the temperature sensor chip according to the I2C address of the temperature sensor chip, and finally displays the temperature condition under the hard disk running state in the BMC management interface. When the temperature is higher than the threshold of the temperature sensor chip, the temperature sensor chip sends an alarm signal (TMP_ALERT#) to the first CPLD chip 4. The first CPLD chip 4 immediately controls the EN enable signals of each 12V and 5V to cut off the power supply to the hard disk and protect the data security.

[0062] According to Figure 4 For the multifunctional two-disk bay backplane applied to the rack-mounted server shown, the selection of core components: Select the GD32 series chip of GigaDevice as the first CPLD chip, select the NST117 chip of Naxin Micro as the temperature sensor chip, select the BL24C64A chip of Shanghai Belling as the EEPROM chip, select the SGM40657 chip of SainSonic as the soft-start protection chip, and select the ADS7828 of TI as the AD conversion chip. Build the implementation environment, and use 2 2.5-inch SATA / SAS / NVMe hard disks respectively for the two-disk bay function test; use the MCIO cable to realize the data interaction between the NVMe disks on the two-disk bay backplane and the motherboard; use the SlimSAS cable to realize the data interaction between the SATA / SAS hard disks and the motherboard; connect the two-disk bay backplane with a rack-mounted server through the power cable and signal cable. After building the implementation environment, perform the following operations, such as Figure 5As shown (some functional modules are not shown, and the rack-mounted server is abbreviated as the server). Among them, the terminal display is connected to the rack-mounted server through the VGA / USB interface to view the status of the hard disk. The debugging notebook is connected through the management network port of the BMC on the motherboard, and the management interface of the BMC (BMC Web UI) is logged in through the IP of the BMC to monitor the temperature, voltage, etc. of the two-disk backplane. BMC_I2C represents the signal for data interaction between the BMC on the motherboard and the two-disk backplane, and the PSU power supply supplies power to the two-disk backplane (POWER).

[0063] Specific implementation steps:

[0064] Step 1: Measure the impedance of the 12V, 5V, and 3.3VSB power supplies of the two-disk backplane, and no short circuit is found;

[0065] Step 2: The server supplies 3.3VSB power to the two-disk backplane, and the user burns the program firmware into the first CPLD chip through the JTAG module;

[0066] Step 3: Log in to the management interface of the BMC of the server (BMC Web UI) to confirm that the label information and the burned program firmware version information of the two-disk backplane are correct;

[0067] Step 4: Turn on the server and supply 12V and 5V power to the two-disk backplane;

[0068] Step 5: On the BMC Web UI management page, confirm whether the 12V, 5V, and 3.3VSB power supplies are normal;

[0069] Step 6: Insert two SATA hard disks or SAS hard disks. The Activity LED is always on, and the Status (Hotplug) LED is off. Enter the lsblk command in the server OS terminal to check whether the hard disks are in place. If they are in place, proceed to the next step;

[0070] Step 7: Forcefully pull out the SATA hard disk or SAS hard disk. Both the Activity LED and the Status (Hotplug) LED are off. Enter the lsblk command in the server OS terminal to check whether the hard disk is successfully pulled out. If the hard disk is not in place, proceed to the next step;

[0071] Step 8: Plug in the SATA hard disk or SAS hard disk. The Activity LED is always on, and the Status (Hotplug) LED is off. Enter the lsblk command in the server OS terminal again to check whether the hard disk is in place. If it is in place, the hot-swap function of the SATA hard disk or SAS hard disk is successfully verified:

[0072] Step 9: Insert two NVMe hard drives and wait for the Activity LED and Status (Hotplug) LED to change from off to blinking, then proceed to the next step;

[0073] Step 10: Wait for the Activity LED to change from blinking to steady on, and wait for the Status (Hotplug) LED to change from blinking to off. Enter the lsblk command in the server OS terminal to check if the hard drive is present. If it is, proceed to the next step;

[0074] Step 11: Send an interrupt signal on the BMC Web UI management page. The Activity LED changes from steady on to blinking. Wait for the Status (Hotplug) LED to change from off to blinking, and wait for 5s. When the Activity LED changes from blinking to off and the Status (Hotplug) LED remains blinking, remove the NVMe hard drive;

[0075] Step 12: Wait for the Status (Hotplug) LED to change from blinking to off, then enter the lsblk command in the server OS terminal to check if the hard drive has been successfully removed. If the hard drive is not present, execute Steps 9 and 10. If it is present, execute Step 13;

[0076] Step 13: Use the mount command in the server OS terminal to mount the hard drive address and write a data file to the hard drive;

[0077] Step 14: Use the md5sum command in the server OS terminal to check if the MD5 value of the written data file is the same as before writing;

[0078] Step 15: Use the FIO stress test tool to perform read and write performance stress tests on the hard drive;

[0079] Step 16: Observe the temperature change of the hard drive on the BMC Web UI management page.

[0080] If the above steps are successfully completed, the multi-functional two-drive bay backplane applied to the rack-mounted server is normal and can be used normally.

[0081] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0082] The above-described embodiments merely represent relatively specific and detailed embodiments of the present application, but should not be construed as limiting the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A multi-functional two-disk bay backplane applied to a rack-mounted server, installed on the rack-mounted server, characterized in that: The multi-functional two-disk bay backplane applied to a rack-mounted server includes a storage module (1), a soft start module (2), a voltage monitoring module (3), a first CPLD chip (4), an NVMe connector (6), a SAS / SATA connector (7), a temperature monitoring module (9), a first U.2 connector (10), and a second U.2 connector (11), wherein: The storage module (1), the voltage monitoring module (3), the NVMe connector (6), the temperature monitoring module (9), the first U.2 connector (10), and the second U.2 connector (11) are all connected to the first CPLD chip (4). The SAS / SATA connector (7) is respectively connected to the first U.2 connector (10) and the second U.2 connector (11). The first U.2 connector (10) and the second U.2 connector (11) are also respectively used to connect an NVMe hard disk, a SATA hard disk, or a SAS hard disk; The power input terminals of the soft start module (2) are respectively connected to a power supply and the first CPLD chip (4), and the power output terminals are respectively connected to the first U.2 connector (10), the second U.2 connector (11), and the first CPLD chip (4); The storage module (1), the voltage monitoring module (3), the temperature monitoring module (9), the NVMe connector (6), and the SAS / SATA connector (7) are also all connected to the motherboard of the rack-mounted server.

2. The multifunctional two-disk bay backplane applied to the rack-mounted server according to claim 1, wherein: The motherboard of the rack-mounted server is provided with a CPU, a BMC, a second CPLD chip, a SATA controller, and a clock chip. The storage module (1), the voltage monitoring module (3), and the temperature monitoring module (9) are all connected to the BMC and the CPU. The NVMe connector (6) is also respectively connected to the clock chip, the BMC, the CPU, and the second CPLD chip. The SAS / SATA connector (7) is also connected to the SATA controller.

3. The multifunctional two-disk bay backplane applied to the rack-mounted server according to claim 2, wherein: The multi-functional two-disk bay backplane applied to a rack-mounted server further includes a sideband signal connector (5) and a power module (8). The storage module (1), the voltage monitoring module (3), and the temperature monitoring module (9) are all connected to the BMC and the CPU through the sideband signal connector (5). The power module (8) is a power connector. The rack-mounted server further includes a PSU power supply. Two ends of the power module (8) are respectively connected to the power input terminal of the soft start module (2) and the PSU power supply. The sideband signal connector (5) is also connected to the PSU power supply. The multi-functional two-disk bay backplane applied to a rack-mounted server is powered by the PSU power supply.

4. The multi-functional two-disk bay backplane applied to a rack-mounted server according to claim 3, wherein: The storage module (1), slow start module (2), voltage monitoring module (3), first CPLD chip (4), sideband signal connector (5), NVMe connector (6), SAS / SATA connector (7) and power supply module (8) are all located on the TOP surface of the multi-functional two-disk bay backplane applied to the rack-mounted server, and the temperature monitoring module (9), first U.2 connector (10) and second U.2 connector (11) are all located on the BOT surface of the multi-functional two-disk bay backplane applied to the rack-mounted server.

5. The multi-functional two-disk bay backplane applied to a rack-mounted server according to claim 3, wherein: The sideband signal connector (5) is a low-speed connector, and the NVMe connector (6), SAS / SATA connector (7), first U.2 connector (10) and second U.2 connector (11) are all high-speed connectors.

6. The multi-functional two-disk bay backplane applied to a rack-mounted server according to claim 1, wherein: The first CPLD chip (4) includes a hard disk hot-swap module, a power-on management module and a lighting module, and the hard disk hot-swap module, the power-on management module and the lighting module are respectively connected to the NVMe hard disk or SATA hard disk or SAS hard disk through the first U.2 connector (10) and the second U.2 connector (11).

7. The multi-functional two-disk bay backplane applied to a rack-mounted server according to claim 1, characterized in that: The storage module (1) is an EEPROM chip, the slow start module (2) is an overcurrent overvoltage protection chip, the voltage monitoring module (3) is an AD conversion chip, and the temperature monitoring module (9) is a temperature sensor chip.

8. The multifunctional two-disk-position backplane applied to a rack-mounted server according to claim 7, characterized in that: The selected type of the CPLD chip is the GD32 series chip, the selected type of the EEPROM chip is BL24C64A, the selected type of the overcurrent overvoltage protection chip is SGM40657, the selected type of the AD conversion chip is ADS7828, and the selected type of the temperature sensor chip is NST117.

9. The multi-functional two-disk bay backplane applied to a rack-mounted server according to claim 1, wherein: The first CPLD chip (4) further includes a JTAG module for burning program firmware.

10. The multifunctional two-disk bay backplane applied to a rack-mounted server according to claim 1, wherein: The length of the multi-functional two-disk bay backplane applied to the rack-mounted server is 150 mm, the width is 67 mm, and the board level is 12 layers.

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