Display panel and display device

Abstract

The utility model discloses a display panel and a display device, the display panel comprises a pixel array, the pixel array comprises a plurality of pixel units, the pixel array is divided into a plurality of display areas, and the display areas comprise a central display area and a plurality of peripheral display areas; each row of pixel units in the central display area is connected with one gate driving connecting line through one gate driving line; each column of pixel units in the central display area is connected with a group of data driving connecting lines through a group of data signal lines; at least two rows of pixel units in the peripheral display area are connected with one gate driving connecting line through one gate driving line; and at least two columns of pixel units in the peripheral display area are connected with a group of data driving connecting lines through a group of data signal lines. Therefore, the number of the grid driving connecting lines and the number of the data driving connecting lines are reduced, the charging speed is increased, the transmission bandwidth between the display device and the display panel and the amount of data needing to be transmitted are reduced, and the power consumption of data transmission is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of display panels, and in particular to a display panel and a display device. Background Art

[0002] In recent years, with the increasing immersion of MR (mixed reality) or VR (virtual reality) devices, demands for a wide field of view, high resolution, high refresh rate, and high PPI (pixel per inch) have emerged. This has led to increasingly stringent requirements for chip computing power and data transmission speeds. However, head-mounted mobile XR devices have extremely stringent requirements for power consumption and heat generation, which further limits the computational effort required to render the displayed images. Therefore, achieving higher-quality images without consuming excessive power or bandwidth has become an urgent challenge.

[0003] To address these technical challenges, foveated rendering technology has emerged. Foveated rendering allocates computing resources and accelerates image rendering based on the human visual system's perceptual model. Based on the human eye's attention model, this technology renders areas with significant features at higher quality and less significant areas at lower quality. This reduces the computational effort required for rendering and the amount of data required to be transmitted without compromising overall perception.

[0004] In recent years, technical solutions for foveated rendering have been continuously proposed. For example, patent "CN 109741298A: An Image Fusion Method and VR Device" proposes rendering two images at two different resolutions and then fusing them. In the display driver system, this solution requires caching the high-resolution image and then upscaling the low-resolution image. This not only requires additional computation and cache space, but also increases image processing latency, limits refresh rate increases, reduces user immersion, and can easily cause dizziness.

[0005] Patent "PCT / CN2019 / 080728" proposes dividing the image into a nine-square grid, rendering different sampling areas at different resolutions, and finally amplifying the image in blocks for display on a pixel array. Because the image is divided into different sampling areas, it requires more complex image amplification logic and is prone to timing issues between data transmission and image display.

[0006] In summary, although the use of foveated rendering technology has solved the above problems to a certain extent, there are still technical problems such as the transmission bandwidth between the processor of the display device and the display panel and the large amount of data to be transmitted, resulting in high power consumption. Utility Model Content

[0007] In view of the above-mentioned shortcomings, the technical problem to be solved by the present invention is: to provide a display panel and a display device, which reduce the number of gate drive connection lines and data drive connection lines, and reduce the number of connection lines required for the display panel and other external devices. Since multiple pixel circuits can be charged at the same time, the time required for charging is reduced and the charging speed is accelerated; and the transmission bandwidth between the processor of the display device and the display panel and the amount of data to be transmitted are reduced, thereby reducing the power consumption caused by data transmission.

[0008] In order to solve the above technical problems, the technical solution of the utility model is:

[0009] A display panel comprises a gate drive controller, a data driver and a pixel array; the pixel array comprises pixel units arranged in an array, each row of the pixel units is connected to a gate drive line, and each column of the pixel units is connected to a group of data signal lines; the gate drive controller is connected to the gate drive line via a gate drive connection line, and the data driver is connected to the data line via a data drive connection line; the pixel array is divided into multiple display areas, the display area comprising a central display area and multiple peripheral display areas arranged outside the central display area; wherein each row of the pixel units in the central display area is connected to a gate drive connection line via a gate drive line; each column of the pixel units in the central display area is connected to a group of data drive connection lines via a group of data signal lines; at least two rows of the pixel units in the peripheral display area are respectively connected to a gate drive connection line via a gate drive line; and / or at least two columns of the pixel units in the peripheral display area are respectively connected to a group of data drive connection lines via a group of data signal lines.

[0010] Preferably, each pixel unit in the pixel array includes a plurality of sub-pixels, and the sub-pixels in each row of the pixel units are connected to the same gate drive line; and each sub-pixel is connected to one of the data signal lines in a one-to-one correspondence.

[0011] Preferably, the central display area and the plurality of peripheral display areas are arranged in rows and columns.

[0012] Preferably, in the plurality of peripheral display areas arranged in the same row as the central display area, each row of pixel units is connected to one gate drive connection line via one gate drive line.

[0013] Preferably, in a plurality of the peripheral display areas that are not arranged in the same row as the central display area, one gate driving connection line is connected to at least two rows of pixel units through at least two gate driving lines.

[0014] Preferably, the number of gate drive lines connected to a gate drive connection line in the peripheral display area arranged close to the row where the central display area is located is less than the number of gate drive lines connected to a gate drive connection line in the peripheral display area arranged away from the row where the central display area is located.

[0015] Preferably, in the plurality of peripheral display areas arranged in the same column as the central display area, each column of pixel units is connected to a group of data drive connection lines via a group of data signal lines.

[0016] Preferably, in the plurality of peripheral display areas that are not arranged in the same column as the central display area, one group of data driving connection lines is connected to at least two columns of pixel units through at least two groups of data signal lines.

[0017] Preferably, the number of data signal lines connected by a group of data drive connection lines in the peripheral display area arranged close to the column where the central display area is located is less than the number of data signal lines connected by a group of data drive connection lines in the peripheral display area arranged away from the column where the central display area is located.

[0018] A display device includes the above-mentioned display panel.

[0019] After adopting the above technical solution, the beneficial effects of the utility model are:

[0020] Due to the display panel and display device of the present invention, the display panel includes a gate drive controller, a data driver and a pixel array; the pixel array includes pixel units arranged in an array, each row of pixel units is connected to a gate drive line, and each column of pixel units is connected to a group of data signal lines; the gate drive controller is connected to the gate drive line through a gate drive connection line, and the data driver is connected to the data line through a data drive connection line; the pixel array is divided into multiple display areas, and the display area includes a central display area and multiple peripheral display areas arranged outside the central display area; wherein each row of pixel units in the central display area is connected to a gate drive connection line through a gate drive line; each column of pixel units in the central display area is connected to a group of data drive connection lines through a group of data signal lines; wherein at least two rows of pixel units in the peripheral display area are respectively connected to a gate drive connection line through a gate drive line; and / or, at least two columns of pixel units in the peripheral display area are respectively connected to a group of data drive connection lines through a group of data signal lines. Because at least two pixel units in the peripheral display area share a gate drive connection line and / or a group of data drive connection lines, the number of gate drive connection lines and data drive connection lines is greatly reduced, thereby reducing the number of connection lines required between the display panel and other external devices; because multiple pixel circuits can be charged simultaneously, the time required for charging is reduced and the charging speed is accelerated; and the transmission bandwidth between the display device and the display panel and the amount of data to be transmitted are reduced, thereby reducing the power consumption caused by data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a principle block diagram of the display device in the utility model;

[0022] Figure 2 This is a schematic diagram of the data signal line drive control in the present utility model;

[0023] Figure 3 Schematic diagram of data writing partitions under the driving control of gate drive lines and data signal lines;

[0024] Figure 4 It is a diagram of the gate drive controller and gate signal;

[0025] Figure 5 This is a schematic diagram of data writing grouping under the gate drive control circuit;

[0026] Figure 6 This is a schematic diagram of the area division of the 3552*3840 pixel array;

[0027] Figure 7 It is a schematic diagram of pixel array driving;

[0028] In the figure: 1-display panel, 2-pixel array, 20-central display area, 21-peripheral display area, 22-pixel unit, 220-sub-pixel. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] It should be noted that, in the description of the present invention, terms such as "up", "down", "left", "right", "inside", and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. This is only for the convenience of description and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.

[0031] Furthermore, it should be noted that, in the description of this utility model, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on specific circumstances.

[0032] like Figure 1 As shown, according to an embodiment of the first aspect of the present utility model, the display panel 1 includes a control unit, a gate drive controller, a data driver, a pixel array 2 and a data buffer, the control unit is electrically connected to the gate drive controller and the data driver respectively, and the data driver is connected to the data buffer.

[0033] The pixel array 2 includes pixel units 22 arranged in an array, each row of pixel units 22 is connected to a gate drive line, and each column of pixel units 22 is connected to a group of data signal lines; the gate drive controller is connected to the gate drive line through the gate drive connection line, and the data driver is connected to the data signal line through the data drive connection line.

[0034] It should be noted that: each pixel unit 22 includes a plurality of sub-pixels 220, and the sub-pixels 220 in each row of pixel units 22 are connected to the same gate drive line; each sub-pixel 220 is connected to a data signal line in a one-to-one correspondence. Figure 7, R is a red sub-pixel 220, G is a green sub-pixel 220, B is a blue sub-pixel 220, and three adjacent RGB sub-pixels 220 in each row form a pixel unit 22. Each sub-pixel 220 includes a gate drive line and a data signal line. The gate drive lines of the three RGB sub-pixels 220 are all connected to the gate drive line GL of the row. For example Figure 3 The gate drive lines of all sub-pixels 220 of all pixel units 22 in the first row are connected to the gate drive line G1; the data signal lines of the three RGB sub-pixels 220 are respectively connected to the data signal lines of their columns, for example, the data signal line of R is connected to the data signal line DL1 of its column, the data signal line of G is connected to the data signal line DL2 of its column, the data signal line of B is connected to the data signal line DL3 of its column, and so on. In addition, Figure 7 The three data signal lines DL1, DL2 and DL3 constitute Figure 3 A group of data signal lines D1.

[0035] like Figure 1 As shown, the pixel array 2 in the present invention is divided into a plurality of display areas, and the display area includes a central display area 20 and a plurality of peripheral display areas 21 arranged outside the central display area 20 .

[0036] Each row of pixel units 22 in the central display area 20 is connected to a gate drive connection line via a gate drive line; each column of pixel units 22 in the central display area 20 is connected to a group of data drive connection lines via a group of data signal lines; see Figure 3 , G9, G10, G11 and G12 are gate drive lines in the central display area, B4, B5, B6 and B7 are corresponding gate drive connection lines, D9, D10, D11 and D12 are data signal line groups in the central display area, A4, A5, A6 and A7 are corresponding data drive connection lines.

[0037] At least two rows of pixel units 22 in the peripheral display area 21 are connected to a gate drive connection line through a gate drive line; and / or at least two columns of pixel units 22 in the peripheral display area 21 are connected to a group of data drive connection lines through a group of data signal lines. Figure 3, G1, G2, G3, G4, G5, G6, G7, G8, G13, G14, G15, G16, G17, G18, G19 and G20 are gate drive lines in the peripheral display area, B1, B2, B3, B8, B9 and B10 are corresponding gate drive connection lines, D1, D2, D3, D4, D5, D6, D7, D8, D13, D14, D15, D16, D17, D18, D19 and D20 are data signal line groups in the peripheral display area, A1, A2, A3, A8, A9 and A10 are corresponding data drive connection lines.

[0038] Specifically, four gate drive lines in the peripheral display area 21 are connected to one gate drive connection line, for example: G1, G2, G3 and G4 are bound and connected and then connected to the gate drive controller through B1, G17, G18, G19 and G20 are bound and connected and then connected to the gate drive controller through B10; two gate drive lines in the peripheral display area 21 can also be connected to one gate drive connection line, for example: G5 and G6 are bound and connected and then connected to the gate drive controller through B2, G7 and G8 are bound and connected and then connected to the gate drive controller through B3, G13 and G14 are bound and connected and then connected to the gate drive controller through B8, and G15 and G16 are bound and connected and then connected to the gate drive controller through B9.

[0039] Specifically, four groups of data signal lines in the peripheral display area 21 are connected to one group of data driver connection lines, for example: D1, D2, D3 and D4 are bound and connected and then connected to the data driver through A1, and D17, D18, D19 and D20 are bound and connected and then connected to the data driver through A10; two groups of data signal lines in the peripheral display area 21 can also be connected to one group of data driver connection lines, for example: D5 and D6 are bound and connected and then connected to the data driver through A2, D7 and D8 are bound and connected and then connected to the data driver through A3, D13 and D14 are bound and connected and then connected to the data driver through A8, and D15 and D16 are bound and connected and then connected to the data driver through A9.

[0040] like Figure 2 、 Figure 3 and Figure 5 As shown, the display panel of the present invention has a central display area divided by its pixel array as the interactive area of ​​area C and area 3, referred to as area C3 for short. Similarly, the peripheral display areas divided by the pixel array include area A1, area A2, area A3, area A4, area A5, area B1, area B2, area B3, area B4, area B5, area C1, area C2, area C4, area C5, area D1, area D2, area D3, area D4, area D5, area E1, area E2, area E3, area E4 and area E5.

[0041] In region C3, gate drive lines are connected one-to-one with gate drive connection lines, meaning each pixel value drives one pixel unit 22. Region C3 is a high-resolution region. Furthermore, the central display area is located in the center of the pixel array, and selecting the central area as the high-resolution region complies with foveated rendering technology.

[0042] Because at least two gate drive lines in each peripheral display area are bound together and then connected to a gate drive connection line, and at least one group of data signal lines are bound together and then connected to a group of data drive connection lines, the number of gate drive connection lines and data drive connection lines is greatly reduced, thereby reducing the number of connection lines required between the display panel and other external devices. Because multiple pixel circuits can be charged simultaneously, the time required for charging is reduced and the charging speed is accelerated. In addition, the transmission bandwidth between the processor of the display device and the display panel and the amount of data to be transmitted are reduced, thereby reducing the power consumption caused by data transmission.

[0043] like Figure 3 and Figure 6 As shown, in some embodiments of the present invention, the central display area and the plurality of peripheral display areas are arranged in rows and columns.

[0044] In some embodiments of the present invention, in a plurality of peripheral display areas arranged in the same row as the central display area, each row of pixel units 22 is connected to a gate drive connection line via a gate drive line. Figure 3 Middle: The gate drive line G9 of areas C1, C2, C4 and C5 arranged in the same row as area C3 is connected to the gate drive connection line B4, the gate drive line G10 is connected to the gate drive connection line B5, the gate drive line G11 is connected to the gate drive connection line B6, and the gate drive line G12 is connected to the gate drive connection line B7.

[0045] In a plurality of peripheral display areas arranged in a different row from the central display area, one gate drive connection line is connected to at least two rows of pixel units 22 via at least two gate drive lines. Figure 3 Middle: For example, area a1, area b2, area d4 and area e5 are arranged in different rows from area c3. In area a1, G1, G2, G3 and G4 are bound and connected and then connected to the gate drive connection line B1, which reduces three gate drive connection lines compared with the central display area; in area b2, G5 and G6 are bound and connected and then connected to the gate drive connection line B2, which reduces one gate drive connection line compared with the central display area; in area d4, G15 and G16 are bound and connected and then connected to the gate drive connection line B9, which reduces one gate drive connection line compared with the central display area; in area e5, G17, G18, G19 and G20 are bound and connected and then connected to the gate drive connection line B10, which reduces three gate drive connection lines compared with the central display area.

[0046] In some embodiments of the present invention, the number of gate drive lines connected by a gate drive connection line in the peripheral display area arranged near the row where the central display area is located is smaller than the number of gate drive lines connected by a gate drive connection line in the peripheral display area arranged far from the row where the central display area is located. Figure 3 Take the b2 area and the a1 area shown in the figure as an example: the b2 area is closer to the central display area c3, the two gate driving lines in the b2 area share one gate driving connection line, and the four gate driving lines in the a1 area share one gate driving connection line.

[0047] The number of data signal lines connected by a group of data drive connection lines in the peripheral display area arranged near the column where the central display area is located is smaller than the number of data signal lines connected by a group of data drive connection lines in the peripheral display area arranged far from the column where the central display area is located. Figure 3 Take the b2 area and a1 area shown in the figure as an example: the b2 area is closer to the central display area c3, the two groups of data signal lines in the b2 area share a group of data drive connection lines, and the four groups of data signal lines in the a1 area share a group of data drive connection lines.

[0048] In some embodiments of the present invention, in a plurality of peripheral display areas arranged in the same column as the central display area, each column of pixel units 22 is connected to a group of data drive connection lines via a group of data signal lines. Figure 3 Middle: The data signal line group D9 of areas a3, b3, d3 and e3 arranged in the same column as area c3 is connected to A4, the data signal line group D10 is connected to A5, the data signal line group D11 is connected to A6, and the data signal line group D12 is connected to A7.

[0049] In a plurality of peripheral display areas that are not arranged in the same column as the central display area, a group of data drive connection lines is connected to at least two columns of pixel units 22 through at least two groups of data signal lines. Figure 3 Middle: In area a5, D1, D2, D3, and D4 are tied together before connecting to A1, reducing the number of data-driven connection lines by three compared to the center display area c3. In area d2, D5 and D6 are tied together before connecting to A2, reducing the number of data-driven connection lines by one compared to the center display area. In area b4, D15 and D16 are tied together before connecting to A9, reducing the number of data-driven connection lines by one compared to the center display area. In area a5, D17, D18, D19, and D20 are tied together before connecting to A10, reducing the number of data-driven connection lines by three compared to the center display area.

[0050] For a clearer understanding, the following example illustrates:

[0051] like Figure 4As shown, it is assumed that the pixel array includes 20 gate drive lines. At this time, the 20 gate drive lines are respectively arranged in area a, area b, area c, area d and area e. The pixel values ​​of one row in area a and area e drive the circuits corresponding to the four rows of pixels in the pixel array; the pixel values ​​of one row in area b and area d drive the circuits corresponding to the two rows of pixels in the pixel array; and the pixel values ​​of one row in area c drive the circuits corresponding to the one row of pixels in the pixel array. It can be seen that in area a, the four gate drive lines are bound and connected and then connected to the gate drive connection line B1. In this way, the gate drive connection line B1 can simultaneously drive the four gate drive lines G1, G2, G3 and G4, so that they are charged at the same time. Similarly, in area b, the two gate drive lines G5 and G6 are bound and connected and then connected to the gate drive connection line B2. In this way, the gate drive connection line B2 can simultaneously drive the two gate drive lines G5 and G6, so that they are charged at the same time. The same treatment is applied to areas c, d and e. Figure 4 In the example circuit, the number of external input gate drive signals is reduced from 20 to 10, which not only reduces the difficulty of connecting the display panel and the display drive system, but also speeds up the charging speed.

[0052] like Figure 5 As shown, when gate drive line B1 is turned on, Data1 is simultaneously written into the four pixels corresponding to Gate1, Gate2, Gate3, and Gate4. When gate drive line B2 is turned on, Data1 is simultaneously written into the two pixels corresponding to Gate5 and Gate6. When gate drive line B3 is turned on, Data1 is simultaneously written into the two pixels corresponding to Gate7 and Gate8. When gate drive line B4 is turned on, Data1 is simultaneously written into the one pixel corresponding to Gate9.

[0053] like Figure 2 As shown, assume that the pixel array includes 20 gate drive lines and 20 groups of data signal lines, with the 20 groups of data signal lines divided into five regions. In regions 1 and 5, a group of data signal lines simultaneously writes to the circuits corresponding to four horizontal pixels; in regions 2 and 4, a group of data signal lines simultaneously writes to the circuits corresponding to two horizontal pixels; and in region 3, a group of data signal lines simultaneously writes to the circuit corresponding to one horizontal pixel. Therefore, in region 1, the four groups of data drive lines D1, D2, D3, and D4 can be bundled and connected together and then connected to A1; the two groups of data signal lines D5 and D6 in region 2 can be bundled and connected together and then connected to A2, and the two groups of data signal lines D7 and D8 can be bundled and connected together and then connected to A3. At this time, in region 1, the data buffer and the data buffer corresponding to A1 simultaneously write the pixel values ​​through A1 to the circuits corresponding to the pixels corresponding to the four groups of data signal lines D1, D2, D3, and D4. Similarly, in areas 2-5, A2-A10 also write the values ​​in the corresponding registers into D5-D20 respectively.

[0054] like Figure 3 As shown, assuming that the pixel array includes 20 gate drive lines and 20 groups of data signal lines, the gate drive line and data signal line control are applied simultaneously, it can be seen that it is divided into 25 areas. In areas a1, a5, e1 and e5, the data drive connection line A1 simultaneously drives the D1, D2, D3 and D4 data signal line groups, and the gate drive connection line B1 simultaneously drives the G1, G2, G3 and G4 gate drive lines. Therefore, in this partition, the pixel value corresponding to A1 in the data buffer will be written into the circuits corresponding to the 16 pixels in the pixel array at the same time. Similarly, in the four areas of a2, a4, e2 and e4, a pixel value in the data buffer is simultaneously written into the circuits corresponding to 8 pixels (2 horizontally and 4 vertically) on the pixel array; in the four areas of b1, b5, d1 and d5, a pixel value in the data buffer is simultaneously written into the circuits corresponding to 8 pixels (4 horizontally and 2 vertically) on the pixel array; in the two areas of c1 and c5, a pixel value in the data buffer is simultaneously written into the circuits corresponding to 4 pixels (4 horizontally and 1 vertically) on the pixel array; in the two areas of a3 and e3, a pixel value in the data buffer is simultaneously written into the circuits corresponding to 4 pixels ( In the four areas of area B2, area B4, area D2 and area D4, a pixel value in the data buffer is simultaneously written into the circuit corresponding to the four pixels on the pixel array (2 horizontally multiplied by 2 vertically); in the two areas of area B3 and area D3, a pixel value in the data buffer is simultaneously written into the circuit corresponding to the two pixels on the pixel array (1 horizontally multiplied by 2 vertically); in the two areas of area C2 and area C4, a pixel value in the data buffer is simultaneously written into the circuit corresponding to the two pixels on the pixel array (2 horizontally multiplied by 1 vertically); in the area C3, a pixel value in the data buffer is simultaneously written into the circuit corresponding to one pixel on the pixel array.

[0055] like Figure 6 As shown in the figure, assuming that the pixel array includes 3840*3552 pixels, has 3840 gate drive lines, and has 3552 groups of data signal lines, the pixel array can be divided into 25 areas. Specifically, the central display area has 1890 gate drive lines, the peripheral display area above the central display area has 655 gate drive lines, and the peripheral display area below the central display area also has 655 gate drive lines; at the same time, the peripheral display area above the central display area has 320 gate drive lines, and the peripheral display area below the central display area has 320 gate drive lines.

[0056] The following table shows the number of gate drive connection lines and data drive connection lines required for the pixel array of the present invention and the pixel array of the prior art:

[0057]

[0058] like Figure 6 As shown, the standard 1x display area includes 1x1, 1x2, and 1x4; the 2x display area includes 2x1, 2x2, and 2x4; and the 4x display area includes 4x1, 4x2, and 4x4.

[0059] By comparing the above table, it can be directly concluded that the pixel array of the display panel in the present invention greatly reduces the number of gate drive connection lines and data drive connection lines, thereby reducing the number of connection lines required between the display panel and other external devices; because multiple pixel circuits can be charged simultaneously, the time required for charging is reduced and the charging speed is accelerated; and the transmission bandwidth between the processor of the display device and the display panel and the amount of data to be transmitted are reduced, thereby reducing the power consumption caused by data transmission.

[0060] like Figure 1 As shown, according to an embodiment of the second aspect of the present invention, the display device includes the display panel of the first aspect of the present invention.

[0061] The display device of the present invention further includes a processor, which includes a graphics renderer and a data transmission device, and the data transmission device is electrically connected to the data buffer. Since the display device includes the display panel of the first aspect of the present invention, it has the following advantages:

[0062] Reduced power consumption: The display panel is optimized for fixed-foveation rendering, which reduces the transmission bandwidth between the processor and the display panel and the amount of data that needs to be transmitted, thereby reducing the power consumption caused by data transmission.

[0063] Faster charging: By partitioning the pixel array and charging one or more pixel circuits within a partition simultaneously, the time required for charging is reduced.

[0064] Reduce the number of connection lines: By partitioning the pixel array, pixels within a partition only require one drive signal, thereby reducing the number of connection lines required between the display panel and other external devices.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications made within the spirit and principles of the present invention, improvements to the same display panel and display device, etc., should be included in the scope of protection of the present invention.

Claims

1. A display panel comprising a gate drive controller, a data driver, and a pixel array; The pixel array includes pixel units arranged in an array, each row of the pixel units is connected to a gate drive line, and each column of the pixel units is connected to a group of data signal lines; the gate drive controller is connected to the gate drive lines via gate drive connection lines, and the data driver is connected to the data signal lines via data drive connection lines; It is characterized in that The pixel array is divided into a plurality of display areas, wherein the display area includes a central display area and a plurality of peripheral display areas arranged outside the central display area; Wherein, each row of pixel units in the central display area is connected to one gate drive connection line via one gate drive line; each column of pixel units in the central display area is connected to one group of data drive connection lines via one group of data signal lines; At least two rows of pixel units in the peripheral display area are respectively connected to one gate drive connection line through one gate drive line; and / or, at least two columns of pixel units in the peripheral display area are respectively connected to one group of data drive connection lines through one group of data signal lines.

2. The display panel according to claim 1, wherein: Each pixel unit in the pixel array includes a plurality of sub-pixels, and the sub-pixels in each row of the pixel units are connected to the same gate drive line; and each sub-pixel is connected to one of the data signal lines in a one-to-one correspondence.

3. The display panel according to claim 2, wherein: The central display area and the plurality of peripheral display areas are arranged in rows and columns.

4. The display panel according to claim 3, wherein: In the plurality of peripheral display areas arranged in the same row as the central display area, each row of pixel units is connected to one gate driving connection line via one gate driving line.

5. The display panel according to claim 4, wherein: In the plurality of peripheral display areas that are not arranged in the same row as the central display area, one gate driving connection line is connected to at least two rows of pixel units through at least two gate driving lines.

6. The display panel according to claim 5, wherein: The number of gate drive lines connected to one gate drive connection line in the peripheral display area arranged close to the row where the central display area is located is less than the number of gate drive lines connected to one gate drive connection line in the peripheral display area arranged away from the row where the central display area is located.

7. The display panel according to claim 3, wherein: In the plurality of peripheral display areas arranged in the same column as the central display area, each column of pixel units is connected to a group of data driving connection lines via a group of data signal lines.

8. The display panel according to claim 7, wherein: In the plurality of peripheral display areas that are not arranged in the same column as the central display area, a group of the data driving connection lines is connected to at least two columns of the pixel units through at least two groups of the data signal lines.

9. The display panel according to claim 8, wherein: The number of data signal lines connected by a group of data drive connection lines in the peripheral display area arranged close to the column where the central display area is located is less than the number of data signal lines connected by a group of data drive connection lines in the peripheral display area arranged away from the column where the central display area is located.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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