Semiconductor structure

By adopting multiple patterning processes and self-alignment processes in semiconductor structures, combined with the design of hard mask layers and inner spacer layers, the integration problem of source/drain structures in multi-gate devices is solved, the quality of finished products and gate control capabilities are improved, and the process complexity is reduced.

CN223428807UActive Publication Date: 2025-10-10TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
CN202422725613.3
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Priority Date
2023-12-26
Filing Date
2024-11-08
Publication Date
2025-10-10
Estimated Expiration
2034-11-08

AI Technical Summary

Technical Problem

In the prior art, it is difficult to effectively integrate and form high-quality source/drain structures when manufacturing multi-gate devices, resulting in increased process complexity and reduced product quality.

Method used

A multiple patterning process combined with photolithography and self-alignment processes is used to form nanostructures and gate structures. The formation of the source/drain structure is controlled through the design of a hard mask layer and an inner spacer layer, including the combined use of an inner spacer layer and a hard mask layer to improve the formation process and quality of the source/drain structure.

Benefits of technology

By improving the formation process of the source/drain structure, the process complexity is reduced, the finished product quality and reliability of the semiconductor structure are improved, the gate control capability is enhanced, and the short channel effect is reduced.

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Abstract

Semiconductor structures are provided herein. The semiconductor structure includes a plurality of nanostructures formed on the substrate along a first direction, and a gate structure formed on the nanostructures along a second direction. The semiconductor structure includes a source / drain structure adjacent to the gate structure, and a plurality of inner spacer layers between the gate structure and the source / drain structure. The semiconductor structure includes a hard mask layer formed on the inner spacer layer, and an upper surface of the hard mask layer is higher than an upper surface of the source / drain structure.
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