USB transmission rate increasing circuit

Abstract

The utility model relates to a USB (universal serial bus) transmission rate increasing circuit, belongs to the technical field of USB data transmission, and solves the problem of low transmission efficiency of a large number of file data generated by an infrared handheld thermal imager in the prior art. The USB transmission rate increasing circuit comprises a bus switching circuit and a memory. The bus switching circuit comprises a data selection circuit and a microcontroller; the data selection circuit comprises a low-speed external data interface, a high-speed external data interface and a synthetic data interface, and the synthetic data interface is connected with the microcontroller; the low-speed or high-speed external data interface is connected with the synthetic data interface; and the microcontroller is electrically connected with the memory. On the basis of keeping the external transmission USB2.0 interface of the original infrared handheld thermal imager, the transmission effect of externally exporting data at the USB3.0 speed is realized by adjusting the local circuit.

Description

TECHNICAL FIELD

[0001] The utility model relates to USB data transmission technical field especially relates to a USB transmission rate promotion circuit. BACKGROUND

[0002] In many fields such as security monitoring, industrial detection, power inspection and building detection, handheld thermal imagers play an indispensable role. Its photographing and video recording functions can accurately record the thermal imaging state of the equipment operation, providing key data support for staff to troubleshoot and analyze equipment problems. For example, in power inspection, the thermal image taken by the handheld thermal imager can quickly find the overheated parts in the line and prevent faults from occurring in advance.

[0003] However, the current handheld thermal imager has obvious shortcomings in data storage and transmission. In daily use, a large number of files generated are stored in the instrument. When these data need to be exported, due to the use of USB2.0 interface in conventional embedded chips, the transmission speed is slow, and it takes a long time to export a large amount of data. In the industrial production detection scene, detection personnel urgently need to export thermal image data quickly for analysis, and the long export time will seriously affect the production efficiency and even delay the entire production progress.

[0004] USB3.0 has significant performance improvement compared to USB2.0. It has higher data transmission rate (theoretically, the transmission speed of USB3.0 can reach 5Gbps, while the transmission speed of USB2.0 is only 480Mbps), stronger power supply capability and better compatibility.

[0005] Currently, there are mainly two common solutions to the data transmission problem of thermal imagers on the market. One is to directly replace the chip with a USB3.0 interface. Although this solution can significantly improve the data transmission speed and effectively shorten the export time, it has many drawbacks. On the one hand, replacing the chip will significantly increase the product cost, leading to an increase in product price and reducing market competitiveness. On the other hand, the compatibility of the new chip with the original embedded system cannot be guaranteed, which may cause various unstable factors and increase the difficulty of product development and maintenance. The other is to use wireless transmission methods such as Wi-Fi, Bluetooth, etc. to transmit data. Although wireless transmission is more convenient to use, it has obvious shortcomings in actual application. The transmission distance will be limited, and the signal will weaken or even be interrupted beyond a certain range. At the same time, wireless signals are easily disturbed, and in a complex electromagnetic environment, the stability of transmission cannot be guaranteed. Moreover, when transmitting a large amount of data, the transmission speed cannot meet the demand of fast export. INVENTION CONTENTS

[0006] In view of the above analysis, the utility model aims at providing a USB transmission rate promotion circuit to solve the low transmission efficiency of a large number of file data generated by the existing infrared handheld thermal imager.

[0007] The utility model discloses a purpose mainly is realized through following technical schemes:

[0008] A USB transmission rate promotion circuit, including bus switching circuit and memory, bus switching circuit includes data selection circuit and microcontroller, data selection circuit has low speed, high speed external data interface and synthetic data interface, and synthetic data interface is connected microcontroller, low speed or high speed external data interface is connected with synthetic data interface, and microcontroller is connected with memory electricity.

[0009] Further, data selection circuit includes USB switch chip, USB switch chip includes low speed, high speed external data interface and synthetic data interface, and low speed external data interface connects external USB2.0 data interface, high speed external data interface connects external USB3.0 data interface, and USB switch chip still includes data selection control pin, and data selection control pin controls the communication of the synthetic data interface of USB switch chip and low speed or high speed external data interface.

[0010] Further, microcontroller includes USB data interface and EMMC bus interface, EMMC bus interface connects memory, and USB data interface connects the synthetic data interface of USB switch chip.

[0011] Further, the USB transmission rate promotion circuit further includes matching resistance, and the matching resistance is connected between the 8-bit data interface of microcontroller EMMC bus interface and the data IO port of memory.

[0012] Further, the USB transmission rate promotion circuit further includes power control circuit, and the power control circuit includes first power conversion circuit and second power conversion circuit, the power input end of first power conversion circuit is connected with external power supply, and the power output end of first power conversion circuit is connected with the power input end of second power conversion circuit, and the power output end of second power conversion circuit is connected with microcontroller electricity.

[0013] Further, the first power conversion circuit further includes power control pin, and the power output end of first power conversion circuit is further connected with USB switch chip, microcontroller and memory electricity, and the power control pin can control the start or shutdown of first power conversion circuit.

[0014] Further, the microcontroller further includes a pair of differential clock interface, and the differential clock interface is connected with external passive crystal oscillator input and output clock.

[0015] Further, the USB switch chip model is HD3SS6126RUAR; the 31 and 32 pins of the HD3SS6126RUAR are connected with the positive and negative ends of the USB2.0 data interface respectively; the 23 and 22 pins of the HD3SS6126RUAR are connected with the receiving positive and receiving negative pins of the external USB3.0 data interface respectively; the 25 and 24 pins of the HD3SS6126RUAR are connected with the sending positive and sending negative pins of the external USB3.0 data interface respectively; the 33 and 34 pins of the HD3SS6126RUAR are connected with the D+ and D- pins of the external USB3.0 data interface respectively; the 6 and 9 pins of the HD3SS6126RUAR are data selection control pins, and are connected with one end of a pull-down resistor R2, and receive a data selection control signal, and the other end of the pull-down resistor R2 is grounded; the 8, 7, 11, 12, 15 and 16 pins of the HD3SS6126RUAR are synthetic data interfaces.

[0016] Further, the memory model is FSEIASLD-128G.

[0017] Further, the microcontroller model is CH565; the 67 and 68 pins of the CH565 are connected with the clock output pin and the input pin of a 30M passive crystal oscillator respectively; the 31 and 29 pins of the CH565 are connected with the M6 and M5 pins of the FSEIASLD-128G respectively; the EMMC bus special data interface of the CH565 is connected with the EMMC data interface of the FSEIASLD-128G.

[0018] Compared with the prior art, the present application can realize at least one of the following beneficial effects:

[0019] 1. The USB transmission rate improving circuit increases the bus switching circuit including the data selection circuit and the microcontroller on the basis of the original USB2.0 interface system; the data selection circuit includes the low-speed and high-speed external data interfaces and the synthetic data interface, and the synthetic data interface is connected with the microcontroller; when the low-speed or high-speed external data interface receives data from the outside, the microcontroller sends the data to the memory for storage; when it is necessary to send data to the outside, the microcontroller reads the data from the memory and sends the data to the synthetic data interface of the data selection circuit, and the data selection circuit sends the data to the outside through the high-speed external data interface. On the basis of maintaining the original USB2.0 interface of the infrared handheld thermal imager, the transmission effect of data exported to the outside at the USB3.0 speed is realized by adjusting the local circuit, the problem of slow data transmission is effectively solved, the original embedded chip is not changed, the cost is saved, and the compatibility with the original infrared handheld thermal imager is maintained.

[0020] 2, The USB transmission rate improvement circuit provided by the application comprises a first power conversion circuit, the first power conversion circuit comprises a power control pin, a power output end of the first power conversion circuit is electrically connected with a second power conversion circuit, a USB switch chip, a microcontroller and a memory, and the power control pin can control the first power conversion circuit to be turned on or turned off.

[0021] The above technical solutions can be combined with each other to realize more preferred combination solutions. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings are only used for the purpose of illustrating specific embodiments and are not considered as limiting the application, and the same reference signs represent the same components throughout the drawings.

[0023] Figure 1 The system block diagram of the USB transmission rate improvement circuit of the application;

[0024] Figure 2 The power control circuit principle diagram of the USB transmission rate improvement circuit of the application;

[0025] Figure 3 The data selection circuit principle diagram of the USB transmission rate improvement circuit of the application;

[0026] Figure 4 The microcontroller part circuit principle diagram of the USB transmission rate improvement circuit of the application;

[0027] Figure 5 The memory part circuit principle diagram of the USB transmission rate improvement circuit of the application. DETAILED DESCRIPTION

[0028] The preferred embodiments of the application will be described in detail below with reference to the drawings, wherein the drawings form a part of the application and are used to explain the principles of the application together with the embodiments of the application, and are not used to limit the scope of the application.

[0029] The utility model discloses a concrete embodiment of a kind of USB transmission rate promotion circuit, including bus switching circuit and memory;Bus switching circuit includes data selection circuit and microcontroller;The data selection circuit has low speed, high speed external data interface and synthetic data interface, and synthetic data interface is connected microcontroller;The low speed or high speed external data interface is connected with synthetic data interface;Microcontroller is electrically connected with memory.

[0030] Specifically, the low-speed external data interface receives the existing USB2.0 data transmission signal of the infrared handheld thermal imager. The high-speed external data interface sends or receives USB3.0 data to the peripheral device. When the low-speed or high-speed external data interface of the data selection circuit receives USB data from the outside, the received external USB data is first transmitted to the synthetic data interface. The synthetic data interface of the data selection circuit converts the USB data into EMMC bus interface data through the microcontroller and sends it to the memory for storage. When data needs to be sent externally, the microcontroller reads the EMMC bus interface data from the memory and converts it into USB3.0 data to send to the synthetic data interface of the data selection circuit. The data selection circuit sends USB3.0 data to the peripheral device through the high-speed external data interface.

[0031] The principle diagram of the data selection circuit is shown in Figure 3 .

[0032] The data selection circuit includes a USB switch chip. The USB switch chip includes low-speed, high-speed external data interfaces and a synthetic data interface. The low-speed external data interface is connected to the external USB2.0 data interface. The high-speed external data interface is connected to the external USB3.0 data interface. The USB switch chip also includes a data selection control pin. The data selection control pin controls the communication between the synthetic data interface and the low-speed or high-speed external data interface of the USB switch chip.

[0033] The system block diagram is shown in Figure 1 . The USB switch chip of the embodiment of the application corresponds to "TI's USB bus switching" in Figure 1 by TI company. The microcontroller uses CH565 chip of Qinheng company. Figure 1 The master ARM in is the infrared handheld thermal imager end. The "instrument interface" can be connected to the peripheral device with USB3.0 data transmission function.

[0034] The USB switch chip model is HD3SS6126RUAR; the 31st and 32nd pins of the HD3SS6126RUAR are respectively connected to the positive and negative ends of a USB2.0 data interface; the 23rd and 22nd pins of the HD3SS6126RUAR are respectively connected to the receiving positive and receiving negative pins of an external USB3.0 data interface; the 25th and 24th pins of the HD3SS6126RUAR are respectively connected to the sending positive and sending negative pins of the external USB3.0 data interface; the 33rd and 34th pins of the HD3SS6126RUAR are respectively connected to the D+ and D- pins of the external USB3.0 data interface; the 6th and 9th pins of the HD3SS6126RUAR are data selection control pins, are connected to one end of a pull-down resistor R2, receive a data selection control signal, and the other end of the pull-down resistor R2 is grounded; and the 8th, 7th, 11th, 12th, 15th and 16th pins of the HD3SS6126RUAR are synthetic data interface pins.

[0035] Specifically, the 13th and 20th pins of the HD3SS6126RUAR are connected to one end of four parallel filter capacitors and are connected to the power output end of the first power conversion circuit; the other end of the four parallel filter capacitors is grounded. The pull-down resistor R2 is 10K. The high and low levels of the data selection control signal input by the 6th and 9th pins of the HD3SS6126RUAR can realize the connection of the synthetic data interface with the low-speed external data interface or the high-speed external data interface. The data selection control signal can be generated by an external device or a microcontroller.

[0036] The memory model is FSEIASLD-128G.

[0037] The memory part circuit principle diagram is as shown in Figure 5 .

[0038] Specifically, the FSEIASLD-128G memory supports an EMMC bus interface, the FSEIASLD-128G is connected to the clock signal special pin of the microcontroller EMMC bus protocol through the M6 pin, is connected to the command signal EMMC_CMD special pin of the microcontroller EMMC bus protocol through the M5 pin, and is connected to the microcontroller EMMC bus data special pin through the EMMC data interface. The M5 pin of the FSEIASLD-128G memory is connected to the power output end of the first power conversion circuit through a 10k pull-up resistor; the K5 pin of the FSEIASLD-128G memory is connected to the power output end of the first power conversion circuit through a 33 ohm resistor.

[0039] The microcontroller part circuit principle diagram is as shown in Figure 4 .

[0040] The microcontroller comprises a USB data interface and an EMMC bus interface, the EMMC bus interface is connected with a memory, and the USB data interface is connected with a composite data interface of a USB switch chip.

[0041] Specifically, the microcontroller converts the USB data into EMMC bus interface data and transmits the EMMC bus interface data to the memory.

[0042] The USB transmission rate improvement circuit further comprises a matching resistor, which is connected between the 8-bit data interface of the EMMC bus interface of the microcontroller and the data IO port of the memory.

[0043] Specifically, the matching resistor connected between the 8-bit special data interface of the EMMC bus interface of the microcontroller and the data IO port of the memory is 33 ohms.

[0044] The microcontroller further comprises a pair of differential clock interfaces, which are connected with an external passive crystal oscillator to input and output clocks.

[0045] The microcontroller is of CH565 type; the 67 and 68 pins of the CH565 are respectively connected with a clock output pin and an input pin of a 30M passive crystal oscillator; the 31 and 29 pins of the CH565 are respectively connected with the M6 and M5 pins of the FSEIASLD-128G; and the EMMC bus special data interface of the CH565 is connected with the EMMC data interface of the FSEIASLD-128G.

[0046] The USB transmission rate improvement circuit further comprises a power control circuit; the power control circuit comprises a first power conversion circuit and a second power conversion circuit; the power input end of the first power conversion circuit is connected with an external power supply, the power output end of the first power conversion circuit is connected with the power input end of the second power conversion circuit; and the power output end of the second power conversion circuit is electrically connected with the microcontroller.

[0047] The power control circuit is shown in the schematic diagram as Figure 2

[0048] The first power conversion circuit further comprises a power control pin; the power output end of the first power conversion circuit is further electrically connected with the USB switch chip, the microcontroller and the memory; and the power control pin can control the first power conversion circuit to be turned on or turned off.

[0049] ​Specifically, the first power conversion circuit of the embodiment adopts NX3P1108UKZ chip, the B2 pin of the NX3P1108UKZ chip is connected with a 10k pull-down resistor, and the B2 pin also receives an external power control signal. The second power conversion circuit adopts TPS62237DRYR chip, the 6th pin of the chip is connected with the 2nd pin through a 1uH inductor, the 1st pin is grounded, and the 3rd pin is connected with the power output end of the first power conversion circuit. The 6th pin is also connected with a pi filter circuit, and finally outputs a 1.2V voltage. The pi filter circuit comprises one 0 ohm resistor and first to third 10uF capacitors, wherein the first and second 10uF capacitors are connected in parallel, one end of which is grounded and the other end is connected with the power output end of the second power conversion circuit and one end of the 0 ohm resistor, the other end of the 0 ohm resistor is connected with one end of the third 10uF capacitor and the 6th pin of the TPS62237DRYR chip, and the other end of the third 10uF capacitor is grounded.

[0050] The power control circuit takes into account the sensitivity of handheld devices to power consumption, increases the function of turning off the circuit, and has significant advantages and innovation.

[0051] Compared with the prior art, the USB transmission rate improvement circuit provided by the embodiment increases the bus switching circuit including the data selection circuit and the microcontroller on the basis of the original USB2.0 interface system; the data selection circuit includes low-speed and high-speed external data interfaces and a synthetic data interface, and the synthetic data interface is connected with the microcontroller; when the low-speed or high-speed external data interface receives data from the outside, the microcontroller sends the data to the memory for storage; when data needs to be sent to the outside, the microcontroller reads the data from the memory and sends the data to the synthetic data interface of the data selection circuit, and the data selection circuit sends the data to the outside through the high-speed external data interface. On the basis of maintaining the original infrared handheld thermal imager external transmission USB2.0 interface, the transmission effect of data exported to the outside at the USB3.0 speed is realized by adjusting the local circuit, which can effectively solve the problem of slow data transmission, does not change the original embedded chip, saves the cost, and maintains the compatibility with the original infrared handheld thermal imager. The first power conversion circuit in the USB transmission rate improvement circuit provided by the embodiment comprises a power control pin; the power output end of the first power conversion circuit is electrically connected with a second power conversion circuit, a USB switch chip, a microcontroller and a memory; and the power control pin can control the first power conversion circuit to be turned on or turned off. The sensitivity of handheld devices to power consumption is taken into account, the function of turning off the circuit is increased, and significant advantages and innovation are achieved.

[0052] Those skilled in the art can understand that the programs / software involved in the above embodiments are methods common in the prior art, and the utility model does not involve any improvement in the software aspect. The utility model only needs to connect various devices with corresponding functions through the connection relationship given in the embodiments of the utility model, and does not involve any improvement in the program / software aspect. As for the connection mode between the hardware devices with corresponding functions, it can be realized by using the prior art, and detailed description is not made here.

[0053] The above is only a preferred specific implementation manner of the utility model, but the protection scope of the utility model is not limited to this, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the utility model, which should be covered in the protection scope of the utility model.

Claims

1. A USB transmission rate enhancement circuit, characterized in that, Includes bus switching circuitry and memory; The bus switching circuit includes a data selection circuit and a microcontroller; The data selection circuit has low-speed and high-speed external data interfaces and a composite data interface, and the composite data interface is connected to the microcontroller. The low-speed or high-speed external data interface is connected to the synthetic data interface; The microcontroller is electrically connected to the memory.

2. The USB transmission rate enhancement circuit according to claim 1, characterized in that, The data selection circuit includes a USB switch chip; the USB switch chip includes low-speed and high-speed external data interfaces and a composite data interface, the low-speed external data interface is connected to an external USB 2.0 data interface; the high-speed external data interface is connected to an external USB 3.0 data interface; the USB switch chip also includes a data selection control pin; the data selection control pin controls the composite data interface of the USB switch chip to connect to the low-speed or high-speed external data interface.

3. The USB transmission rate enhancement circuit according to claim 2, characterized in that, The microcontroller includes a USB data interface and an EMMC bus interface. The EMMC bus interface is connected to the memory, and the USB data interface is connected to the composite data interface of the USB switch chip.

4. The USB transmission rate enhancement circuit according to claim 3, characterized in that, The USB transmission rate enhancement circuit also includes a matching resistor, which is connected between the 8-bit data interface of the microcontroller's EMMC bus interface and the data I / O port of the memory.

5. The USB transmission rate enhancement circuit according to claim 1, characterized in that, The USB transmission rate enhancement circuit also includes a power control circuit; the power control circuit includes a first power conversion circuit and a second power conversion circuit; the power input terminal of the first power conversion circuit is connected to an external power source, and the power output terminal of the first power conversion circuit is connected to the power input terminal of the second power conversion circuit. The power output terminal of the second power conversion circuit is electrically connected to the microcontroller.

6. The USB transmission rate enhancement circuit according to claim 5, characterized in that, The first power conversion circuit also includes a power control pin; the power output terminal of the first power conversion circuit is also electrically connected to the USB switch chip, the microcontroller, and the memory; the power control pin can control the first power conversion circuit to turn on or off.

7. The USB transmission rate enhancement circuit according to claim 3, characterized in that, The microcontroller also includes a pair of differential clock interfaces that connect to the input and output clocks of an external passive crystal oscillator.

8. The USB transmission rate enhancement circuit according to claim 6, characterized in that, The USB switch chip is model HD3SS6126RUAR. Pins 31 and 32 of HD3SS6126RUAR are connected to the positive and negative terminals of the USB 2.0 data interface, respectively. Pins 23 and 22 of HD3SS6126RUAR are connected to the positive and negative receive pins of the external USB 3.0 data interface, respectively. Pins 25 and 24 of HD3SS6126RUAR are connected to the positive and negative transmit pins of the external USB 3.0 data interface, respectively. Pins 33 and 34 of HD3SS6126RUAR are connected to the D+ and D- pins of the external USB 3.0 data interface, respectively. Pins 6 and 9 of HD3SS6126RUAR are data selection control pins, both connected to one end of pull-down resistor R2, and receive the data selection control signal. The other end of pull-down resistor R2 is grounded. Pins 8, 7, 11, 12, 15, and 16 of HD3SS6126RUAR are for the combined data interface.

9. The USB transmission rate enhancement circuit according to claim 6, characterized in that, The memory model is FSEIASLD-128G.

10. The USB transmission rate enhancement circuit according to claim 9, characterized in that, The microcontroller model is CH565; pins 67 and 68 of CH565 are connected to the clock output pin and input pin of a 30MHz passive crystal oscillator, respectively; pins 31 and 29 of CH565 are connected to the M6 ​​and M5 pins of FSEIASLD-128G, respectively; the dedicated EMMC bus data interface of CH565 is connected to the EMMC data interface of FSEIASLD-128G.

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