Double-host glasses framework with multiplied computing power

Abstract

The utility model discloses a double-host glasses framework with multiplied computing power, which belongs to the technical field of image processing, two groups of Soc host units in local closed-loop operation are arranged in the glasses framework, the two groups of Soc host units respectively and independently process images of left and right eyes, a high-speed data link is arranged between the Soc host units, and the Soc host units are connected with the high-speed data link. The Soc host units undertake image processing tasks of corresponding single eyes, respectively process image data of the left eye and the right eye in parallel through the two groups of independent Soc host units to form a local closed loop, and cooperatively work by using a high-speed data link which only transmits control information; therefore, calculation power multiplication is realized while a binocular pixel path is decoupled, the display delay is remarkably reduced, and the redundancy safety of the system is improved.

Description

Technical Field

[0001] This utility model relates to the field of image processing technology, and in particular to a dual-host glasses architecture that doubles computing power. Background Technology

[0002] With the rapid development of near-eye display technology and augmented reality (AR), virtual reality (VR), and video see-through (VST) technologies, wearable display devices are increasingly demanding higher image resolution and refresh rates. In pursuit of ultimate immersion and realism, 4K resolution per eye and refresh rates of 90Hz or even higher have gradually become the mainstream standards in the industry.

[0003] In the prior art, such as Chinese Patent Publication No. CN114488507A, a wearable display device for microscopic observation is disclosed. This wearable display device for binocular microscopy includes a wearable display, two video sensor heads, and an image processor. The wearable display has two screens for viewing by both eyes. The video sensor heads have mounting brackets that can be directly mounted on the eyepieces of any binocular microscope to acquire image information. The image information acquired through the two eyepieces is then sent to the image processor in an external host for processing. The video signals output by the image processor can then be viewed by both eyes through the screens in the wearable display device. The observer can remotely observe the images in the eyepieces without any modification to the binocular microscope. The communication port of the external host can connect to a remote server to achieve remote technical collaboration.

[0004] Most existing wearable display devices employ a single-host (SoC) architecture. In this architecture, a single chip must simultaneously drive both the left and right display units through multiple interfaces. With increasing resolution, in traditional SoC solutions, all tasks such as image rendering, ISP (Image Signal Processing), and geometric correction compete for the computing resources within the same SoC. When processing ultra-high-resolution pixel data, the SoC's internal bus bandwidth and memory controller often become bottlenecks, forcing the system to reduce image quality or sacrifice frame rate to maintain operation, severely impacting the visual experience.

[0005] Meanwhile, excessive end-to-end latency in a single-host architecture results in a sequential or time-division multiplexing of the two image signals in the processing logic, leading to a severe queuing effect in the image data processing buffer. For VST devices, excessive latency causes the user's perceived image to lag behind the physical action, which in turn causes severe visual motion sickness.

[0006] Furthermore, since the single host is the sole control core of the entire system, if it loses power or stops working due to overheating, overload, or hardware failure, it will directly lead to the loss of synchronization between the two eyes' images or even a complete black screen. In applications with extremely high real-time requirements, such as industrial, medical, or driving applications, this lack of redundancy poses significant safety hazards.

[0007] From an industrialization perspective, while self-developed dedicated chips and independent production lines allow for deep customization of the process, they involve high investment, long cycles, concentrated risks, and difficulty in keeping up with process iterations. In contrast, the mobile phone industry chain is highly mature, with rapid updates to general-purpose system-on-a-chip (SoC) and a complete toolchain and driver ecosystem. If the coupling between the two devices in the pixel path is decoupled at the system architecture level, allowing each device to occupy a complete acquisition, processing, and display loop, it can directly support generational upgrades of general-purpose chips. This allows for simultaneous improvements in resolution, frame rate, and latency at a lower marginal cost, while preserving the space for future expansion through high-speed interconnect standards. Open interconnect standards for chip-level integration are also evolving rapidly, providing a mature path for future access to higher-speed on-chip interconnects and control plane communication at the packaging level. Utility Model Content

[0008] To address the aforementioned issues, this invention provides a dual-host glasses architecture that doubles computing power. It uses two independent SoC host units to process the image data of the left and right eyes in parallel, forming a local closed loop. It also utilizes a high-speed data link that transmits only control information to work together, thereby decoupling the pixel paths of both eyes, doubling computing power, significantly reducing display latency, and improving the redundancy and security of the system.

[0009] The above objectives can be achieved through the following approach:

[0010] A dual-host glasses architecture that doubles computing power includes a glasses frame, within which are two sets of locally closed-loop operating SoC host units. The two sets of SoC host units independently process images for the left and right eyes, respectively. A high-speed data link is provided between the SoC host units, and each SoC host unit undertakes the image processing task for its corresponding single eye.

[0011] Furthermore, the two sets of SoC host units corresponding to the left and right eyes each form a local closed-loop operation, and the two sets of SoC host units corresponding to the left and right eyes operate in parallel without forwarding image data through the other SoC host unit.

[0012] Optionally, the high-speed data link is used only for processing control information exchange between the two sets of SoC host units. The high-speed data link includes, but is not limited to, at least one of PCIExpress-based wired links, USB-based wired links, and UCIe-compliant high-speed inter-chip interconnects.

[0013] Optionally, the eyeglasses frame may also include a display component for receiving and displaying image signals from the SoC host unit.

[0014] Optionally, each of the SoC host units corresponds to at least one set of display components. The SoC host unit is electrically connected to the corresponding display component, and the SoC host unit and the corresponding display component constitute a local hardware path for monocular image processing and display, forming a local closed-loop operation of the SoC host unit display.

[0015] Optionally, when any SoC host unit fails, loses power, or stops working, another SoC host unit can continue to drive its corresponding display component without obtaining control commands or image data from that SoC host unit, maintaining image data output for at least one eye.

[0016] Optionally, the dual-host glasses architecture further includes a power supply unit, which includes a battery module mounted on the glasses frame and is electrically connected to the SoC host unit and the display component.

[0017] Optionally, the power supply unit may include, but is not limited to, a built-in battery and an external power supply structure.

[0018] Optionally, the SoC host unit is symmetrically arranged within the eyeglass frame, and the eyeglass frame is provided with a heat dissipation component that fits into the SoC host unit.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] This invention establishes two independent SoC host units for processing the left and right eyes, enabling each eye to have a complete processing and display closed loop. This parallel operation mode effectively decouples the two eyes in the pixel path, while also directly supporting generational upgrades in general-purpose chips, achieving higher resolution and frame rates at a lower cost, thus doubling computing power and improving performance.

[0021] The two sets of SoC host units of this invention operate in parallel without forwarding image data from the other party, eliminating the image queuing effect in the single host architecture, significantly reducing end-to-end latency, and thus effectively alleviating motion sickness caused by image lag.

[0022] Meanwhile, this invention forms a local closed-loop operation. When one of the SoC host units fails, loses power, or stops working, the other unit can continue to drive its corresponding display component without needing to obtain instructions from the other, ensuring that at least one eye has image output, thus improving safety in extreme scenarios. Furthermore, the high-speed data links between SoCs (such as PCI Express, USB, or UCIe) are only used for control information interaction, ensuring the coordination of images from both eyes without occupying image processing bandwidth. The SoC host units are symmetrically arranged within the frame and equipped with fitting heat dissipation components, ensuring thermal stability under high load operation and providing high hardware redundancy and safety. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of the dual-host electronic glasses of this utility model;

[0025] Figure 2 This is a cross-sectional view of the dual-host electronic glasses of this utility model.

[0026] In the diagram: 1. Eyeglasses frame; 2. Display component; 3. SoC host unit. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0028] Reference Figures 1-2 As shown, one embodiment of this utility model proposes a dual-host glasses architecture with doubled computing power, including a glasses frame. The glasses frame is equipped with two sets of locally closed-loop operating SoC host units, and the two sets of SoC host units independently process the images of the left and right eyes respectively. A high-speed data link is provided between the SoC host units, and the SoC host units undertake the image processing tasks of the corresponding single eye.

[0029] Furthermore, the two sets of SoC host units corresponding to the left and right eyes each form a local closed-loop operation, and the two sets of SoC host units corresponding to the left and right eyes operate in parallel without forwarding image data through the other SoC host unit.

[0030] Specifically, the system employs two independent SoC host units, electrically independent of each other and possessing their own independent computing cores and memory resources. A physical high-speed data link connects the communication interfaces of the left and right host units via cabling. Logically, the system firmware specifies that the left SoC host unit is dedicated to processing image data for the left eye's visual region, while the right SoC host unit is dedicated to processing image data for the right eye's visual region. This architecture physically eliminates the bottleneck of having to converge binocular image data onto a single chip, allowing both SoC host units to start and perform data computation simultaneously. Because the hardware is independent, left-eye image data does not need to be transmitted to the right host, and right-eye image data does not pass through the left host, thus achieving parallel operation and local closed-loop processing at the physical pathway level. When the user wears glasses, the left display image directly enters the left SoC for rendering, and the right image is processed similarly. The two do not wait for each other, eliminating the queuing delay caused by single-chip time-sharing of binocular images, significantly improving image processing throughput, and reducing the risk of motion sickness caused by image lag.

[0031] Optionally, the high-speed data link is used only for processing control information exchange between the two sets of SoC host units. The high-speed data link includes, but is not limited to, at least one of the following: PCI Express-based wired link, USB-based wired link, and UCIe-compliant high-speed inter-chip interconnect.

[0032] Specifically, the physical layer routing of the high-speed data link is configured to transmit only control plane information, such as timestamp synchronization signals, spatial coordinate matrix information, or interactive commands, while shielding the transmission of large amounts of video pixel data at the underlying protocol level. In terms of hardware selection, engineers can use differential signal lines based on the PCI Express protocol to connect two SoCs in the PCB design, or use physical interface lines based on the USB protocol, or adopt UCIe-compliant inter-chip interconnect technology to package two bare dies on the same substrate and interconnect them through high-density wiring. This design ensures that the communication channel is not blocked by massive amounts of video data, guarantees the real-time arrival of control commands, reduces dependence on inter-chip interconnect bandwidth, and allows low-cost, low-power interconnect interfaces to meet the needs of dual-machine collaboration, while ensuring a high degree of consistency in the rendering rhythm of both eyes.

[0033] Optionally, a display component is also provided within the eyeglass frame, which is used to receive and display image signals from the SoC host unit.

[0034] Specifically, a display component is installed at the eye position on the eyeglass frame. This display component is physically fixed inside the frame, with the light path aligned with the user's eyes. The signal input of the display component is directly soldered or connected to the video output interface of the SoC host unit, such as a MIPI DSI or DisplayPort interface, via a flexible printed circuit board (FPC) or coaxial cable. Through this connection, the digital image signal processed by the SoC host unit is directly converted into an optical signal for display, completing the physical connection from computation to display. This simplifies the internal wiring complexity, saves internal space, reduces signal attenuation and interference over long distances, and ensures image clarity.

[0035] Optionally, each SoC host unit corresponds to at least one set of display components. The SoC host unit is electrically connected to the corresponding display components, and the SoC host unit and the corresponding display components constitute a local hardware path for monocular image processing and display, forming a local closed-loop operation of the SoC host unit display.

[0036] Specifically, the SoC host unit adopts a dedicated one-to-one or one-to-many connection mode. That is, the video output pin of the left SoC host unit is connected only to the display component of the left eye, and the same applies to the right side. Multiple sets of left-eye and right-eye display components can be set as needed to improve the display effect. This connection method constructs a local hardware path for monocular image processing and display at the physical layer. The entire data flow process is strictly limited to a single-sided hardware closed loop, and there is no overhead of cross-side data routing or bus arbitration.

[0037] Optionally, when any SoC host unit fails, loses power, or stops working, another SoC host unit can continue to drive its corresponding display component without obtaining control commands or image data from that SoC host unit, maintaining image data output for at least one eye.

[0038] Specifically, because the two SoC host units have independent power management chips and boot programs, when one SoC host unit shuts down due to overheating, battery depletion, or program crash, the other SoC host unit will detect the link interruption, but its own image rendering cycle does not depend on the other's status signal. Therefore, the SoC host unit that is not malfunctioning continues to send image signals to its connected display components at the predetermined refresh rate, maintaining normal display of the screen on one side. If the left host unit overheats and is forced to restart due to processing complex 3D drawings, the right host unit will still work normally, and the operator's right eye can still maintain the display of necessary information. This improves the safety and reliability of the equipment in mission-critical scenarios and avoids the dangerous situation of the operator completely losing visual assistance or falling into "total darkness" due to a single point of failure.

[0039] Optionally, the dual-host glasses architecture also includes a power supply unit, which includes a battery module mounted on the glasses frame and electrically connected to the SoC host unit and the display component.

[0040] Specifically, space is planned within the structural design of the eyeglass frame to accommodate the power supply unit, typically located at the rear of the temples. Battery modules, such as lithium polymer cells, are then connected via power management circuitry to provide power to the left and right SoC host units and their corresponding display components. A dual-power supply topology can be employed, where the positive terminal of the battery is connected to two independent power management chips (PMICs) via a shunt circuit. This ensures that power is simultaneously and stably delivered to the two high-performance computing nodes. A well-planned battery layout balances the overall center of gravity, improving wearing comfort while providing the necessary energy support for the high-power operation of the dual hosts.

[0041] Optionally, the power supply unit may include, but is not limited to, a built-in battery and an external power supply structure.

[0042] Specifically, the power supply unit was redesigned with an expanded configuration. While retaining the internal battery as the primary energy source, standard power interfaces, such as USB, Type-C, or magnetic contacts, were added to the outside or bottom of the eyeglass frame. These interfaces are connected to the battery charge / discharge management chip via internal circuitry. This allows the device to not only rely on its internal chemical power source but also support connection to external power sources, such as power banks, adapters, or tethered cables, thus creating a hybrid power supply system. For example, the eyeglasses themselves contain a small-capacity battery to maintain short-term wireless use, while the temples feature magnetic interfaces to attach a cable to a high-capacity power bank. When a cable is connected, the system automatically switches to external power supply mode. The beneficial effect of this demonstration is that it solves the high power consumption and battery life anxiety caused by dual-host architectures, enabling the device to meet both the needs of lightweight, short-term use and the demands of long-term, high-intensity work environments.

[0043] Optionally, the SoC host unit is symmetrically arranged within the eyeglass frame, and the eyeglass frame is provided with a heat dissipation component that fits into the SoC host unit.

[0044] Specifically, two sets of SoC main units are symmetrically distributed along the center line of the forehead of the eyeglass frame. Heat dissipation components are attached to the chip surface of the SoC main units. These components can be graphene thermal pads, copper heat sinks, or micro heat pipes. The shape of the heat dissipation components conforms to the SoC main units and the surrounding inner wall of the frame, utilizing the frame's surface area for passive heat dissipation or constructing airflow channels for active heat dissipation. The two SoCs are physically symmetrical, and the heat generated is evenly dissipated through the metal casing, ensuring weight balance on both sides of the glasses and preventing tilting during wear. Simultaneously, the symmetrical heat dissipation design ensures that the two SoCs maintain the same temperature under the same workload, preventing inconsistent visual performance between the two eyes due to unilateral overheating and frequency throttling.

[0045] All equivalent changes and modifications made in accordance with the teachings of this utility model shall still fall within the scope of this utility model. Other embodiments of this utility model will be readily apparent to those skilled in the art upon consideration of the specification and the disclosure of practical truth. This application is intended to cover any variations, uses, or adaptations of this utility model that follow the general principles of this utility model and include common knowledge or customary techniques in the art not described in this utility model.

Claims

1. A dual-host glasses architecture for doubled computing power, comprising a glasses frame, characterized in that, The eyeglasses frame is equipped with two sets of locally closed-loop SoC host units, and the two sets of SoC host units independently process the images of the left and right eyes. A high-speed data link is provided between the SoC host units, and the SoC host unit undertakes the image processing task of the corresponding single eye.

2. The dual-host glasses architecture for doubling computing power according to claim 1, characterized in that, The high-speed data link is used only for processing control information exchange between the two sets of SoC host units. The high-speed data link includes, but is not limited to, at least one of the following: PCI Express-based wired link, USB-based wired link, and UCIe-compliant high-speed chip-to-chip interconnect.

3. The dual-host glasses architecture for multiplying computing power according to claim 1, characterized in that, The eyeglasses frame is also equipped with a display component, which is used to receive and display image signals from the SoC host unit.

4. The dual-host glasses architecture for multiplying computing power according to claim 1, characterized in that, The SoC host unit corresponds to at least one set of display components. The SoC host unit is electrically connected to the corresponding display component, and the SoC host unit and the corresponding display component constitute a local hardware path for monocular image processing and display, forming a local closed-loop operation of the SoC host unit display.

5. The dual-host glasses architecture for doubling computing power according to claim 1, characterized in that, The dual-host glasses architecture also includes a power supply unit, which includes a battery module mounted on the glasses frame and is electrically connected to the SoC host unit and the display component.

6. The dual-host glasses architecture for multiplying computing power according to claim 5, characterized in that, The power supply unit includes, but is not limited to, a built-in battery and an external power supply structure.

7. The dual-host glasses architecture for doubling computing power according to claim 1, characterized in that, The SoC host unit is symmetrically arranged within the eyeglass frame, and the eyeglass frame is provided with a heat dissipation component that fits into the SoC host unit.

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