Light emitting diode epitaxial wafer and light emitting diode

Abstract

The utility model discloses a light emitting diode epitaxial wafer and a light emitting diode. The light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an insertion layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-GaN layer which are stacked on the substrate in sequence. Wherein the insertion layer at least comprises a Si3N4 layer. The light-emitting efficiency of the light-emitting diode provided by the utility model is obviously improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a light-emitting diode epitaxial wafer and a light-emitting diode. Background Technology

[0002] A light-emitting diode (LED) epitaxial wafer consists of a substrate and an epitaxial layer grown on the substrate. The substrate is typically made of materials such as sapphire, silicon, or silicon carbide. Due to lattice mismatch and differences in thermal expansion coefficients, the epitaxial layer structure generates significant stress and defects during growth, affecting internal quantum efficiency and ultimately luminous efficiency. To relieve this stress, an InGaN stress-relieving layer is usually placed before the multi-quantum-well layer. However, the InGaN layer also generates stress with the GaN layer in the multi-quantum-well layer, thus limiting its stress-regulating effect. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an epitaxial wafer for a light-emitting diode and a light-emitting diode, which can improve the brightness of the light-emitting diode.

[0004] To address the aforementioned technical problems, this utility model discloses a light-emitting diode epitaxial wafer, comprising a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an insertion layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-GaN layer sequentially stacked on the substrate; wherein the insertion layer comprises at least a Si3N4 layer.

[0005] As an improvement to the above scheme, the thickness of the insertion layer is 10nm to 100nm.

[0006] As an improvement to the above scheme, the thickness of the insertion layer is 30nm to 70nm.

[0007] As an improvement to the above scheme, the insertion layer is a Si3N4 layer.

[0008] As an improvement to the above scheme, the insertion layer includes periodically alternating layers of Si3N4 and InN.

[0009] As an improvement to the above scheme, the number of alternating stacking cycles of the Si3N4 layer and the InN layer is 3 to 8, and in each cycle, the thickness ratio of the Si3N4 layer to the InN layer is 1:(0.3 to 0.5).

[0010] As an improvement to the above scheme, the buffer layer includes an AlN buffer layer, a GaN buffer layer and a three-dimensional GaN buffer layer stacked sequentially; the thickness of the AlN buffer layer is 10nm to 30nm, the thickness of the GaN buffer layer is 15nm to 35nm, and the thickness of the three-dimensional GaN buffer layer is 500nm to 2000nm.

[0011] As an improvement to the above scheme, the stress relief layer includes periodically alternating layers of InGaN and GaN layers, with an alternation period of 5 to 14; in each period, the thickness of the InGaN layer is 2 nm to 4 nm, and the thickness of the GaN layer is 5 nm to 10 nm.

[0012] As an improvement to the above scheme, the multi-quantum well layer includes periodically alternating InGaN well layers and GaN barrier layers, with an alternation period of 6 to 14; in each period, the thickness of the InGaN well layer is 2 nm to 4 nm, and the thickness of the GaN barrier layer is 8 nm to 12 nm.

[0013] Accordingly, this utility model also discloses a light-emitting diode, which includes the above-mentioned light-emitting diode epitaxial wafer.

[0014] The present invention provides the following advantages: An insertion layer is provided between the N-GaN layer and the stress-relieving layer, and the insertion layer includes at least a Si3N4 layer. The Si3N4 layer can absorb some lattice distortion, reduce defect propagation, and lower dislocation density. Furthermore, the thermal expansion coefficient of Si3N4 material is close to that of the epitaxial GaN material, which can reduce thermal mismatch stress. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the light-emitting diode epitaxial wafer provided in this embodiment of the utility model;

[0016] Figure 2 This is a schematic diagram of the structure of the buffer layer provided in an embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram of the structure of the insertion layer provided in an embodiment of this utility model. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this utility model clearer, the following will describe this utility model in further detail with reference to the accompanying drawings. It is hereby declared that the terms "up," "down," "left," "right," "front," "back," "inner," and "outer," etc., appearing or about to appear in this document, are based solely on the accompanying drawings and are not intended to specifically limit this utility model.

[0019] like Figure 1 As shown, this embodiment of the present invention provides a light-emitting diode epitaxial wafer, including a substrate 100, and a buffer layer 200, a U-GaN layer 300, an N-GaN layer 400, an insertion layer 500, a stress relief layer 600, a multiple quantum well layer 700, an electron blocking layer 800 and a P-GaN layer 900 sequentially stacked on the substrate 100.

[0020] Specifically, substrate 100 can be selected from one of the following: sapphire substrate, SiO2-sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate. Specifically, substrate 100 is selected as a sapphire substrate. Sapphire is currently the most commonly used substrate material for GaN-based light-emitting diodes. Sapphire substrates have advantages such as mature manufacturing processes, low price, ease of cleaning and processing, and good stability at high temperatures.

[0021] The buffer layer 200 can be one or more of AlN buffer layers, AlGaN buffer layers, and GaN buffer layers. Specifically, for example... Figure 2 As shown, the buffer layer 200 includes an AlN buffer layer 210, a GaN buffer layer 220, and a three-dimensional GaN buffer layer 230 stacked sequentially. The thickness of the AlN buffer layer 210 is 10nm to 30nm, exemplarily 14nm, 16nm, 18nm, 20nm, 24nm, or 28nm, but not limited thereto. The thickness of the GaN buffer layer 220 is 15nm to 35nm, exemplarily 18nm, 20nm, 26nm, 28nm, 30nm, or 32nm, but not limited thereto. The thickness of the three-dimensional GaN buffer layer 230 is 500nm to 2000nm, exemplarily 800nm, 1000nm, 1200nm, 1400nm, 1600nm, or 1800nm, but not limited thereto. An AlN buffer layer 210 provides nucleation centers aligned with the substrate, relieving stress caused by lattice mismatch between the subsequently grown GaN material and the substrate material, as well as thermal stress caused by thermal expansion coefficient mismatch. This is followed by the growth of GaN buffer layer 220 and a three-dimensional GaN buffer layer 230, improving the quality of the subsequently grown epitaxial structure and thus the overall crystal quality of the epitaxial wafer, ultimately increasing the luminous efficiency of the fabricated light-emitting diode. The AlN buffer layer 210 can be grown using PVD, the GaN buffer layer 220 using MOCVD, and the three-dimensional GaN buffer layer 230 using MOCVD. The growth temperature is 1000℃~1200℃, the growth pressure is 100torr~300torr, TMGa is used as the Ga source, NH3 as the N source, and N2 and H2 as carrier gases.

[0022] The U-GaN layer 300 is an undoped GaN layer with a thickness of 800nm ​​to 1200nm.

[0023] The thickness of the N-GaN layer 400 is 1000 nm to 3000 nm, and the Si doping concentration is 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 .

[0024] The insertion layer 500 is at least a Si3N4 layer 510.

[0025] In one embodiment, the insertion layer 500 is a Si3N4 layer 510. Since Si3N4 is an amorphous structure, it does not directly match InGaN, thus absorbing some lattice distortion and reducing defect propagation, thereby lowering the dislocation density. Simultaneously, the Si3N4 layer 510 formed from the amorphous Si3N4 material is a porous thin film layer, and the coefficient of thermal expansion of Si3N4 is approximately 3 × 10⁻⁶. -6 / K, compared to the thermal expansion coefficient of GaN (approximately 5.6 × 10⁻⁶). -6 The coefficient of thermal expansion ( / K) is close to, and lower than, that of sapphire (approximately 7.5 × 10⁻⁶). -6 / K), which can reduce thermal mismatch stress. The growth temperature of Si3N4 layer 510 is 800℃~1000℃, the growth pressure is 100torr~300torr, NH3 is used as N source, SiH4 is used as Si source, and N2 is used as carrier gas.

[0026] Understandably, the thickness of the Si3N4 layer 510 also plays a crucial role. Due to the physical properties of Si3N4, if it is too thin, it cannot effectively release stress; if it is too thick, it will cause cracks, affecting the growth of subsequent epitaxial layers or introducing further defects. In one embodiment, the thickness of the Si3N4 layer 510 is 10nm to 100nm, with exemplary values ​​of 20nm, 40nm, 50nm, 60nm, 80nm, or 90nm, but not limited to these. Preferably, the thickness of the Si3N4 layer 510 is 30nm to 70nm.

[0027] In a preferred embodiment, such as Figure 3 As shown, the insertion layer 500 includes periodically alternating Si3N4 layers 510 and InN layers 520. The number of alternating stacks of Si3N4 layers 510 and InN layers 520 is 3 to 8. In each period, the thickness ratio of Si3N4 layer 510 to InN layer 520 is 1:(0.3 to 0.5), exemplarily 1:0.32, 1:0.34, 1:0.38, 1:0.4, 1:0.42, or 1:0.48, but not limited to these. Si3N4 layer 510 serves to block defects and dislocation propagation and release stress. InN layer 520 can improve the lateral mobility of Si and N atoms on the surface of Si3N4 layer 510, improve the growth quality of Si3N4 layer 510, and the good uniformity of Si3N4 layer 510 further enhances the blocking of dislocations and defects.

[0028] The stress relief layer 600 comprises periodically alternating layers of InGaN and GaN stress relief layers, with a growth cycle of 2 to 10. The thickness of the InGaN stress relief layer is 1 nm to 3 nm, and the thickness of the GaN stress relief layer is 15 nm to 30 nm. In a preferred embodiment, the stress relief layer 600 can be a low-temperature stress relief layer, with a growth temperature of 800°C to 900°C.

[0029] The multi-quantum-well layer 700 comprises periodically alternating InGaN well layers and GaN barrier layers, with an alternation period of 6 to 14. In each period, the thickness of the InGaN well layer is 2 nm to 4 nm, and the thickness of the GaN barrier layer is 8 nm to 12 nm.

[0030] The electron blocking layer 800 comprises a periodically alternating structure of AlGaN electron blocking layers and GaN electron blocking layers, with a thickness ranging from 10 nm to 60 nm. The electron blocking layer 800 effectively restricts electron overflow and reduces hole blocking, thereby improving the hole-to-electron-well injection efficiency, reducing carrier Auger recombination, and enhancing the luminous efficiency of the light-emitting diode.

[0031] The thickness of the P-GaN layer 900 is 10 nm to 50 nm, and the Mg doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 21 cm -3 Excessive Mg doping concentration will damage the crystal quality, while insufficient doping concentration will affect the hole concentration.

[0032] Accordingly, this utility model also discloses a light-emitting diode, which includes the above-mentioned light-emitting diode epitaxial wafer.

[0033] The present invention will be further illustrated below with specific embodiments:

[0034] Example 1

[0035] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an insertion layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer sequentially stacked on the substrate.

[0036] The insertion layer is a Si3N4 layer with a thickness of 50 nm.

[0037] Example 2

[0038] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 5 nm. All other aspects are the same as in Embodiment 1.

[0039] Example 3

[0040] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 10 nm. All other aspects are the same as in Embodiment 1.

[0041] Example 4

[0042] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 30 nm. All other aspects are the same as in Embodiment 1.

[0043] Example 5

[0044] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 60 nm. All other aspects are the same as in Embodiment 1.

[0045] Example 6

[0046] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 80 nm. All other aspects are the same as in Embodiment 1.

[0047] Example 7

[0048] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 100 nm. All other aspects are the same as in Embodiment 1.

[0049] Example 8

[0050] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer is a Si3N4 layer with a thickness of 120 nm. All other aspects are the same as in Embodiment 1.

[0051] Example 9

[0052] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer includes periodically alternating Si3N4 layers and InN layers, with a stacking period of 5. In each period, the thickness of the Si3N4 layer is 5 nm, and the thickness of the InN layer is 2.5 nm. All other aspects are the same as in Embodiment 1.

[0053] Comparative Example 1

[0054] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not have an insertion layer, but is otherwise the same as Example 1.

[0055] The LED epitaxial wafers obtained in Examples 1 to 9 and Comparative Example 1 were fabricated into standard-sized chips with dimensions of 22mil*35mil. The test current was 60mA. Performance tests were performed on the standard-sized chips, and the luminous efficiency improvement rate of Examples 1 to 9 compared to Comparative Example 1 was calculated. The specific test results are shown in the table below:

[0056]

[0057] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications are also considered to be within the protection scope of this utility model.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, It includes a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an insertion layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer sequentially stacked on the substrate; wherein the insertion layer includes at least a Si3N4 layer.

2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The thickness of the insertion layer is 10 nm to 100 nm.

3. The light-emitting diode epitaxial wafer as described in claim 2, characterized in that, The thickness of the insertion layer is 30nm to 70nm.

4. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The insertion layer is a Si3N4 layer.

5. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The insertion layer comprises periodically alternating layers of Si3N4 and InN.

6. The light-emitting diode epitaxial wafer as described in claim 5, characterized in that, The number of alternating Si3N4 and InN layers is 3 to 8, and in each cycle, the thickness ratio of the Si3N4 layer to the InN layer is 1:(0.3 to 0.5).

7. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The buffer layer comprises an AlN buffer layer, a GaN buffer layer, and a three-dimensional GaN buffer layer stacked sequentially; the thickness of the AlN buffer layer is 10nm to 30nm, the thickness of the GaN buffer layer is 15nm to 35nm, and the thickness of the three-dimensional GaN buffer layer is 500nm to 2000nm.

8. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The stress relief layer comprises periodically alternating layers of InGaN and GaN stress relief layers, with an alternation period of 2 to 10. In each period, the thickness of the InGaN stress relief layer is 1 nm to 3 nm, and the thickness of the GaN stress relief layer is 15 nm to 30 nm.

9. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The multiple quantum well layer comprises periodically alternating InGaN well layers and GaN barrier layers, with an alternation period of 6 to 14; in each period, the thickness of the InGaN well layer is 2 nm to 4 nm, and the thickness of the GaN barrier layer is 8 nm to 12 nm.

10. A light-emitting diode, characterized in that, The light-emitting diode includes a light-emitting diode epitaxial wafer as described in any one of claims 1 to 9.

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