Pixels, display devices including pixels, and electronic devices including display devices.

Abstract

This application relates to pixels, display devices including pixels, and electronic devices including display devices. A pixel includes: a light-emitting element through which a driving current flows; a light-emitting element driver that generates the driving current based on a pulse-width modulation (PWM) signal; and a pulse-width modulator that generates a PWM signal based on first data bits to a k-th data bit. The PWM modulator includes: a data writer that writes first data bits to a k-th data bit in response to a scan signal; a PWM controller that stores first data bits to a k-th data bit and sequentially outputs first data bits to a k-th data bit in response to a clock signal; and a PWM signal generator that generates a PWM signal in response to the first data bits to a k-th data bit and a transmit signal.

Description

Technical Field

[0001] The embodiments relate to display devices. More specifically, the embodiments relate to pixels driven by a pulse width modulation method, display devices including pixels, and electronic devices including display devices. Background Technology

[0002] The display device may include multiple pixels, and each pixel may include a self-emissive element. The self-emissive element may include an organic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, etc.

[0003] Typically, organic light-emitting diodes (OLEDs) can be driven using a pulse amplitude modulation (“PAM”) method, which controls the brightness of light emitted from a pixel by controlling the amplitude of the driving current flowing through the OLED.

[0004] When a micro-LED is driven using a pulse amplitude modulation (PWM) method, the wavelength of the light emitted from the micro-LED may vary depending on the amplitude of the driving current flowing through it. Therefore, the micro-LED can be driven using a pulse width modulation ("PWM") method, which controls the brightness of the light emitted from the pixel by controlling the emission duration of the micro-LED while keeping the amplitude of the driving current flowing through it constant. Utility Model Content

[0005] The implementation provides pixels that accurately represent grayscale levels.

[0006] The embodiments provide a display device with improved display quality and an electronic device including the display device.

[0007] The pixel in the embodiments of this disclosure includes: a light-emitting element through which a driving current flows; a light-emitting element driver that generates the driving current based on a pulse width modulation signal; and a pulse width modulator that generates a pulse width modulation signal based on a first data bit to a k-th data bit, where k is a natural number greater than 2. The pulse width modulator includes: a data writer that writes the first data bit to the k-th data bit in response to a scan signal; a pulse width modulation controller that stores the first data bit to the k-th data bit and sequentially outputs the first data bit to the k-th data bit in response to a clock signal; and a pulse width modulation signal generator that generates the pulse width modulation signal in response to the first data bit to the k-th data bit and a transmit signal.

[0008] In one implementation, the pulse width modulation controller may include: a first flip-flop to a k-th flip-flop, which shifts a first data bit to a k-th data bit in response to a clock signal; and a first connection transistor to a k-th connection transistor, which connects the first flip-flop to the k-th flip-flop in response to a scan signal.

[0009] In this implementation, the first data bits to the kth data bits can be written to the first flip-flops to the kth flip-flops at the rising or falling edge of the clock signal during the activation period of the scan signal.

[0010] In the implementation, the first data bit to the kth data bit can be shifted between the first flip-flop and the kth flip-flop at the rising or falling edge of the clock signal during the activation period of the transmit signal.

[0011] In an implementation, the transmit length corresponding to each of the first data bit and the kth data bit can be the interval between the rising or falling edge of the transmit signal and the rising or falling edge of the adjacent (near) rising or falling edge of the transmit signal of the clock signal.

[0012] In an implementation, the transmit length corresponding to each of the second to (k-1)th data bits among the first to kth data bits can be the interval between adjacent pulses of the clock signal.

[0013] In an implementation, each of the first to the kth connection transistors may be one of an n-channel metal-oxide-semiconductor (“NMOS”) transistor, a p-channel metal-oxide-semiconductor (“PMOS”) transistor, and a complementary metal-oxide-semiconductor (“CMOS”) transistor.

[0014] In one implementation, the data writer may include a first write transistor to a k-th write transistor, which writes a first data bit to a k-th data bit to a first flip-flop to a k-th flip-flop in response to a scan signal.

[0015] In an implementation, each of the first write transistor to the kth write transistor can be one of an NMOS transistor, a PMOS transistor, and a CMOS transistor.

[0016] In one implementation, the pulse width modulation signal generator may include logic gates that generate a pulse width modulation signal in response to a k-th output signal or a k-th inverted output signal from a k-th flip-flop and a transmit signal.

[0017] In the implementation, the logic gate can be one of NAND gate, OR gate, NOR gate and AND gate.

[0018] In an implementation, the pulse width modulation signal generator may further include a level shifter that changes the voltage level of the pulse width modulation signal.

[0019] In one embodiment, the light-emitting element driver may include an emitting transistor that forms a current path for a drive current in response to a pulse width modulation signal, and a current source that controls the amplitude of the drive current.

[0020] In this implementation, the emitter transistor can be either a PMOS transistor or an NMOS transistor.

[0021] In one implementation, the emitting transistor can be connected to a line that transmits high voltage, the light-emitting element can be connected to a line that transmits low voltage, and a current source can be connected between the emitting transistor and the light-emitting element.

[0022] In one implementation, the light-emitting element can be connected to a line that transmits high voltage, the emitting transistor can be connected to a line that transmits low voltage, and a current source can be connected between the light-emitting element and the emitting transistor.

[0023] The display device may include: a display panel including pixels; a data driver providing each pixel with first data bits to k data bits corresponding to grayscale levels, where k is a natural number greater than 2; and a gate driver providing the pixels with a scan signal, a clock signal, and a transmit signal. Each pixel may include: a light-emitting element through which a drive current flows; a light-emitting element driver generating a drive current based on a pulse width modulation signal; and a pulse width modulator generating a pulse width modulation signal based on the first data bits to the k data bits. The pulse width modulator may include: a data writer writing the first data bits to the k data bits in response to a scan signal in the scan signal; a pulse width modulation controller storing the first data bits to the k data bits and sequentially outputting the first data bits to the k data bits in response to a clock signal in the clock signal; and a pulse width modulation signal generator generating the pulse width modulation signal in response to the first data bits to the k data bits and a transmit signal in the transmit signal.

[0024] In this implementation, each of the scan signal, clock signal, and transmit signal can be provided sequentially to the pixel rows of the display panel at horizontal time intervals.

[0025] In this implementation, scan signals can be sequentially provided to the pixel rows of the display panel at horizontal time intervals, and each of the clock signal and the transmit signal can be provided to the pixel rows simultaneously.

[0026] In one implementation, when a still image is displayed on the display panel, the pulse width modulator can generate a pulse width modulation signal based on the first to the kth data bits stored in the pulse width modulation controller without rewriting the first to the kth data bits.

[0027] In an electronic device comprising a display apparatus for displaying an image and a processor for controlling the display apparatus according to embodiments of the present disclosure, the display apparatus includes: a display panel including pixels; a data driver providing each pixel with first data bits to k data bits corresponding to grayscale levels, where k is a natural number greater than 2; and a gate driver providing the pixels with a scan signal, a clock signal, and a transmit signal. Each pixel includes: a light-emitting element through which a drive current flows; a light-emitting element driver generating a drive current based on a pulse width modulation signal; and a pulse width modulator generating a pulse width modulation signal based on the first data bits to the k data bits. The pulse width modulator includes: a data writer writing the first data bits to the k data bits in response to a scan signal in the scan signal; a pulse width modulation controller storing the first data bits to the k data bits and sequentially outputting the first data bits to the k data bits in response to a clock signal in the clock signal; and a pulse width modulation signal generator generating the pulse width modulation signal in response to the first data bits to the k data bits and a transmit signal in response to a transmit signal.

[0028] In the pixels of the embodiments, the pulse width modulator can use digital logic to generate pulse width modulation signals, and thus can precisely control the pulse width of the driving current flowing through the light-emitting element, and the pixel can accurately represent gray levels. Furthermore, in the display devices and electronic devices of the embodiments, each pixel can accurately represent gray levels, and therefore, the display quality of the display device can be improved. Attached Figure Description

[0029] The illustrative and non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a circuit diagram illustrating an implementation of the pixel.

[0031] Figure 2 It is shown Figure 1 The timing diagram of the signal of the pixel.

[0032] Figure 3 This is a circuit diagram illustrating an implementation of the pixel.

[0033] Figure 4 This is a circuit diagram illustrating an implementation of the pixel.

[0034] Figure 5 This is a circuit diagram illustrating an implementation of the pixel.

[0035] Figure 6 This is a circuit diagram illustrating an implementation of the pixel.

[0036] Figure 7 This is a circuit diagram illustrating an implementation of the pixel.

[0037] Figure 8 This is a circuit diagram illustrating an implementation of the pixel.

[0038] Figure 9 This is a circuit diagram illustrating an embodiment of a light-emitting element and a light-emitting element driver.

[0039] Figure 10 This is a circuit diagram illustrating an implementation of the pixel.

[0040] Figure 11 This is a circuit diagram illustrating an implementation of the pixel.

[0041] Figure 12 This is a circuit diagram illustrating an implementation of the pixel.

[0042] Figure 13 This is a circuit diagram illustrating an implementation of the pixel.

[0043] Figure 14 This is a circuit diagram illustrating an implementation of the pixel.

[0044] Figure 15 This is a circuit diagram illustrating an implementation of the pixel.

[0045] Figure 16 This is a circuit diagram illustrating an implementation of the pixel.

[0046] Figure 17 This is a circuit diagram illustrating an embodiment of a light-emitting element and a light-emitting element driver.

[0047] Figure 18 This is a circuit diagram illustrating an implementation of the pixel.

[0048] Figure 19 This is a block diagram illustrating an embodiment of the display device.

[0049] Figure 20 This is a block diagram illustrating an implementation of an electronic device.

[0050] Figure 21 It is shown Figure 20 The diagram shows an implementation of an electronic device as a smartwatch. Detailed Implementation

[0051] In the following description, pixels, display devices, and electronic devices in embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals will be used for the same elements.

[0052] What will be understood is that when an element is said to be "on" another element, it can be directly on the other element, or there can be an intervening element between them. Conversely, when an element is said to be "directly" on another element, there is no intervening element.

[0053] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms (which include “at least one”) unless otherwise clearly indicated by the content. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising,” “including,” or “including” and / or “comprising” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0055] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the drawing, the exemplary term “down” can cover both “down” and “up” orientations. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can cover both “up” and “down” orientations.

[0056] Considering the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the values ​​and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, a term such as “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0057] As used herein, terms such as “writer,” “controller,” “signal generator,” and “shifter” are intended to refer to hardware components such as circuitry that perform a predetermined function. Hardware components may include, for example, field-programmable gate arrays (“FPGAs”) or application-specific integrated circuits (“ASICs”).

[0058] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0059] Figure 1 This is a circuit diagram illustrating an implementation of pixel PX. Figure 2 It is shown Figure 1 A timing diagram of the signal of pixel PX. In an implementation, for example, Figure 1 and Figure 2 This can represent a pixel PX located in the nth pixel row and mth pixel column, along with the signal provided to pixel PX. Here, n and m are natural numbers greater than 0.

[0060] refer to Figure 1 and Figure 2 A pixel PX may include a light-emitting element (LED), a light-emitting element driver (LEDD), and a pulse width modulator (PWM).

[0061] Drive current I LED It can flow through the light-emitting element (LED). The LED can emit light with a current I = 1. LED amplitude and drive current I LED The brightness of light corresponds to the pulse width. In this embodiment, the light-emitting element LED can be one of micro light-emitting diodes, organic light-emitting diodes, inorganic light-emitting diodes, and quantum dot light-emitting diodes.

[0062] The LED driver can generate a drive current I based on a pulse width modulation (PWM) signal. LEDThe light-emitting element driver LEDD can include an emitting transistor TD and a current source CS.

[0063] The emitter transistor TD can generate a drive current I in response to the pulse width modulation signal PWMS. LED The current path. Drive current I LED The current path can be formed in the direction from the high-voltage emitter VDD_LED to the low-voltage emitter VSS_LED. The voltage level of the high-voltage emitter VDD_LED can be higher than the voltage level of the low-voltage emitter VSS_LED. The emitter transistor TD can be one of a p-channel metal-oxide-semiconductor (“PMOS”) transistor and an n-channel metal-oxide-semiconductor (“NMOS”) transistor.

[0064] The current source CS can control the drive current I LED The amplitude. The current source CS can generate a drive current I with a constant amplitude. LED .

[0065] In one implementation, the emitting transistor TD can be connected to a line transmitting a high-voltage VDD_LED, the light-emitting element LED can be connected to a line transmitting a low-voltage VSS_LED, and a current source CS can be connected between the emitting transistor TD and the light-emitting element LED. In this configuration, the emitting transistor TD may include a gate for receiving a pulse width modulation signal PWMS, a first electrode for receiving the high-voltage VDD_LED, and a second electrode; the light-emitting element LED may include a first electrode (e.g., an anode) for receiving the low-voltage VSS_LED, and a second electrode (e.g., a cathode); and the current source CS may include a first terminal connected to the second electrode of the emitting transistor TD and a second terminal connected to the first electrode of the light-emitting element LED.

[0066] A pulse width modulator (PWM) can control the drive current I. LED The pulse width. A pulse width modulator (PWM) can generate a pulse width modulation signal PWMS based on the first data bits to the kth data bits (k is a natural number greater than 2). The first data bits to the kth data bits can represent the grayscale levels of the image data. Data bits can have values ​​of 0 or 1. In an implementation, for example, a data bit of 0 can correspond to a logic low level, and a data bit of 1 can correspond to a logic high level.

[0067] In one implementation, the k-th data bit may be the most significant bit (“MSB”) and the first data bit may be the least significant bit (“LSB”). However, this disclosure is not limited thereto, and the MSB may be one of the first data bits to the (k-1)-th data bits, and the LSB may be one of the second data bits to the k-th data bits.

[0068] The following text describes a grayscale range of 0 to 255 (i.e., k is 8).

[0069] A pulse width modulator (PWM) may include a pulse width modulation controller (PWMC), a data writer (DW), and a pulse width modulation signal generator (PWMSG).

[0070] The pulse width modulation controller (PWMC) can store first data bits D0[m] to eighth data bits D7[m], and can sequentially output first data bits D0[m] to eighth data bits D7[m] in response to the clock signal PWM_CLK[n]. The PWMC may include first flip-flops FF1 to eighth flip-flops FF8 and first connection transistors TC1 to eighth connection transistors TC8.

[0071] The first connecting transistor TC1 through the eighth connecting transistor TC8 can connect the first flip-flop FF1 through the eighth flip-flop FF8 in response to the scan signal Scan[n]. The first connecting transistor TC1 can be arranged between the eighth flip-flop FF8 and the first flip-flop FF1. The second connecting transistor TC2 can be arranged between the first flip-flop FF1 and the second flip-flop FF2. The third connecting transistor TC3 can be arranged between the second flip-flop FF2 and the third flip-flop FF3. The fourth connecting transistor TC4 can be arranged between the third flip-flop FF3 and the fourth flip-flop FF4. The fifth connecting transistor TC5 can be arranged between the fourth flip-flop FF4 and the fifth flip-flop FF5. The sixth connecting transistor TC6 can be arranged between the fifth flip-flop FF5 and the sixth flip-flop FF6. The seventh connecting transistor TC7 can be arranged between the sixth flip-flop FF6 and the seventh flip-flop FF7. The eighth connecting transistor TC8 can be arranged between the seventh flip-flop FF7 and the eighth flip-flop FF8. Each of the first connecting transistors TC1 through the eighth connecting transistor TC8 can be one of an n-channel metal-oxide-semiconductor (“NMOS”) transistor, a p-channel metal-oxide-semiconductor (“PMOS”) transistor, and a complementary metal-oxide-semiconductor (“CMOS”) transistor.

[0072] The first flip-flop FF1 to the eighth flip-flop FF8 can shift the first data bit D0[m] to the eighth data bit D7[m] in response to the clock signal PWM_CLK[n]. When the first connecting transistor TC1 to the eighth connecting transistor TC8 are turned on in response to the scan signal Scan[n], the first data bit D0[m] to the eighth data bit D7[m] can be shifted in the direction from the first flip-flop FF1 to the eighth flip-flop FF8 in response to the pulse of the clock signal PWM_CLK[n].

[0073] In this implementation, each of the first flip-flops FF1 to the eighth flip-flops FF8 can be a D flip-flop. In this case, each of the first flip-flops FF1 to the eighth flip-flops FF8 can output an output signal Q and an inverted output signal QB, which is the inverted signal of the output signal Q, wherein the output signal Q is the same as the input data bit D in response to the pulse input of the clock signal PWM_CLK[n]. In this implementation, for example, each of the first flip-flops FF1 to the eighth flip-flops FF8 can output 1 and 0 as the output signal Q and the inverted output signal QB, respectively, when the input data bit D is 1, and can output 0 and 1 as the output signal Q and the inverted output signal QB, respectively, when the input data bit D is 0.

[0074] The data writer DW can write first data bits D0[m] to eighth data bits D7[m] in response to the scan signal Scan[n]. The data writer DW may include first write transistors TW1 to eighth write transistors TW8. First write transistors TW1 to eighth write transistors TW8 can write first data bits D0[m] to eighth data bits D7[m] to first flip-flops FF1 to eighth flip-flops FF8 in response to the scan signal Scan[n]. Each of the first write transistors TW1 to eighth write transistors TW8 can be one of an NMOS transistor, a PMOS transistor, and a CMOS transistor.

[0075] The pulse width modulation signal generator PWMSG can generate a pulse width modulation signal PWMS in response to the first data bit D0[m] to the eighth data bit D7[m] and the transmit signal EM[n].

[0076] The pulse width modulation signal generator PWMSG may include logic gate LG. Logic gate LG may respond to either the eighth output signal Q7 or the eighth inverted output signal QB7 from the eighth flip-flop FF8 (see [link to relevant documentation]). Figure 5 The signal EM[n] is used to generate the pulse width modulation signal PWMS. The logic gate LG can be one of NAND gate, OR gate, NOR gate, and AND gate.

[0077] The first data bits D0[m] to the eighth data bits D7[m] can be written to the first flip-flop FF1 to the eighth flip-flop FF8 at the rising or falling edge of the clock signal PWM_CLK[n] within the activation period PW of the scan signal Scan[n]. The activation period PW of the scan signal Scan[n] can be the period during which the scan signal Scan[n] has an active level. In the implementation, as... Figure 2As shown, the first data bits D0[m] to the eighth data bits D7[m] can be written to the first flip-flop FF1 to the eighth flip-flop FF8 at the rising edge of the internal clock signal PWM_CLK[n] during the activation period PW of the scan signal Scan[n]. In this case, the first output signal Q0 to the eighth output signal Q7 can be the first data bits D0[m] to the eighth data bits D7[m] from the first time point TP1 to the second time point TP2, respectively. However, this disclosure is not limited to this, and in another embodiment, the first data bits D0[m] to the eighth data bits D7[m] can be written to the first flip-flop FF1 to the eighth flip-flop FF8 at the falling edge of the internal clock signal PWM_CLK[n] during the activation period PW of the scan signal Scan[n].

[0078] The first data bits D0[m] to the eighth data bits D7[m] can be shifted between the first flip-flop FF1 to the eighth flip-flop FF8 within the rising or falling edge of the clock signal PWM_CLK[n] during the activation period PE of the transmit signal EM[n]. The activation period PE of the transmit signal EM[n] can be the period during which the transmit signal EM[n] has an activation level. In the implementation, as... Figure 2 As shown, the first data bits D0[m] to the eighth data bits D7[m] can be shifted between the first flip-flop FF1 to the eighth flip-flop FF8 during the rising edge of the clock signal PWM_CLK[n] within the activation period PE of the transmit signal EM[n]. In this case, the first output signal Q0 to the eighth output signal Q7 from the second time point TP2 to the third time point TP3 can be the eighth data bit D7[m] and the first data bits D0[m] to the seventh data bit D6[m], respectively. The first output signal Q0 to the eighth output signal Q7 from the third time point TP3 to the fourth time point TP4 can be the seventh data bit D6[m], the eighth data bit D7[m] and the first data bit D0[m] to the sixth data bit D5[m], respectively. And the first output signal Q0 to the eighth output signal Q7 from the fifth time point TP5 can be the second data bit D1[m] to the eighth data bit D7[m] and the first data bit D0[m].

[0079] The transmit lengths corresponding to the first data bits D0[m] to the eighth data bits D7[m] can be determined by controlling the rising and falling edges of the transmit signal EM[n] and the pulses of the clock signal PWM_CLK[n] within the activation period PE of the transmit signal EM[n]. The transmit lengths corresponding to the first data bits D0[m] to the eighth data bits D7[m] can correspond to the weights of the first data bits D0[m] to the eighth data bits D7[m]. In an implementation, for example, when the eighth data bit D7[m] is MSB and the first data bit D0[m] is LSB, among the transmit lengths corresponding to the first data bits D0[m] to the eighth data bits D7[m], the eighth transmit length EL7 corresponding to the eighth data bit D7[m] can be the largest, and the first transmit length EL0 corresponding to the first data bit D0[m] can be the smallest.

[0080] The transmit length corresponding to each of the first data bit D0[m] and the eighth data bit D7[m] can be the interval between the rising or falling edge of the transmit signal EM[n] and the rising or falling edge of the adjacent (near) rising or falling edge of the transmit signal EM[n] of the clock signal PWM_CLK[n]. In the implementation, as... Figure 2 As shown, the eighth transmit length EL7 corresponding to the eighth data bit D7[m] can be the interval between the rising edge of the transmit signal EM[n] and the rising edge of the adjacent (near) rising edge of the transmit signal EM[n] of the clock signal PWM_CLK[n], and the first transmit length EL0 corresponding to the first data bit D0[m] can be the interval between the falling edge of the transmit signal EM[n] and the rising edge of the adjacent (near) falling edge of the transmit signal EM[n] of the clock signal PWM_CLK[n]. However, this disclosure is not limited thereto, and in another embodiment, when the first data bit D0[m] to the eighth data bit D7[m] are written to the first flip-flop FF1 to the eighth flip-flop FF8 at the falling edge of the clock signal PWM_CLK[n], the eighth transmit length EL7 corresponding to the eighth data bit D7[m] can be the interval between the rising edge of the transmit signal EM[n] and the falling edge of the adjacent (near) rising edge of the transmit signal EM[n] of the clock signal PWM_CLK[n], and the first transmit length EL0 corresponding to the first data bit D0[m] can be the interval between the falling edge of the transmit signal EM[n] and the falling edge of the adjacent (near) falling edge of the transmit signal EM[n] of the clock signal PWM_CLK[n].

[0081] The transmit length corresponding to each of the second data bits D1[m] to the seventh data bits D6[m] can be the interval between adjacent pulses of the clock signal PWM_CLK[n]. In the implementation, as... Figure 2As shown, the seventh transmit length EL6 corresponding to the seventh data bit D6[m] can be the interval between the first and second pulses of the clock signal PWM_CLK[n] within the activation period PE of the transmit signal EM[n], and the sixth transmit length EL5 corresponding to the sixth data bit D5[m] can be the interval between the second and third pulses of the clock signal PWM_CLK[n] within the activation period PE of the transmit signal EM[n].

[0082] The emitter transistor TD can be turned on for a duration corresponding to the sum of the emitter lengths corresponding to the data bits having a logic level of 1, and has a drive current I corresponding to the pulse width corresponding to the sum of the emitter lengths corresponding to the data bits having a logic level of 1. LED It can flow through the light-emitting element LED. Therefore, the driving current I LED The pulse width can be controlled by the gray levels indicated by the first data bit D0[m] to the eighth data bit D7[m], and the light-emitting element LED can emit light with a brightness corresponding to the gray levels indicated by the first data bit D0[m] to the eighth data bit D7[m].

[0083] In the illustrated embodiment of pixel PX, each of the first write transistors TW1 to the eighth write transistors TW8 can be an NMOS transistor, each of the first connection transistors TC1 to the eighth connection transistors TC8 can be a PMOS transistor, the logic gate LG can be a NAND gate, and the emitter transistor TD can be a PMOS transistor. Furthermore, the activation level of the scan signal Scan[n] can be a logic high level, the first write transistors TW1 to the eighth write transistors TW8 can be turned on in response to the activation level of the scan signal Scan[n], the first connection transistors TC1 to the eighth connection transistors TC8 can be turned on in response to the deactivation level of the scan signal Scan[n], the logic gate LG can receive the eighth output signal Q7 from the eighth flip-flop FF8, and the activation level of the emitter signal EM[n] can be a logic high level.

[0084] In the illustrated embodiment, the pulse width modulator (PWM) can use digital logic including first flip-flops FF1 through eighth flip-flops FF8 to generate a pulse width modulation signal PWMS, and therefore, the drive current I flowing through the light-emitting element LED can be precisely controlled. LED The pulse width, and the pixel PX can accurately represent the gray levels indicated by the first data bit D0[m] to the eighth data bit D7[m].

[0085] Figure 3 This is a circuit diagram illustrating an implementation of pixel PX_1.

[0086] References omitted Figure 3 The description of pixel PX_1 and reference Figure 1 and Figure 2 The description of the components of pixel PX is essentially the same as or similar to the description of the components.

[0087] refer to Figure 3 In the illustrated embodiment of pixel PX_1, each of the first connecting transistors TC1 to the eighth connecting transistor TC8 can be an NMOS transistor. Furthermore, the first connecting transistors TC1 to the eighth connecting transistor TC8 can be turned on in response to the activation level of the inverted scan signal ScanB[n]. The inverted scan signal ScanB[n] can be the inverted signal of the scan signal Scan[n].

[0088] Figure 4 This is a circuit diagram illustrating an implementation of pixel PX_2.

[0089] References omitted Figure 4 The description of pixel PX_2 and reference Figure 1 and Figure 2 The description of the components of pixel PX is essentially the same as or similar to the description of the components.

[0090] refer to Figure 4 In the illustrated embodiment of pixel PX_2, each of the first write transistors TW1 to the eighth write transistors TW8 can be a CMOS transistor, and each of the first connection transistors TC1 to the eighth connection transistors TC8 can be a CMOS transistor. Furthermore, the first write transistors TW1 to the eighth write transistors TW8 can be turned on in response to the activation level of the scan signal Scan[n] and the deactivation level of the inverted scan signal ScanB[n], and the first connection transistors TC1 to the eighth connection transistors TC8 can be turned on in response to the activation level of the inverted scan signal ScanB[n] and the deactivation level of the scan signal Scan[n]. The inverted scan signal ScanB[n] can be the inverted signal of the scan signal Scan[n].

[0091] In pixel PX_2 of the illustrated embodiment, each of the first connecting transistors TC1 to the eighth connecting transistors TC8 can be similar to Figure 1 The pixel PX is changed to a PMOS transistor, or it can be similar to... Figure 3 Pixel PX_1 is changed to an NMOS transistor. In pixel PX_2 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 1 The pixel PX is changed to an NMOS transistor.

[0092] Figure 5 This is a circuit diagram illustrating an implementation of pixel PX_3.

[0093] References omitted Figure 5 The described pixel PX_3 and reference Figure 1 and Figure 2 The description of the components of pixel PX is essentially the same as or similar to the description of the components.

[0094] refer to Figure 5 In the illustrated embodiment of pixel PX_3, logic gate LG can be an OR gate. Furthermore, logic gate LG can receive the eighth inverted output signal QB7 from the eighth flip-flop FF8, and the activation level of the transmit signal EM[n] can be a logic low level.

[0095] In pixel PX_3 of the illustrated embodiment, each of the first connecting transistors TC1 to the eighth connecting transistors TC8 can be similar to Figure 3 Pixel PX_1 is changed to an NMOS transistor. In pixel PX_3 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 4 Pixel PX_2 is changed to a CMOS transistor. In pixel PX_3 of the illustrated embodiment, each of the first connecting transistor TC1 to the eighth connecting transistor TC8 can be similar to Figure 4 Pixel PX_2 is changed to a CMOS transistor. In pixel PX_3 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 and the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 4 The pixel PX_2 is changed to a CMOS transistor.

[0096] Figure 6 This is a circuit diagram illustrating an implementation of pixel PX_4.

[0097] Omitted reference Figure 6 The description of pixel PX_4 and reference Figure 1 and Figure 2 The description of the components of pixel PX is essentially the same as or similar to the description of the components.

[0098] refer to Figure 6In the illustrated embodiment of pixel PX_4, each of the first write transistors TW1 to the eighth write transistors TW8 can be a PMOS transistor, and each of the first connection transistors TC1 to the eighth connection transistors TC8 can be an NMOS transistor. Furthermore, the activation level of the scan signal Scan[n] can be a logic low level. When the activation level of the scan signal Scan[n] is a logic low level, the first write transistors TW1 to the eighth write transistors TW8 can be turned on in response to the activation level of the scan signal Scan[n], and the first connection transistors TC1 to the eighth connection transistors TC8 can be turned on in response to the deactivation level of the scan signal Scan[n].

[0099] Figure 7 This is a circuit diagram illustrating an implementation of pixel PX_5.

[0100] References omitted Figure 7 The description of pixel PX_5 and reference Figure 6 The description of the components of pixel PX_4 is substantially the same as or similar to the description of the components.

[0101] refer to Figure 7 In the illustrated embodiment of pixel PX_5, each of the first connecting transistors TC1 to the eighth connecting transistor TC8 can be a PMOS transistor. Furthermore, the first connecting transistors TC1 to the eighth connecting transistor TC8 can be turned on in response to the activation level of the inverted scan signal ScanB[n]. The inverted scan signal ScanB[n] can be the inverted signal of the scan signal Scan[n].

[0102] In pixel PX_5 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 4 Pixel PX_2 is changed to a CMOS transistor. In pixel PX_5 of the illustrated embodiment, each of the first connecting transistor TC1 to the eighth connecting transistor TC8 can be similar to Figure 4 Pixel PX_2 is changed to a CMOS transistor. In pixel PX_5 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 and the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 4 The pixel PX_2 is changed to a CMOS transistor.

[0103] Figure 8 This is a circuit diagram illustrating an implementation of pixel PX_6.

[0104] References omitted Figure 8 The description of pixel PX_6 and reference Figure 6The description of the components of pixel PX_4 is substantially the same as or similar to the description of the components.

[0105] refer to Figure 8 In the illustrated embodiment, pixel PX_6, logic gate LG can be an OR gate. Furthermore, logic gate LG can receive the eighth inverted output signal QB7 from the eighth flip-flop FF8, and the activation level of the transmit signal EM[n] can be logic low. When the activation level of the scan signal Scan[n] is logic low, the first write transistor TW1 to the eighth write transistor TW8 can be turned on in response to the activation level of the scan signal Scan[n], and the first connection transistor TC1 to the eighth connection transistor TC8 can be turned on in response to the deactivation level of the scan signal Scan[n].

[0106] In pixel PX_6 of the illustrated embodiment, each of the first connecting transistors TC1 to the eighth connecting transistors TC8 can be similar to Figure 1 The pixel PX is changed to a PMOS transistor. In the illustrated embodiment of pixel PX_6, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 4 Pixel PX_2 is changed to a CMOS transistor. In pixel PX_6 of the illustrated embodiment, each of the first connecting transistor TC1 to the eighth connecting transistor TC8 can be similar to Figure 4 Pixel PX_2 is changed to a CMOS transistor. In pixel PX_6 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 and the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 4 The pixel PX_2 is changed to a CMOS transistor.

[0107] Figure 9 This is a circuit diagram illustrating an embodiment of a light-emitting element (LED) and a light-emitting element driver (LEDD).

[0108] Figure 9 The connection relationship between the light-emitting element (LED) and the light-emitting element driver (LEDD) can be different. Figure 1 , Figures 3 to 8 The connection relationship between the light-emitting element (LED) and the light-emitting element driver (LEDD).

[0109] refer to Figure 9In one embodiment, the light-emitting element (LED) can be connected to a line transmitting a high-voltage emission VDD_LED, the emitting transistor (TD) can be connected to a line transmitting a low-voltage emission VSS_LED, and a current source (CS) can be connected between the LED and the emitting transistor (TD). In this case, the emitting transistor (TD) may include a gate for receiving a pulse width modulation (PWMS) signal, a first electrode, and a second electrode for receiving the low-voltage emission VSS_LED. The LED may include a first electrode (e.g., anode) and a second electrode (e.g., cathode) for receiving the high-voltage emission VDD_LED, and the current source (CS) may include a first terminal connected to the second electrode of the LED and a second terminal connected to the first electrode of the emitting transistor (TD).

[0110] Figure 10 This is a circuit diagram illustrating an implementation of pixel PX_7.

[0111] References omitted Figure 10 The description of pixel PX_7 and reference Figure 1 and Figure 2 The description of the components of pixel PX is essentially the same as or similar to the description of the components.

[0112] refer to Figure 10 In the illustrated embodiment of pixel PX_7, logic gate LG can be a NOR gate, and the emitter transistor TD can be an NMOS transistor. Furthermore, logic gate LG can receive the eighth inverted output signal QB7 from the eighth flip-flop FF8, and the activation level of the emitter signal EM[n] can be a logic low level.

[0113] Figure 11 This is a circuit diagram illustrating an implementation of pixel PX_8.

[0114] References omitted Figure 11 The described pixel PX_8 and reference Figure 10 The description of the components of pixel PX_7 is substantially the same as or similar to the description of the components.

[0115] refer to Figure 11 In the illustrated embodiment of pixel PX_8, each of the first connecting transistors TC1 to the eighth connecting transistor TC8 can be an n-channel metal-oxide-semiconductor (“NMOS”) transistor. Furthermore, the first connecting transistors TC1 to the eighth connecting transistor TC8 can be turned on in response to the activation level of the inverted scan signal ScanB[n]. The inverted scan signal ScanB[n] can be the inverted signal of the scan signal Scan[n].

[0116] Figure 12 This is a circuit diagram illustrating an implementation of pixel PX_9.

[0117] References omitted Figure 12 The description of pixel PX_9 and reference Figure 10 The description of the components of pixel PX_7 is substantially the same as or similar to the description of the components.

[0118] refer to Figure 12 In the illustrated embodiment of pixel PX_9, each of the first write transistors TW1 to the eighth write transistors TW8 can be a CMOS transistor, and each of the first connection transistors TC1 to the eighth connection transistors TC8 can be a CMOS transistor. Furthermore, the first write transistors TW1 to the eighth write transistors TW8 can be turned on in response to the activation level of the scan signal Scan[n] and the deactivation level of the inverted scan signal ScanB[n], and the first connection transistors TC1 to the eighth connection transistors TC8 can be turned on in response to the activation level of the inverted scan signal ScanB[n] and the deactivation level of the scan signal Scan[n]. The inverted scan signal ScanB[n] can be the inverted signal of the scan signal Scan[n].

[0119] In pixel PX_9 of the illustrated embodiment, each of the first connecting transistor TC1 to the eighth connecting transistor TC8 can be similar to Figure 10 The pixel PX_7 is changed to a PMOS transistor, or it can be similar to... Figure 11 Pixel PX_8 is changed to an NMOS transistor. In pixel PX_9 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 10 The pixel PX_7 was changed to an NMOS transistor.

[0120] Figure 13 This is a circuit diagram illustrating an implementation of pixel PX_10.

[0121] References omitted Figure 13 The described pixel PX_10 and reference Figure 10 The description of the components of pixel PX_7 is substantially the same as or similar to the description of the components.

[0122] refer to Figure 13 In the illustrated embodiment of pixel PX_10, logic gate LG can be an AND gate. Furthermore, logic gate LG can receive the eighth output signal Q7 from the eighth flip-flop FF8, and the activation level of the transmit signal EM[n] can be a logic high level.

[0123] In the illustrated embodiment of pixel PX_10, each of the first connecting transistors TC1 to the eighth connecting transistors TC8 can be similar to Figure 11Pixel PX_8 is changed to an NMOS transistor. In pixel PX_10 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 12 Pixel PX_9 is changed to a CMOS transistor. In pixel PX_10 of the illustrated embodiment, each of the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 12 Pixel PX_9 is changed to a CMOS transistor. In pixel PX_10 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 and the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 12 The pixel PX_9 was changed to a CMOS transistor.

[0124] Figure 14 This is a circuit diagram illustrating an implementation of pixel PX_11.

[0125] Omitted reference Figure 14 The described pixel PX_11 and reference Figure 10 The description of the components of pixel PX_7 is substantially the same as or similar to the description of the components.

[0126] refer to Figure 14 In the illustrated embodiment of pixel PX_11, each of the first write transistors TW1 to the eighth write transistors TW8 can be a PMOS transistor, and each of the first connection transistors TC1 to the eighth connection transistors TC8 can be an NMOS transistor. Furthermore, the activation level of the scan signal Scan[n] can be a logic low level. When the activation level of the scan signal Scan[n] is a logic low level, the first write transistors TW1 to the eighth write transistors TW8 can be turned on in response to the activation level of the scan signal Scan[n], and the first connection transistors TC1 to the eighth connection transistors TC8 can be turned on in response to the deactivation level of the scan signal Scan[n].

[0127] Figure 15 This is a circuit diagram illustrating an implementation of pixel PX_12.

[0128] References omitted Figure 15 The described pixel PX_12 and reference Figure 14 The description of the components of pixel PX_11 is substantially the same as or similar to the description of the components.

[0129] refer to Figure 15In the illustrated embodiment of pixel PX_12, each of the first connecting transistors TC1 to the eighth connecting transistors TC8 can be a PMOS transistor. Furthermore, the first connecting transistors TC1 to the eighth connecting transistors TC8 can be turned on in response to the activation level of the inverted scan signal ScanB[n]. The inverted scan signal ScanB[n] can be the inverted signal of the scan signal Scan[n].

[0130] In the illustrated embodiment of pixel PX_12, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 12 Pixel PX_9 is changed to a CMOS transistor. In pixel PX_12 of the illustrated embodiment, each of the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 12 Pixel PX_9 is changed to a CMOS transistor. In pixel PX_12 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 and the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 12 The pixel PX_9 was changed to a CMOS transistor.

[0131] Figure 16 This is a circuit diagram showing pixel PX_13.

[0132] References omitted Figure 16 The described pixel PX_13 and reference Figure 14 The description of the components of pixel PX_11 is substantially the same as or similar to the description of the components.

[0133] refer to Figure 16 In the illustrated embodiment of pixel PX_13, logic gate LG can be an AND gate. Furthermore, logic gate LG can receive the eighth output signal Q7 from the eighth flip-flop FF8, and the activation level of the transmit signal EM[n] can be a logic high level.

[0134] In pixel PX_13 of the illustrated embodiment, each of the first connecting transistor TC1 to the eighth connecting transistor TC8 can be similar to Figure 10 Pixel PX_7 is changed to a PMOS transistor. In pixel PX_13 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 can be similar to Figure 12 Pixel PX_9 is changed to a CMOS transistor. In pixel PX_13 of the illustrated embodiment, each of the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 12Pixel PX_9 is changed to a CMOS transistor. In pixel PX_13 of the illustrated embodiment, each of the first write transistor TW1 to the eighth write transistor TW8 and the first connection transistor TC1 to the eighth connection transistor TC8 can be similar to Figure 12 The pixel PX_9 was changed to a CMOS transistor.

[0135] Figure 17 This is a circuit diagram illustrating an embodiment of a light-emitting element (LED) and a light-emitting element driver (LEDD).

[0136] Figure 17 The connection relationship between the light-emitting element (LED) and the light-emitting element driver (LEDD) can be different. Figures 10 to 16 The connection relationship between the light-emitting element (LED) and the light-emitting element driver (LEDD).

[0137] refer to Figure 17 In one embodiment, the light-emitting element (LED) can be connected to a line transmitting a high-voltage emission VDD_LED, the emitting transistor (TD) can be connected to a line transmitting a low-voltage emission VSS_LED, and a current source (CS) can be connected between the LED and the emitting transistor (TD). In this case, the emitting transistor (TD) may include a gate for receiving a pulse width modulation (PWMS) signal, a first electrode, and a second electrode for receiving the low-voltage emission VSS_LED. The LED may include a first electrode (e.g., anode) and a second electrode (e.g., cathode) for receiving the high-voltage emission VDD_LED, and the current source (CS) may include a first terminal connected to the second electrode of the LED and a second terminal connected to the first electrode of the emitting transistor (TD).

[0138] Figure 18 This is a circuit diagram illustrating an implementation of pixel PX_14.

[0139] References omitted Figure 18 The described pixel PX_14 and reference Figure 1 and Figure 2 The description of the components of pixel PX is essentially the same as or similar to the description of the components.

[0140] refer to Figure 18 The pulse width modulation signal generator PWMSG may also include a level shifter LS. The level shifter LS can change the voltage level of the pulse width modulation signal PWMS. The level shifter LS can increase or decrease the voltage level of the pulse width modulation signal PWMS output from logic gate LG based on a low voltage VSS and a high voltage VDD, in order to output a compensated pulse width modulation signal PWMS'. The voltage level of the high voltage VDD can be higher than the voltage level of the low voltage VSS.

[0141] Figure 19 This is a block diagram illustrating an embodiment of the display device 100.

[0142] refer to Figure 19 The display device 100 may include a display panel 110, a data driver 120, a gate driver 130, and a controller 140.

[0143] Display panel 110 may include pixels. Figure 19 The pixel PX[n,m] shown can correspond to Figure 1 PX pixels Figure 3 The pixel PX_1, Figure 4 PX_2 pixels Figure 5 PX_3 pixels Figure 6 PX_4 pixels Figure 7 PX_5 pixels Figure 8 PX_6 pixels Figure 10 PX_7 pixels Figure 11 PX_8 pixels Figure 12 PX_9 pixels Figure 13 PX_10 pixels Figure 14 The pixel PX_11, Figure 15 PX_12 pixels Figure 16 PX_13 or Figure 18 The number of pixels is PX_14.

[0144] The data driver 120 can provide each pixel with first to eighth data bits corresponding to the gray level of the second image data IMD2. The data driver 120 can generate the first to eighth data bits based on the gray level of the second image data IMD2 and the first control signal CNT1. The data driver 120 can provide a set of first to eighth data bits to a pixel column. In an embodiment, for example, the data driver 120 can provide the m-th first data bits D0[m] to the eighth data bits D7[m] to the m-th pixel column.

[0145] Gate driver 130 can provide a scan signal, a clock signal, and a transmit signal to a pixel. Gate driver 130 can generate the scan signal, clock signal, and transmit signal based on the second control signal CNT2. Gate driver 130 can provide a scan signal, a clock signal, and a transmit signal to a pixel row. In an embodiment, for example, gate driver 130 can provide the nth scan signal Scan[n], the nth clock signal PWM_CLK[n], and the nth transmit signal EM[n] to the nth pixel row PXR[n].

[0146] Scan signals can be provided sequentially to the pixel rows at horizontal time intervals. In an implementation, for example, the nth scan signal Scan[n] provided to the nth pixel row PXR[n] can be a signal offset from the first scan signal provided to the first pixel row by n-1 horizontal durations.

[0147] In one implementation, each of the clock signal and the transmit signal can be provided sequentially to the pixel row at horizontal time intervals. For example, the nth clock signal PWM_CLK[n] and the nth transmit signal EM[n] provided to the nth pixel row PXR[n] can be signals offset by n-1 horizontal durations from the first clock signal and the first transmit signal provided to the first pixel row, respectively. In this case, the display panel 110 can be driven in a sequential emission manner, emitting light sequentially from pixel row to pixel row.

[0148] In one implementation, the clock signal and the transmit signal can be provided simultaneously to the pixel row. For example, the nth clock signal PWM_CLK[n] and the nth transmit signal EM[n] provided to the nth pixel row PXR[n] can be the same signals as the first clock signal and the first transmit signal provided to the first pixel row, respectively. In this case, the display panel 110 can be driven in a simultaneous emission mode where the pixel rows emit light simultaneously.

[0149] The controller 140 can control the operation (or drive) of the data driver 120 and the gate driver 130. The controller 140 can provide the data driver 120 with second image data IMD2 and a first control signal CNT1, and can provide the gate driver 130 with a second control signal CNT2. The controller 140 can generate the second image data IMD2, the first control signal CNT1, and the second control signal CNT2 based on the first image data IMD1 and the control signal CNT1. The controller 140 can generate the second image data IMD2 by compensating for the first image data IMD1.

[0150] refer to Figure 1 and Figure 19When the display panel 110 displays a still image, the pulse width modulator (PWM) of pixel PX can generate a pulse width modulation signal (PWMS) based on the first data bits D0[m] to the eighth data bits D7[m] stored in the pulse width modulation controller (PWMC) without rewriting the first data bits D0[m] to the eighth data bits D7[m]. When the display panel 110 displays a still image, the grayscale level indicated by the first data bits D0[m] to the eighth data bits D7[m] can be the same for multiple frames, and therefore, the pulse width modulator (PWM) can generate the pulse width modulation signal (PWMS) without rewriting the first data bits D0[m] to the eighth data bits D7[m]. Therefore, the power consumption of pixel PX can be reduced.

[0151] When the display panel 110 is driven by the active matrix organic light-emitting diode pulse driving (“AID”) method, the pulse width modulator (PWM) of the pixel PX can generate a pulse width modulation signal PWMS based on the first data bits D0[m] to the eighth data bits D7[m] stored in the pulse width modulation controller PWMC without rewriting the first data bits D0[m] to the eighth data bits D7[m]. The AID method can be a driving method that includes multiple transmission cycles in a frame. When the display panel 110 is driven by the AID method, the gray levels indicated by the first data bits D0[m] to the eighth data bits D7[m] can be the same during the multiple transmission cycles included in a frame, and therefore, the pulse width modulator PWM can generate the pulse width modulation signal PWMS without rewriting the first data bits D0[m] to the eighth data bits D7[m]. Therefore, the power consumption of the pixel PX can be reduced.

[0152] Figure 20 This is a block diagram illustrating an embodiment of the electronic device 1000. Figure 21 It is shown Figure 20 The diagram shows an implementation of the electronic device 1000 as a smartwatch.

[0153] refer to Figure 20 and Figure 21 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may also include multiple ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0154] In the implementation method, such as Figure 21As shown, the electronic device 1000 can be implemented as a smartwatch. However, this disclosure is not limited thereto, and in another embodiment, the electronic device 1000 can be implemented as a television, mobile phone, video phone, smart board, tablet personal computer (“PC”), vehicle navigation system, laptop computer, head-mounted display, artificial reality (“AR”) device, etc.

[0155] Processor 1010 can perform predetermined calculations or tasks. In embodiments, processor 1010 may be a microprocessor, a central processing unit (“CPU”), or the like. Processor 1010 can be connected to other components via address buses, control buses, data buses, etc. In embodiments, processor 1010 may also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0156] The processor 1010 can control the display device 1060. In one embodiment, the processor 1010 can provide power to the display device 1060. Figure 19 The first image data IMD1 and Figure 19 The control signal CNT0.

[0157] The memory device 1020 can store data required for the operation of the electronic device 1000. In embodiments, for example, the memory device 1020 may include: a non-volatile memory device, such as an erasable programmable read-only memory (“EPROM”), an electrically erasable programmable read-only memory (“EEPROM”), a flash memory, a phase-change random access memory (“PRAM”), a resistive random access memory (“RRAM”), a nano-floating gate memory (“NFGM”), a polymer random access memory (“PoRAM”), a magnetic random access memory (“MRAM”), or a ferroelectric random access memory (“FRAM”); and / or a volatile memory device, such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”), or mobile DRAM.

[0158] Storage device 1030 may include a solid-state drive (“SSD”), a hard disk drive (“HDD”), an optical disc read-only memory (“CD-ROM”), etc. I / O device 1040 may include: input devices such as a keyboard, keypad, touchpad, touchscreen, or mouse; and output devices such as speakers or printers. Power supply 1050 provides the power required for the operation of electronic device 1000. Display device 1060 can be connected to other components via a bus or other communication link. Display device 1060 may correspond to... Figure 19 The display device 100.

[0159] In the pixels included in the display device 1060, a pulse width modulator can generate a pulse width modulation signal using digital logic, and therefore, the pulse width of the driving current flowing through the light-emitting element can be precisely controlled, and the pixel can accurately represent grayscale levels. Furthermore, since each pixel can accurately represent grayscale levels, the display quality of the display device 1060 can be improved.

[0160] The display device described in this embodiment can be applied to display devices including computers, laptops, mobile phones, smartphones, smartboards, smartwatches, portable media players (“PMP”), personal digital assistants (“PDAs”), Moving Picture Experts Group Audio Layer III (“MP3”) players, etc.

[0161] Although the pixels, display devices, and electronic devices in the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims.

Claims

1. A pixel, characterized by, The pixels include: A light-emitting element, through which a driving current flows; A light-emitting element driver generates the driving current based on a pulse-width modulation signal; and A pulse width modulator generates the pulse width modulated signal based on the first data bits to the k-th data bits, where k is a natural number greater than 2, and the pulse width modulator includes: A data writer writes the first data bit to the kth data bit in response to a scan signal; A pulse width modulation controller stores the first data bits up to the k-th data bit, and sequentially outputs the first data bits up to the k-th data bit in response to a clock signal; and A pulse width modulation signal generator generates the pulse width modulation signal in response to the first data bits to the kth data bits and the transmitted signal.

2. The pixel of claim 1, wherein, The pulse width modulation controller includes: The first to the kth flip-flops, in response to the clock signal, shift the first data bit to the kth data bit; and The first connecting transistor to the k-th connecting transistor connects the first flip-flop to the k-th flip-flop in response to the scan signal.

3. The pixel of claim 2, wherein, The first data bit to the kth data bit are written to the first flip-flop to the kth flip-flop at the rising or falling edge of the clock signal during the activation period of the scan signal.

4. The pixel of claim 2, wherein, The first data bit to the kth data bit are shifted between the first flip-flop and the kth flip-flop at the rising or falling edge of the clock signal during the activation period of the transmitted signal.

5. The pixel of claim 2, wherein, The transmit length corresponding to each of the first data bit and the kth data bit is the interval between the rising or falling edge of the transmit signal and the rising or falling edge of the clock signal adjacent to the rising or falling edge of the transmit signal.

6. The pixel of claim 2, wherein, The transmit length corresponding to each of the second to (k-1)th data bits from the first data bit to the kth data bit is the interval between adjacent pulses of the clock signal.

7. The pixel of claim 2, wherein, The data writer includes: The first write transistor to the k-th write transistor write the first data bit to the k-th data bit to the first flip-flop to the k-th flip-flop in response to the scan signal.

8. The pixel according to claim 2, characterized in that, The pulse width modulation signal generator includes: A logic gate that generates the pulse width modulation signal in response to the k-th output signal or the k-th inverted output signal from the k-th flip-flop and the transmit signal.

9. A display device, characterized in that, The display device includes: A display panel, comprising pixels, each of the pixels comprising: A light-emitting element, through which a driving current flows; A light-emitting element driver generates the driving current based on a pulse-width modulation signal; and A pulse width modulator generates the pulse width modulated signal, the pulse width modulator comprising: Data writer; Pulse width modulation controller; and A pulse width modulation signal generator generates the pulse width modulation signal; A data driver provides each of the pixels with first data bits to k-th data bits corresponding to the gray level, where k is a natural number greater than 2; and The gate driver provides the pixel with scan signals, clock signals, and transmit signals. The pulse width modulator generates the pulse width modulated signal based on the first data bits to the k-th data bits. The data writer writes the first data bit to the k-th data bit in response to a scan signal in the scan signal. The pulse width modulation controller stores the first data bits to the k-th data bits, and sequentially outputs the first data bits to the k-th data bits in response to a clock signal in the clock signal. The pulse width modulation signal generator generates the pulse width modulation signal in response to one of the first data bits to the k-th data bits and the transmit signal.

10. An electronic device, characterized in that, The electronic device includes: Display device, for displaying images; and A processor controls the display device, the display device comprising: A display panel, comprising pixels, each of the pixels comprising: A light-emitting element, through which a driving current flows; A light-emitting element driver generates the driving current based on a pulse-width modulation signal; and A pulse width modulator generates the pulse width modulated signal, the pulse width modulator comprising: Data writer; Pulse width modulation controller; and A pulse width modulation signal generator generates the pulse width modulation signal; A data driver provides each of the pixels with first data bits to k-th data bits corresponding to the gray level, where k is a natural number greater than 2; and The gate driver provides the pixel with scan signals, clock signals, and transmit signals. The pulse width modulator generates the pulse width modulated signal based on the first data bits to the k-th data bits. The data writer writes the first data bit to the k-th data bit in response to a scan signal in the scan signal. The pulse width modulation controller stores the first data bits to the k-th data bits, and sequentially outputs the first data bits to the k-th data bits in response to a clock signal in the clock signal. The pulse width modulation signal generator generates the pulse width modulation signal in response to one of the first data bits to the k-th data bits and the transmit signal.

Images