PMOS switching circuit

Abstract

The utility model relates to the field of switching circuits, in particular to a PMOS (P-channel Metal Oxide Semiconductor) switching circuit, which is characterized in that a source electrode of a PMOS tube Q1 is connected with an input voltage end Vi n, and a drain electrode is connected with a load output end Vout; a base electrode of the triode Q2 receives the switching signal through a control signal end PWR, and an emitting electrode of the triode Q2 is grounded; the first divider resistor R1 is connected between the grid electrode of the PMOS tube Q1 and an input voltage end Vi n; the second divider resistor R2 is connected between the grid electrode of the PMOS tube Q1 and the collector electrode of the triode Q2; the first capacitor C1 is connected between the grid electrode and the source electrode of the PMOS tube Q1; the resistance value ratio of the first divider resistor R1 to the second divider resistor R2 is 1: 3 to 1: 5, the capacitance value of the first capacitor C1 is 10 nF to 100 nF, and the load capacitance C2 does not exceed 470 [mu] F. The voltage division ratio of R1 / R2 is matched with the capacitor C1, so that the conduction time of the PMOS is prolonged, the instantaneous charging current peak value of the load capacitor C2 is remarkably reduced, voltage drop is avoided, and the stability of the system is guaranteed.

Description

Technical Field

[0001] This utility model relates to the field of switching circuits, and more particularly to a PMOS switching circuit. Background Technology

[0002] In electronic systems such as power control and motor drives, PMOS transistors are often used as switching devices to achieve power on / off or load control due to their advantages such as low on-state voltage and simple control logic. Traditional PMOS switching circuits mostly use a driving scheme combining voltage divider resistors and transistors, directly adjusting the gate voltage through control signals. However, this approach has the following significant drawbacks in practical applications:

[0003] When a large capacitor (e.g., >1000μF) is connected to the load, the short-circuit charging current at the moment of PMOS turn-on can reach tens of amperes, far exceeding the safe operating area (SOA) of the MOSFET, which can easily lead to thermal breakdown. Existing technologies often address this by increasing the current specification of the MOSFET, resulting in a cost increase of more than 50%.

[0004] The instantaneous current demand of a large capacitor load may exceed the load capacity of the preceding power supply, causing a sudden drop in input voltage, triggering a system reset, or even damaging sensitive components. Traditional solutions use an external soft-start IC for current slope control, but this increases hardware complexity and BOM cost. Improper selection of the voltage divider resistor ratio can cause the gate drive voltage to exceed the safe range, leading to subthreshold conduction of the MOSFET or gate oxide breakdown. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a PMOS switching circuit. The voltage divider ratio of R1 / R2, in conjunction with the gate capacitor C1, extends the PMOS conduction time to the level of hundreds of microseconds, significantly reducing the peak instantaneous charging current of the load capacitor C2. This prevents the input power supply from experiencing a voltage drop exceeding 5% due to instantaneous overload, thus ensuring system stability.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows: a PMOS switching circuit, comprising: a PMOS transistor Q1, whose source is connected to the input voltage terminal Vin and whose drain is connected to the load output terminal Vout; a transistor Q2, whose base receives a switching signal through the control signal terminal PWR and whose emitter is grounded; a first voltage divider resistor R1, connected between the gate of the PMOS transistor Q1 and the input voltage terminal Vin; a second voltage divider resistor R2, connected between the gate of the PMOS transistor Q1 and the collector of the transistor Q2; a first capacitor C1, connected between the gate and the source of the PMOS transistor Q1; and a load capacitor C2, connected between the load output terminal Vout and ground; wherein, the resistance ratio of the first voltage divider resistor R1 to the second voltage divider resistor R2 is 1:3 to 1:5, the capacitance of the first capacitor C1 is 10nF-100nF, and the maximum capacitance of the load capacitor C2 does not exceed 470μF.

[0007] Furthermore, the resistance of the first voltage divider resistor R1 is 10kΩ-50kΩ, and the resistance of the second voltage divider resistor R2 is 30kΩ-150kΩ.

[0008] Furthermore, the capacitance of the first capacitor C1 is specifically 22nF.

[0009] Furthermore, the transistor Q2 is an NPN transistor.

[0010] Furthermore, the breakdown voltage of the PMOS transistor Q1 is not less than 1.5 times the input voltage Vin, and its continuous conduction current capability is more than twice the maximum operating current of the load.

[0011] The beneficial effects of this utility model are as follows:

[0012] 1. The combination of the R1 / R2 voltage divider ratio (1:3 to 1:5) and the gate capacitor C1 (10nF to 100nF) extends the PMOS conduction time to the hundreds of microseconds level, significantly reducing the peak instantaneous charging current of the load capacitor C2 (≤470μF) (e.g., from 40A to below 5A), preventing the input power supply from experiencing a voltage drop of more than 5% due to instantaneous overload, and ensuring system stability.

[0013] 2. The R1 / R2 voltage divider network limits the PMOS gate drive voltage. Combined with the RC slow-start effect of C1, the PMOS conduction process is smooth, the surge current is reduced, and the risk of device thermal failure caused by sudden current changes is avoided.

[0014] 3. Only basic components such as resistors, capacitors, and transistors are required. Reliable control in complex scenarios can be achieved through parameter coordination. Compared with traditional solutions (such as soft-start ICs or high-current power supplies), the cost is reduced by 30% to 50%, making it suitable for cost-sensitive fields such as consumer electronics and motor control. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a PMOS switching circuit. Detailed Implementation

[0016] Please see Figure 1 As shown, this utility model relates to a PMOS switching circuit, comprising:

[0017] PMOS transistor Q1 has its source connected to the input voltage terminal Vin and its drain connected to the load output terminal Vout; transistor Q2 has its base receiving a switching signal through the control signal terminal PWR and its emitter grounded; a first voltage divider resistor R1 is connected between the gate of PMOS transistor Q1 and the input voltage terminal Vin; a second voltage divider resistor R2 is connected between the gate of PMOS transistor Q1 and the collector of transistor Q2; a first capacitor C1 is connected between the gate and the source of PMOS transistor Q1; and a load capacitor C2 is connected between the load output terminal Vout and ground; wherein the resistance ratio of the first voltage divider resistor R1 to the second voltage divider resistor R2 is 1:3 to 1:5, the capacitance of the first capacitor C1 is 10nF-100nF, and the maximum capacitance of the load capacitor C2 does not exceed 470μF.

[0018] The working principle of a voltage divider resistor ratio of 1:3 to 1:5

[0019] When the control signal PWR is high, transistor Q2 is turned on, and the lower end of R2 is grounded. At this time, the gate voltage of PMOS transistor Q1 is determined by the voltage division relationship between R1 and R2: Vgs=-Vin*R1 / (R1+R2)

[0020] If R1 = 10kΩ and R2 = 30kΩ (ratio 1:3), then: Vgs = -0.25Vin; for example, when Vin = 12V, Vgs = -3V. This voltage ensures that the PMOS enters the saturation region (typical PMOS turn-on threshold Vth ≈ -2V), but the drive strength is low (Rds is high), which can limit the rate of rise of the conduction current.

[0021] If R1 = 10kΩ and R2 = 50kΩ (ratio 1:5), then: Vgs = -0.167Vin; for example, when Vin = 12V, Vgs = -2V, which is close to the conduction threshold. At this time, the PMOS is working in the critical conduction state, and Rds increases significantly (for example, from 0.1Ω to 1Ω), further suppressing the surge current.

[0022] Therefore, it can be concluded that the larger the voltage division ratio (e.g., 1:5), the smaller the absolute value of Vgs, the slower the PMOS conduction speed, the higher Rds, and the more limited the surge current peak (I_peak=Vin / Rds).

[0023] For example: when Vgs = -3V, PMOS Rds ≈ 0.1Ω → I_peak = 12V / 0.1Ω = 120A (without other limitations); when Vgs = -2V, Rds ≈ 1Ω → I_peak = 12A. Combined with the capacitance control of C1 (described later), the actual surge current can be further reduced to a safe range (e.g., <5A).

[0024] Further discussion: When R1 = 10kΩ and R2 = 30kΩ (1:3): Static power consumption: 0.3mA (suitable for interference-priority scenarios such as industrial controllers). RC time constant (when C1 = 22nF): τ = (10kΩ / / 30kΩ) × 22nF = 7.5kΩ × 22nF = 165μs. Therefore, in this scheme, the faster conduction speed (τ = 165μs) shortens the charging time of C2, reducing the instantaneous load on the front-end power supply.

[0025] Assuming C2 = 470μF, charging time ≈ 3τ = 500μs → average charging current ≈ (470μF × 12V) / 500μs = 11.3A → requires the pre-amplifier power supply to support short-term high current.

[0026] When R1 = 50kΩ, R2 = 150kΩ (1:5): Static power consumption: 0.06mA (suitable for battery-powered devices). RC time constant: τ = (50kΩ / / 150kΩ) × 22nF = 37.5kΩ × 22nF = 825μs. In this scheme, the slower turn-on speed (τ = 825μs) further reduces the peak current: with the same C2, the average current ≈ (470μF × 12V) / 2.5ms = 2.26A → lower requirements for the pre-amplifier power supply.

[0027] Further discussion reveals that C1, together with the voltage divider resistors R1 and R2, forms an RC low-pass filter circuit, which determines the rise time of the gate voltage (Vg). τ = (R1∥R2) × C1

[0028] For example, when R1 = 10kΩ and R2 = 30kΩ, τ = 10k + 30k = 10k × 30k × 22nF = 7.5kΩ × 22nF = 165μs. The turn-on time is approximately 3τ = 495μs, extending the transition time of the PMOS from cutoff to turn-on to the half-millisecond level. This slows down the rate of change of Vgs and limits the rise slope of the drain current (di / dt). Furthermore, by extending the charging time (t = 3τ), it reduces the instantaneous power demand on the preceding power supply, preventing Vin drop.

[0029] Furthermore, in this application, experimental verification revealed that 22nF is the preferred option for C1. Experimental testing of the effects of different C1 values ​​on surge current and switching losses showed that 22nF is the equilibrium point.

[0030]

[0031]

[0032] The advantages of using a 22nF C1: inrush current is reduced to a safe range (<5A), while switching losses are acceptable (60% reduction compared to a 100nF solution). When used with voltage divider resistors (R1 = 10kΩ-50kΩ), τ = 165μs-825μs, covering the response requirements of common power supply systems.

[0033] Furthermore, if a PNP transistor is used, it needs to conduct when PWR = Low, causing the control logic to reverse, requiring an additional inverter and increasing circuit complexity. In this application, an NPN transistor is used, whose high-level active logic is directly compatible with the MCU output, reducing the risk of false triggering. The switching speed of an NPN transistor (such as 2N3904) (t_switch≈10ns) is much faster than the conduction requirement of a PMOS transistor (μs level), avoiding the impact of delay.

[0034] Additionally, when the PMOS is turned on, the load capacitor C2 needs to be charged quickly to the input voltage Vin. If the capacitance of C2 is too large, the instantaneous current required for charging will exceed the power supply capacity of the preceding stage (such as a battery or voltage regulator), causing Vin to be pulled down briefly, affecting the stability of other parts of the system.

[0035] Therefore, as the capacitance of C2 decreases, the total charge required for charging decreases. For example: (Double the charge) means that a smaller charge reduces the instantaneous power demand of the power supply. Assuming the maximum output current of the pre-amplifier is 5A and the charging time Δt = 500μs: For C2 = 470μF: Iavg = ΔtQ = 500μs 5.64mC = 11.28A (acceptable for short pulses). If C2 = 1000μF: then Iavg = 500μs 12mC = 24A (far exceeding the power supply's capacity, causing a sharp drop in Vin). Actual measurements show that when C2 = 470μF, Vin only drops by 2.5% (12V → 11.7V); while when C2 = 1000μF, Vin may drop by more than 10% (12V → 10.8V), triggering a system reset.

[0036] Simultaneously, the MOSFET needs to carry the charging current of C2 at the moment of conduction. If the current is too large, it may exceed the rated pulse current of the MOSFET, causing the device to overheat or burn out. The peak charging current is: Ipeak = C2 × Δt ΔV (Δt is controlled by the PMOS conduction time). When C2 = 470μF and Δt = 500μs: Ipeak = 470μF × 500μs 12V = 11.28A; if the rated current of the MOSFET is 10A (satisfying a 2x margin), it can safely carry this short-term pulse. The voltage divider resistor (R1 / R2) and the gate capacitor (C1) extend the conduction time of the PMOS (Δt = 500μs), further reducing the current rise slope (di / dt) and avoiding sudden current changes. Example: Without C1, Δt ≈ 50μs → I_peak = 112.8A (dangerous). When C1 = 22nF, Δt = 500μs → I_peak = 11.28A (safe).

[0037] The above embodiments are merely preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model. Various modifications and improvements made to the technical solutions of the present utility model by those skilled in the art without departing from the spirit of the present utility model should fall within the protection scope defined by the claims of the present utility model.

Claims

1. A PMOS switching circuit, characterized in that, include: The PMOS transistor (Q1) has its source connected to the input voltage terminal (Vin) and its drain connected to the load output terminal (Vout). The transistor (Q2) receives a switching signal at its base through the control signal terminal (PWR), and its emitter is grounded. The first voltage divider resistor (R1) is connected between the gate of the PMOS transistor (Q1) and the input voltage terminal (Vin); The second voltage divider resistor (R2) is connected between the gate of the PMOS transistor (Q1) and the collector of the transistor (Q2); The first capacitor (C1) is connected between the gate and source of the PMOS transistor (Q1); The load capacitor (C2) is connected between the load output terminal (Vout) and ground; Wherein, the resistance ratio of the first voltage divider resistor (R1) to the second voltage divider resistor (R2) is 1:3 to 1:5, the capacitance of the first capacitor (C1) is 10nF-100nF, and the maximum capacitance of the load capacitor (C2) does not exceed 470μF.

2. The PMOS switching circuit according to claim 1, characterized in that, The resistance of the first voltage divider resistor (R1) is 10kΩ-50kΩ, and the resistance of the second voltage divider resistor (R2) is 30kΩ-150kΩ.

3. The PMOS switching circuit according to claim 1, characterized in that, The capacitance of the first capacitor (C1) is specifically 22nF.

4. A PMOS switching circuit according to claim 1, characterized in that, The transistor (Q2) is an NPN transistor.

5. A PMOS switching circuit according to claim 1, characterized in that, The breakdown voltage of the PMOS transistor (Q1) is not less than 1.5 times the input voltage (Vin), and its continuous conduction current capability is more than twice the maximum operating current of the load.

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