A board card and electronic equipment

Abstract

This application provides a circuit board and electronic device. The circuit board includes a processor, a PCI bus interface, an ISA bus interface, and a DIP switch. The PCI bus interface and the ISA bus interface are electrically connected to the processor. The PCI bus interface is used to input a first signal to the processor. The ISA bus interface is used to input a second signal to the processor. The first data pin of the DIP switch is used to input a first-level signal to a first configuration pin of the processor. The second data pin of the DIP switch is used to input a second-level signal to a second configuration pin of the processor. When the two level signals are in a first combination state and the processor receives the first signal, the circuit board is in PCI mode. When the two level signals are in a second combination state and the processor receives the second signal, the circuit board is in ISA mode. Thus, the circuit board can be in PCI mode or ISA mode at different times or time periods, improving the circuit board's expandability, compatibility, and applicable scenarios.

Description

Technical Field

[0001] This application relates to the field of circuit board structure design technology, and in particular to a circuit board and electronic device. Background Technology

[0002] Circuit boards are one of the most basic and important power devices in electronic devices. Circuit boards contain various power devices such as processors, bridge chips, BIOS (Basic Input Output System) chips, and memory, forming the main circuit system that controls the operation of electronic devices.

[0003] Currently, the boards on the market either have a PCI (Peripheral Component Interconnect) bus interface and support PCI devices, or an ISA (Industry Standard Architecture) bus interface and support ISA devices. The boards can only be used with one of these bus protocols, which greatly restricts the boards' scalability, compatibility, applicable scenarios, and other performance aspects, making it impossible to meet the usage requirements of multifunctional electronic devices. Utility Model Content

[0004] In view of this, this application provides a board and electronic device to at least solve the problem that existing boards can only use one of the PCI bus protocol or the ISA bus protocol, which limits their performance.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] This application provides a board, including a processor, a PCI bus interface, an ISA bus interface, and a DIP switch; the PCI bus interface and the ISA bus interface are respectively electrically connected to the processor.

[0007] When a PCI device is connected to the PCI bus interface, the PCI bus interface inputs a first signal to the processor; when an ISA device is connected to the ISA bus interface, the ISA bus interface inputs a second signal to the processor.

[0008] The processor includes a first configuration pin and a second configuration pin, and the DIP switch includes a first data pin and a second data pin; the first data pin is electrically connected to the first configuration pin and is used to input a first level signal to the first configuration pin; the second data pin is electrically connected to the second configuration pin and is used to input a second level signal to the second configuration pin.

[0009] When the first level signal and the second level signal are in a first combined state and the processor receives the first signal, the board is in PCI mode; when the first level signal and the second level signal are in a second combined state and the processor receives the second signal, the board is in ISA mode.

[0010] Optionally, when the first level signal and the second level signal are in a third combined state and the processor does not receive the first signal and the second signal, the board is in autonomous mode.

[0011] Optionally, the board also includes a 1553 bus interface; the 1553 bus interface is electrically connected to the processor; when a 1553 device is connected to the 1553 bus interface, the 1553 bus interface provides a third signal to the processor.

[0012] When the first level signal and the second level signal are in a fourth combined state, and the processor receives the third signal, the board is in simplified mode.

[0013] Optionally, the processor includes a first bus pin and a second bus pin, wherein the first bus pin is electrically connected to the PCI bus interface and the second bus pin is electrically connected to the ISA bus interface.

[0014] Optionally, the PCI bus interface is located at the first edge of the board, and the ISA bus interface is located at the second edge of the board; wherein the first edge and the second edge are two adjacent edges of the board.

[0015] Optionally, the PCI bus interface and the ISA bus interface are both stacked pin-type structures.

[0016] Optionally, the board has a through hole extending through the board along its thickness direction, and the processor is detachably installed in the through hole.

[0017] Optionally, the board may also include a peripheral interface electrically connected to the processor, the peripheral interface being used to connect power devices.

[0018] This application also provides an electronic device including any of the aforementioned boards.

[0019] Compared with the prior art, the board and electronic device described in this application have the following advantages:

[0020] The board of this application can be in PCI mode or ISA mode at different times or time periods according to the signal state between the processor, PCI bus interface, ISA bus interface and DIP switch. That is, the board can use one of the PCI bus protocol or ISA bus protocol at different times or time periods, which improves the board's scalability, compatibility and applicable scenarios, and enables the board to meet the usage requirements of multifunctional electronic devices.

[0021] The electronic device of this application has the same or similar advantages as the prior art and the aforementioned boards, which will not be repeated here. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 This is one of the schematic diagrams of the board in the embodiments of this application;

[0024] Figure 2 This is the second schematic diagram of the board in the embodiments of this application;

[0025] Figure 3 This is a simplified schematic diagram of the connections of various interfaces on the board in the embodiments of this application.

[0026] Explanation of reference numerals in the attached figures:

[0027] 1-Board, 10-DIP switch, 101-First data pin, 102-Second data pin, 11-PCI bus interface, 12-ISA bus interface, 13-Processor, 131-First configuration pin, 132-Second configuration pin, 133-First bus pin, 134-Second bus pin, 135-Third bus pin, 14-1553 bus interface, 15-Peripheral interface. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] The terms "comprising," "including," or any other variations thereof used in the specification and claims of this application are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0031] The following detailed description of a circuit board and electronic device provided in this application is provided through specific embodiments.

[0032] This application provides a board 1, Figure 1 and Figure 2 The schematic diagrams of the boards in the embodiments of this application are shown respectively, with reference to Figure 1 and Figure 2 As shown, board 1 includes a processor 13, a PCI bus interface 11, an ISA bus interface 12, and a DIP switch 10; the PCI bus interface 11 and the ISA bus interface 12 are electrically connected to the processor 13 respectively; when the PCI bus interface 11 is connected to a PCI device, the PCI bus interface 11 inputs a first signal to the processor 13; when the ISA bus interface 12 is connected to an ISA device, the ISA bus interface 12 inputs a second signal to the processor 13.

[0033] The processor 13 includes a first configuration pin 131 and a second configuration pin 132, and the DIP switch 10 includes a first data pin 101 and a second data pin 102. The first data pin 101 is electrically connected to the first configuration pin 131 and is used to input a first level signal to the first configuration pin 131. The second data pin 102 is electrically connected to the second configuration pin 132 and is used to input a second level signal to the second configuration pin 132.

[0034] When the first level signal and the second level signal are in a first combination state and the processor 13 receives the first signal, the board 1 is in PCI mode; when the first level signal and the second level signal are in a second combination state and the processor 13 receives the second signal, the board 1 is in ISA mode.

[0035] In this embodiment, board 1 is a PCB (Printed Circuit Board). Board 1 is an indispensable and important component in the electronics field, providing electrical connections and physical support for various electronic components. It also houses integrated circuits for signal transmission and processing. Processor 13 performs functions such as instruction execution, logical operations, and data processing, and is responsible for controlling the normal operation of the entire system on board 1. PCI bus and ISA bus are two important bus standards, primarily used to connect various hardware devices on board 1. PCI bus slots are typically 8-bit or 16-bit, while ISA bus slots are typically 32-bit or 64-bit; the two bus slot types differ. Currently, commercially available circuit boards 1 either have a PCI bus interface 11 supporting PCI devices or an ISA bus interface 12 supporting ISA devices. Circuit boards 1 can only use one of these bus protocols, which significantly restricts their expandability, compatibility, and applicability, failing to meet the needs of multifunctional electronic devices. In this embodiment, the circuit board 1 has both a PCI bus interface 11 and an ISA bus interface 12, both electrically connected to the processor 13. This allows the circuit board 1 to simultaneously support both PCI and ISA devices. When a PCI device is connected to the PCI bus interface 11, the PCI bus interface 11 inputs a first signal to the processor 13. When an ISA bus interface 12 is connected to an ISA device, the ISA bus interface 12 inputs a second signal to the processor 13. The first and second signals can be any type of electrical signal.

[0036] Furthermore, the processor 13 includes a first bus pin 133 and a second bus pin 134. The first bus pin 133 is electrically connected to the PCI bus interface 11, and the second bus pin 134 is electrically connected to the ISA bus interface 12. In other words, the PCI bus interface 11 is electrically connected to the processor 13 through the first bus pin 133, and the ISA bus interface 12 is electrically connected to the processor 13 through the second bus pin 134. When a PCI device is connected to the PCI bus interface 11, a change in the level state of the first bus pin 133 of the processor 13 is triggered, thereby generating a first signal. When an ISA device is connected to the ISA bus interface 12, a change in the level state of the second bus pin 134 of the processor 13 is triggered, thereby generating a second signal. The range of changes in the level states of the first bus pin 133 and the second bus pin 134 is not limited in this embodiment.

[0037] Board 1 includes a DIP switch 10, which typically has a power supply pin (VCC), a ground pin (GND), and one or more data pins. The power supply pin provides the operating voltage for the DIP switch 10, enabling it to function properly. The ground pin provides a reference potential for the circuit, allowing the levels of various signals to be defined with reference to ground potential. The data pins output level signals corresponding to the states of the DIP switch 10. For example, when the DIP switch 10 is to one state, the corresponding pin outputs a low-level signal; when the DIP switch is to another state, the corresponding pin outputs a high-level signal. The high-level and low-level signals are fed back to the processor 13, which uses these signals to determine the corresponding configuration parameters.

[0038] The DIP switch 10 in this embodiment includes a first data pin 101 and a second data pin 102. The processor 13 includes a first configuration pin 131 and a second configuration pin 132. The first data pin 101 is electrically connected to the first configuration pin 131 and is used to input a first level signal to the first configuration pin 131. The second data pin 102 is electrically connected to the second configuration pin 132 and is used to input a second level signal to the second configuration pin 132. According to the above embodiment, the first level signal and the second level signal are high level signals or low level signals. It can be set that when the first configuration pin 131 or the second configuration pin 132 inputs a high level signal, the processor 13 reads the pin state as "1", and when the first configuration pin 131 or the second configuration pin 132 inputs a low level signal, the processor 13 reads the pin state as "0". Thus, according to the level signals of the first configuration pin 131 and the second configuration pin 132, the processor 13 may read four combination states: "00", "01", "10", and "11". Different combination states represent different configuration parameters of the DIP switch 10.

[0039] In this embodiment, when the first and second level signals are in a first combined state and the processor 13 receives the first signal, the board 1 is in PCI mode. For example, the first combined state can correspond to the "00" state read by the processor 13. Therefore, when the processor 13 reads the "00" state and receives the first signal, the board 1 is in PCI mode and performs data transmission and communication according to the PCI bus protocol. When the first and second level signals are in a second combined state and the processor 13 receives the second signal, the board 1 is in ISA mode. For example, the second combined state can correspond to the "01" state read by the processor 13. Therefore, when the processor 13 reads the "01" state and receives the second signal, the board 1 is in ISA mode and performs data transmission and communication according to the ISA bus protocol.

[0040] It should be noted that the DIP switch 10 will only be in one combination of signal levels at any given time or within the same time period, which also means that the board 1 will only be in one operating mode at any given time or within the same time period. Furthermore, for the board 1 to be in PCI mode or ISA mode, two conditions must be met simultaneously: the first signal and the second signal are in a first combination or a second combination, and the processor 13 receives the first signal or the second signal. If the combination of the first signal and the second signal does not match the first signal or the second signal received by the processor 13, the board 1 cannot be in the corresponding PCI mode or ISA mode. For example, in conjunction with the above embodiment, if the processor 13 reads a "00" state but receives the second signal or does not receive the signal, the board cannot be in PCI mode. Alternatively, if the processor 13 reads a "01" state but receives the first signal or does not receive the signal, the board cannot be in ISA mode.

[0041] Therefore, the board 1 of this application can be in PCI mode or ISA mode at different times or time periods by adjusting the signal states between the processor 13, PCI bus interface 11, ISA bus interface 12 and DIP switch 10. That is, the board 1 can be used with either PCI bus protocol or ISA bus protocol at different times or time periods, thereby improving the scalability, compatibility and applicable scenarios of the board 1 and enabling the board 1 to meet the usage requirements of multifunctional electronic devices.

[0042] Optionally, in some embodiments of this application, when the first level signal and the second level signal are in a third combined state and the processor 13 does not receive the first signal and the second signal, the board 1 is in autonomous mode.

[0043] In conjunction with the foregoing embodiments, the third combined state can correspond to the "10" state read by the processor 13. Therefore, when the processor 13 reads the "10" state and does not receive the first and second signals, the board 1 is in autonomous mode. That is, in autonomous mode, the board 1 is not connected to a PCI or ISA device, does not require the main control support of a host computer, and can be controlled by the processor 13 and some storage units.

[0044] Since the DIP switch 10 will only be in one combination of signal levels at the same time or within the same time period, it means that the board 1 will only be in one working mode at the same time or within the same time period. That is, the board 1 can be in PCI mode, ISA mode or autonomous mode at different times or within different time periods.

[0045] Optionally, refer to Figure 2 As shown, in some embodiments of this application, board 1 further includes a 1553 bus interface 14, which is electrically connected to processor 13; when a 1553 device is connected to the 1553 bus interface 14, the 1553 bus interface 14 inputs a third signal to processor 13; when the first level signal and the second level signal are in a fourth combination state and processor 13 receives the third signal, board 1 is in simplified mode.

[0046] In this embodiment, the 1553 bus interface 14 specifically includes: a bus controller (BC) interface, a remote terminal (RT) interface, and a bus monitor (BM) interface. The bus controller is the terminal on the bus that is scheduled to execute and initiate data transmission tasks, and is responsible for controlling the entire data transmission process on the bus. The remote terminal, as a user subsystem connected to the data bus, extracts or receives data under the control of the remote terminal and responds to the instructions of the remote terminal to perform data sending or receiving operations. The bus monitor is mainly used to monitor the information transmission on the bus, record and analyze the data sources on the bus, so as to facilitate system debugging, fault diagnosis, and performance evaluation. Overall, the 1553 bus adopts a bidirectional, dual-redundant dual-bus architecture. When one bus fails, it can automatically switch to the backup bus to ensure uninterrupted communication and effectively resist electromagnetic interference, ensuring data integrity. When the 1553 bus interface 14 is connected to a 1553 device, the 1553 bus interface 14 inputs a third signal to the processor 13. The third signal can be any type of electrical signal.

[0047] Furthermore, the processor 13 may also include a third bus pin 135, which is electrically connected to the 1553 bus interface 14. In other words, the 1553 bus interface 14 is electrically connected to the processor 13 via the third bus pin 135. When a 1553 device is connected to the 1553 bus interface 14, a change in the level state of the third bus pin 135 of the processor 13 is triggered, thereby generating a third signal. The range of the level state change of the third bus pin 135 is not limited in this embodiment.

[0048] When the first level signal and the second level signal are in the fourth combined state and the processor 13 receives the third signal, the board 1 is in the simplified mode. In conjunction with the aforementioned embodiment, the fourth combined state can correspond to the "11" state read by the processor 13. Thus, when the processor 13 reads the "11" state and the processor 13 receives the third signal, the board 1 is in the simplified mode. In the simplified mode, the 1553 device can interact with the board 1 via the 1553 bus.

[0049] Since the DIP switch 10 will only be in one combination of signal levels at the same time or within the same time period, it means that the board 1 will only be in one working mode at the same time or within the same time period. That is, the board 1 can be in one of the following modes at different times or within different time periods: PCI mode, ISA mode, autonomous mode, or simplified mode.

[0050] In summary, the board 1 of this application has a rich set of interfaces, including a PCI bus interface 11, an ISA bus interface 12, and a 1553 bus interface 14. Through these interfaces, the board 1 can have four different operating modes, including PCI mode, ISA mode, autonomous mode, and simplified mode. This allows the board 1 to support different types of host computers, greatly improving its expandability, compatibility, applicability, and other performance aspects, enabling the board 1 to meet the usage needs of more functional electronic devices.

[0051] Optionally, refer to Figure 1 and Figure 2 As shown, in some embodiments of this application, the PCI bus interface 11 is located at the first edge of the board 1, and the ISA bus interface 12 is located at the second edge of the board 1; wherein, the first edge and the second edge are two adjacent edges of the board 1. Specifically, the board 1 is usually a rectangular structure, and the two adjacent edges on the board 1 correspond to two adjacent sides of the rectangular structure. The PCI bus interface 11 is located on one side, and the ISA bus interface 12 is located on the other side. This arrangement makes it easy to distinguish the positions of the PCI bus interface 11 and the ISA bus interface 12, and it is not easy to confuse them when connecting the corresponding devices. At the same time, it will not cause interference and ensure a smooth connection.

[0052] Optionally, in some embodiments of this application, the PCI bus interface 11 and the ISA bus interface 12 are stacked pin-type structures. A pin-type interface consists of two parts: pins and sockets. The pins are typically made of metal and are mostly cylindrical or rectangular in shape, arranged in a certain pattern at the interface end. The socket has a corresponding number and position of holes and contains elastic contact pieces. When a pin is inserted into the socket, the pin and the contact pieces inside the socket make tight contact, achieving an electrical connection between the two components. In this embodiment, the PCI bus interface 11 and the ISA bus interface 12 can be either pin parts or socket parts, depending on whether they are adapted to the structure of the connected PCI and ISA devices. Pin-type interfaces provide a stable connection, are not easily dislodged by external vibration or shaking, ensure the stability of the electrical connection, and are easy to install and remove. Connection is completed simply by aligning the pin with the socket; no special tools are required, facilitating device assembly and maintenance.

[0053] Optionally, in some embodiments of this application, the board 1 has a through hole extending through the board 1 along its thickness direction, and the processor 13 is detachably installed in the through hole. Specifically, multiple high-precision connection holes can be provided around the through hole, and the processor 13 is installed on the board 1 using high-precision screws. This configuration allows for open-shell testing of the processor 13. For example, when the processor 13 malfunctions and the specific cause cannot be determined by conventional external testing methods, open-shell testing allows technicians to directly observe the internal structure of the processor 13, thereby facilitating fault analysis and location of the processor 13, and providing convenience for the repair and maintenance of the board 1.

[0054] Optionally, Figure 3 A simplified schematic diagram of the interface connections on the board in this embodiment is shown. (Refer to...) Figure 2 and Figure 3As shown, in some embodiments of this application, the board 1 further includes a peripheral interface 15, which is electrically connected to the processor 13 and is used to connect power devices. Specifically, the peripheral interface 15 includes a PCM (Pulse Code Modulation) interface, a PPC (PowerPC) interface, a GPIO (General-Purpose Input / Output) interface, a PWM (Pulse Width Modulation) interface, and a UART (Universal Asynchronous Receiver-Transmitter) interface. PCM is mainly used for the processing and transmission of digital audio signals, converting analog audio signals into digital signals through sampling, quantization, and encoding processes for signal storage, processing, and transmission. The PPC interface is used to realize communication and data transmission between the processor 13 and other devices, including connections to memory, peripherals, etc. The GPIO interface can be configured by the user as input or output pins via software for simple digital signal interaction with external devices. The PWM interface is mainly used to generate pulse signals with variable duty cycles, and the operating state of external devices is controlled by changing the duty cycle of the pulse signals. The UART interface is a universal serial data bus, mainly used for serial data transmission between board 1 and external devices. The aforementioned peripheral interface 15 can also be designed as a pin-type structure to simplify the connection method and realize detachable connection between each interface and peripheral components.

[0055] Optionally, refer to Figure 3 As shown in some embodiments of this application, board 1 integrates a JTAG system. The JTAG (Joint Test Action Group) system defines a TAP (Test Access Port) within the device, and uses dedicated JTAG testing tools to test internal nodes. A standard JTAG interface includes four signal lines: Mode Select (TMS), Clock (TCK), Data Input (TDI), and Data Output (TDO). The state machine of the TAP controller changes state through the Mode Select and Clock lines to input data and instructions. JTAG testing allows multiple devices to be connected in series via the JTAG interface, forming a JTAG chain, enabling separate testing of each device.

[0056] Optionally, in some embodiments of this application, the board 1 also integrates an external watchdog controller. The watchdog controller is a circuit module used to monitor the operating status of the system. It can prevent the system from crashing or freezing due to software failures, hardware anomalies, or other reasons, thereby improving the stability and reliability of the system.

[0057] Optionally, in some embodiments of this application, board 1 also integrates Nor Flash (Nor Flash Memory). Nor Flash is a non-volatile memory, meaning data is not lost after power failure. It has random access capability, allowing direct reading of data from any address. It offers fast read speeds and enables rapid code execution, serving as storage for system startup code, the operating system kernel, and other important programs and data requiring fast access. Furthermore, board 1 integrates two Nor Flash chips, enabling redundant data storage.

[0058] Optionally, in some embodiments of this application, the board 1 is also provided with an RS232 (Recommended Standard 232) serial port. The RS232 serial port is an asynchronous serial communication interface standard used to realize serial data transmission between the board 1 and external devices. In addition, the board 1 is also provided with a DC 5V power supply interface, which is connected to a power management circuit and can provide a stable DC 5V voltage to the circuit board.

[0059] This application also provides an electronic device, including the board 1 described in any of the foregoing embodiments. The electronic device includes, but is not limited to, laptops, desktop computers, communication equipment, or industrial computer equipment. The inclusion of the board 1 described in any of the foregoing embodiments in the electronic device helps to improve the performance of the electronic device in various aspects and enrich the functions of the electronic device.

[0060] It should be understood that the phrase "some embodiments" throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0061] Finally, it should be noted that the above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A circuit board, characterized in that, This includes the processor, PCI bus interface, ISA bus interface, and DIP switches; The PCI bus interface and the ISA bus interface are electrically connected to the processor, respectively. When a PCI device is connected to the PCI bus interface, the PCI bus interface inputs a first signal to the processor; When an ISA device is connected to the ISA bus interface, the ISA bus interface provides a second signal to the processor. The processor includes a first configuration pin and a second configuration pin, and the DIP switch includes a first data pin and a second data pin; the first data pin is electrically connected to the first configuration pin and is used to input a first level signal to the first configuration pin; the second data pin is electrically connected to the second configuration pin and is used to input a second level signal to the second configuration pin. When the first level signal and the second level signal are in a first combined state and the processor receives the first signal, the board is in PCI mode; When the first level signal and the second level signal are in a second combined state and the processor receives the second signal, the board is in ISA mode.

2. The board according to claim 1, characterized in that, When the first level signal and the second level signal are in a third combined state and the processor does not receive the first signal and the second signal, the board is in autonomous mode.

3. The circuit board according to claim 2, characterized in that, It also includes a 1553 bus interface; The 1553 bus interface is electrically connected to the processor; When a 1553 device is connected to the 1553 bus interface, the 1553 bus interface provides a third signal to the processor. When the first level signal and the second level signal are in a fourth combined state, and the processor receives the third signal, the board is in simplified mode.

4. The board according to claim 1, characterized in that, The processor includes a first bus pin and a second bus pin, the first bus pin being electrically connected to the PCI bus interface and the second bus pin being electrically connected to the ISA bus interface.

5. The circuit board according to claim 1, characterized in that, The PCI bus interface is located at the first edge of the board, and the ISA bus interface is located at the second edge of the board; The first edge and the second edge are two adjacent edges of the board.

6. The board according to claim 5, characterized in that, The PCI bus interface and the ISA bus interface are both stacked pin-type structures.

7. The board according to claim 1, characterized in that, The board has a through hole that extends through the board along its thickness direction, and the processor is detachably installed in the through hole.

8. The circuit board according to any one of claims 1 to 6, characterized in that, It also includes a peripheral interface, which is electrically connected to the processor and is used to connect power devices.

9. An electronic device, characterized in that, Includes the board as described in any one of claims 1 to 8.

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