buffers, multiplexers, chips, radio frequency transceivers, and electronic devices
By introducing a transmission gate module and a signal processing module into the buffer, the influence of the input signal on the output is isolated, solving the problems of signal quality degradation and noise performance deterioration, and achieving signal quality improvement and noise performance optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2025-04-22
- Publication Date
- 2026-06-12
AI Technical Summary
In existing technologies, the design of buffers cannot completely isolate the influence of input signals on the output impedance, resulting in a decrease in signal quality and a deterioration in noise performance.
A transmission gate module is set at the signal input terminal of the buffer to transmit or block the input signal. The signal processing module generates an output signal or enters a high-impedance state according to the state of the transmission gate module, thus isolating the input signal from the impedance of the buffer output terminal.
It improves signal quality, optimizes image rejection ratio and noise performance, and ensures the stability and independence of the signal processing module.
Smart Images
Figure CN224356097U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and more particularly to a buffer, multiplexer, chip, radio frequency transceiver, and electronic device. Background Technology
[0002] In related technologies, to achieve precise control of the signal path and reduce static power consumption, switches are typically added to both the power supply and ground terminals of the buffer to control its on and off states. However, this design cannot completely isolate the influence of the input signal on the output impedance of the buffer, leading to a decrease in the quality of subsequent signals and a deterioration in image rejection ratio and noise performance. Utility Model Content
[0003] This application provides a buffer, a multiplexer, a chip, an RF transceiver, and an electronic device. The technical solution of this application is as follows:
[0004] The first aspect of this application provides a buffer, comprising:
[0005] A transmission gate module, wherein the input end of the transmission gate module serves as the receiving end of the input signal, and the transmission gate module is used to transmit or block the input signal;
[0006] A signal processing module, the input of which is connected to the output of the transmission gate module, is used to generate and send a corresponding output signal or enter a high-impedance state according to the state of the transmission gate module.
[0007] A second aspect of this application provides a multiplexer comprising: a plurality of buffers as described above, wherein the plurality of buffers are connected in parallel.
[0008] A third aspect of this application provides a chip including a multiplexer as described above.
[0009] A fourth aspect of this application provides a radio frequency transceiver, including: a multiplexer as described above.
[0010] A fifth aspect of this application provides an electronic device, characterized in that it includes: a buffer as described above.
[0011] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:
[0012] The buffer in this embodiment includes a transmission gate module and a signal processing module. The input terminal of the transmission gate module serves as the receiving terminal for the input signal, and the transmission gate module is used to transmit or block the input signal. The input terminal of the signal processing module is connected to the output terminal of the transmission gate module, and the signal processing module is used to generate and send a corresponding output signal or enter a high-impedance state based on the state of the transmission gate module. By setting a transmission gate module at the signal input terminal for transmitting or blocking the input signal, the buffer in this application can effectively isolate the influence of the input signal on the impedance of the buffer's output terminal, thereby improving the quality of subsequent signals and optimizing the image rejection ratio and noise performance.
[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.
[0015] Figure 1 This is a schematic diagram of a buffer according to an embodiment of this application;
[0016] Figure 2 This is a schematic diagram of a buffer used for transmitting input signals according to an embodiment of this application;
[0017] Figure 3 This is a schematic diagram of a buffer used to block an input signal according to an embodiment of this application;
[0018] Figure 4 This is a schematic diagram of a multiplexer according to one embodiment of this application;
[0019] Figure 5 This is a schematic diagram of a radio frequency transceiver according to an embodiment of this application. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0021] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0022] The buffers, multiplexers, chips, radio frequency transceivers, and electronic devices according to embodiments of this application are described below with reference to the accompanying drawings.
[0023] Figure 1 This is a schematic diagram of a buffer according to an embodiment of this application.
[0024] like Figure 1 As shown, the buffer 100 in this embodiment of the application includes a transmission gate module 110 and a signal processing module 120.
[0025] The input terminal of the transmission gate module 110 serves as the receiving terminal for the input signal, and is used to transmit or block the input signal. The input terminal of the signal processing module 120 is connected to the output terminal of the transmission gate module 110, and the signal processing module 120 is used to generate and send a corresponding output signal or enter a high-impedance state according to the state of the transmission gate module 110.
[0026] In this embodiment, when the state of the transmission gate module 110 is to allow the input signal to pass, the signal processing module 120 will receive a valid input signal and generate a corresponding output signal based on the received input signal.
[0027] When the state of the transmission gate module 110 is not allowed to allow input signals to pass, the signal processing module 120 enters a high-impedance state. This means that the signal processing module 120 will not receive any valid signals from the transmission gate module 110, and its input terminal is equivalent to a disconnected state. In this case, the signal processing module 120 may not generate and output any output signal, which can effectively isolate the influence of the input signal on the impedance of the output terminal of the buffer 100.
[0028] Therefore, the buffer of this application can effectively isolate the influence of the input signal on the impedance of the buffer output by setting a transmission gate module at the signal input end for transmitting or blocking the input signal, thereby improving the quality of the subsequent signal and optimizing the image rejection ratio and noise performance.
[0029] like Figure 1As shown, the transmission gate module 110 in this embodiment includes a first transmission gate unit 111 and a second transmission gate unit 112; wherein,
[0030] The first input terminal of the first transmission gate unit 111 and the first input terminal of the second transmission gate unit 112 are connected to serve as the input terminal of the transmission gate module 110 for receiving input signals.
[0031] The output terminal of the first transmission gate unit 111 serves as the first output terminal of the transmission gate module 110 and is connected to the first input terminal of the signal processing module 120.
[0032] The output terminal of the second transmission gate unit 112 serves as the second output terminal of the transmission gate module 110 and is connected to the second input terminal of the signal processing module 120.
[0033] like Figure 1 As shown, the first transmission gate unit 111 in this embodiment includes: a first transistor M1 and a second transistor M2; wherein,
[0034] The first terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, serving as the input terminal of the first transmission gate unit 111;
[0035] The control terminal of the first transistor M1 is used to receive the enable control signal;
[0036] The control terminal of the second transistor M2 is used to receive the inverted signal of the enable control signal;
[0037] The second terminal of the first transistor M1 is connected to the second terminal of the second transistor M2, serving as the output terminal of the first transmission gate unit 111.
[0038] like Figure 1 As shown, the second transmission gate unit 112 in this embodiment includes: a third transistor M3 and a fourth transistor M4; wherein,
[0039] The first terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4, serving as the input terminal of the second transmission gate unit 112;
[0040] The control terminal of the third transistor M3 is used to receive the enable control signal;
[0041] The control terminal of the fourth transistor M4 is used to receive the inverted signal of the enable control signal;
[0042] The second terminal of the third transistor M3 is connected to the second terminal of the fourth transistor M4, serving as the output terminal of the second transmission gate unit 112.
[0043] like Figure 1As shown, the signal processing module 120 of this embodiment includes: a fifth transistor M5 and a sixth transistor M6; wherein,
[0044] The control terminal of the fifth transistor M5 serves as the first input terminal of the signal processing module 120.
[0045] The control terminal of the sixth transistor M6 serves as the second input terminal of the signal processing module 120.
[0046] The first terminal of the fifth transistor M5 is connected to the power supply terminal VDD, and the first terminal of the sixth transistor M6 is connected to the ground terminal.
[0047] The second terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6, serving as the output terminal of the signal processing module 120.
[0048] like Figure 1 As shown, the signal processing module 120 in this embodiment of the application further includes:
[0049] The seventh transistor M7 has a control terminal that receives an enable control signal. The first terminal of the seventh transistor M7 is connected to the power supply terminal VDD, and the second terminal of the seventh transistor M7 is connected to the control terminal of the fifth transistor M5.
[0050] The eighth transistor M8 has a control terminal that receives the inverted enable control signal. The first terminal of the eighth transistor M8 is connected to the ground terminal, and the third terminal of the eighth transistor M8 is connected to the control terminal of the sixth transistor M6.
[0051] Among them, the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are all one type of MOS transistor, either NMOS or PMOS; the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are all another type of MOS transistor, either NMOS or PMOS.
[0052] For ease of explanation, we will use an example where the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are all NMOS transistors, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are all PMOS transistors. The first terminal of each transistor is its source, the second terminal is its drain, and the control terminal is its gate.
[0053] When the enable control signal En is high, the inverted signal En_b of the enable control signal En is low. Figure 1 The working principle diagram of the buffer 100 shown is as follows: Figure 2 As shown:
[0054] The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all in the on state, causing the first control gate unit 111 and the second control gate unit 112 to close; the fifth transistor M5 and the sixth transistor M6 form an inverter; the seventh transistor M7 and the eighth transistor M8 are turned off.
[0055] In this state, the input signal can pass through normally. Specifically, if the input signal is high, the fifth transistor M5 is off and the sixth transistor M6 is on, resulting in a low-level output signal; if the input signal is low, the fifth transistor M5 is on and the sixth transistor M6 is off, resulting in a high-level output signal.
[0056] When the enable control signal En is low, the inverted signal En_b of the enable control signal En is high. Figure 1 The working principle diagram of the buffer 100 shown is as follows: Figure 3 As shown:
[0057] The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all in the off state, so that the first control gate unit 111 and the second control gate unit 112 are disconnected; the seventh transistor M7 and the eighth transistor M8 are turned on.
[0058] In this state, when the seventh transistor M7 is on, the fifth transistor M5 is off; when the eighth transistor M8 is on, the sixth transistor M6 is off. That is, the gate voltages of the fifth transistor M5 and the sixth transistor M6 are clamped by the corresponding seventh transistor M7 and eighth transistor M8, preventing the input signal from being transmitted to the gates of the fifth transistor M5 and the sixth transistor M6. This ensures that the states of the fifth transistor M5 and the sixth transistor M6 remain stable, allowing the signal processing module 120 to enter a high-impedance state. This means that the impedance of the output of the signal processing module 120 is unaffected by the input signal, effectively blocking any unnecessary signal transmission or interference.
[0059] like Figure 1 As shown, the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are all MOS transistors of one type, either NMOS or PMOS; the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are all MOS transistors of another type, either NMOS or PMOS.
[0060] In summary, the buffer of this application embodiment includes a transmission gate module and a signal processing module. The input terminal of the transmission gate module serves as the receiving terminal of the input signal, and the transmission gate module is used to transmit or block the input signal. The input terminal of the signal processing module is connected to the output terminal of the transmission gate module, and the signal processing module is used to generate and send a corresponding output signal or enter a high-impedance state based on the state of the transmission gate module. By setting a transmission gate module at the signal input terminal for transmitting or blocking the input signal, the buffer of this application can effectively isolate the influence of the input signal on the impedance of the buffer's output terminal, thereby improving the quality of subsequent signals and optimizing the image rejection ratio and noise performance.
[0061] Based on the above embodiments, this application also proposes a multiplexer.
[0062] Figure 4 This is a schematic diagram of a multiplexer according to an embodiment of this application.
[0063] like Figure 4 As shown, the multiplexer 1000 of this application embodiment includes: a plurality of buffers 100, such as buffer 1, buffer 2, buffer 3, ..., buffer n.
[0064] Buffers 1, 2, 3, ..., n are connected in parallel. The input terminal of buffer 1 is input signal 1, the input terminal of buffer 2 is input signal 2, the input terminal of buffer 3 is input signal 3, ..., the input terminal of buffer n is input signal N.
[0065] The multiplexer 1000 can transmit different input signals to the output terminal according to the selection of the control signal, thereby realizing functions such as data selection and signal switching.
[0066] It should be noted that for details not disclosed in the multiplexer 1000 of this application embodiment, please refer to the description of the buffer 100 in this application embodiment, which will not be repeated here.
[0067] The multiplexer in this application embodiment connects multiple buffers in parallel. After the multiple buffers are connected in parallel, each buffer independently processes its own input signal, thereby avoiding interference from other input signals on the output impedance of a single buffer. This design ensures the independence between the input signals and improves the stability and reliability of the system. Since the input signals are effectively isolated and not affected by other signals, noise and distortion in subsequent signal paths are significantly reduced, thereby improving the overall signal quality. By effectively isolating the input signals, crosstalk and noise coupling are reduced, further optimizing the image rejection ratio and overall noise performance.
[0068] Based on the above embodiments, this application also proposes a chip that includes the above-described multiplexer.
[0069] In the embodiments of this application, the chip can be an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Such a chip is suitable for a variety of radio frequency applications, such as WIFI (Wireless Fidelity), Bluetooth, GPS (Global Positioning System) and other radio frequency chips.
[0070] Based on the above embodiments, this application also proposes a radio frequency transceiver.
[0071] Figure 5 This is a schematic diagram of a radio frequency transceiver according to an embodiment of this application.
[0072] like Figure 5 As shown, the radio frequency transceiver 10000 of this application embodiment includes: a plurality of multiplexers 1000, such as a first multiplexer 1100 and a second multiplexer 1200.
[0073] The first multiplexer 1100 is connected to the first mixer 2003 in the receiving path. The second multiplexer 1200 is connected to the second mixer 2009 in the transmitting path.
[0074] like Figure 5 As shown, the radio frequency transceiver 10000 of this application embodiment further includes:
[0075] Multiple phase-locked loops 2012, such as phase-locked loop 1, ..., phase-locked loop N. The multiple phase-locked loops 2012 are arranged between the first multiplexer 1100 and the second multiplexer 1200 to provide a stable frequency reference signal.
[0076] like Figure 5 As shown, the receiving path of the radio frequency transceiver 10000 in this embodiment includes:
[0077] The receiving antenna 2001 is used to receive electromagnetic wave signals and transmit them to subsequent modules.
[0078] The low-noise amplifier 2002 is used to amplify received signals to improve the signal-to-noise ratio.
[0079] During the receiving process, the first multiplexer 1100 selects a suitable input signal according to the control signal to ensure that the received high-frequency signal can be correctly transmitted to the first mixer 2003.
[0080] The first mixer 2003 is used to convert high-frequency signals into lower-frequency intermediate-frequency signals.
[0081] The first low-pass filter 2004 is used to filter out high-frequency components generated during the mixing process and retain the useful signal.
[0082] Analog-to-digital converter 2005 is used to convert analog signals into digital signals.
[0083] The digital baseband processor 2006 is used to process and decode digital signals to extract useful information.
[0084] like Figure 5 As shown, the transmission path of the radio frequency transceiver 10000 in this embodiment includes:
[0085] The digital-to-analog converter 2007 is used to convert digital signals into analog signals.
[0086] The second low-pass filter 2008 is used to filter out high-frequency noise generated during digital-to-analog conversion.
[0087] During transmission, the second multiplexer 1200 selects the appropriate signal path according to the control signal to ensure that the signal generated by the digital baseband processor 2006 can be correctly transmitted to the second mixer 2009.
[0088] The second mixer 2009 is used to modulate low-frequency signals to the desired radio frequency band.
[0089] Power amplifier 2010 is used to amplify the modulated signal for transmission through transmitting antenna 2011.
[0090] The transmitting antenna 2011 is used to transmit the amplified radio frequency signal.
[0091] The RF transceiver of this application embodiment, by using the aforementioned multiplexer, can dynamically select different input or output paths according to the control signal, thereby adapting to various operating modes and frequency ranges. This allows the RF transceiver to flexibly switch between different communication standards (such as Wi-Fi, Bluetooth, GPS, etc.). By accurately selecting the signal path, the multiplexer can reduce signal loss and interference, improve the quality of the received signal and the stability of the transmitted signal. In addition, the multiplexer, when used in conjunction with a phase-locked loop, can provide a more stable frequency reference signal, further optimizing system performance. Using a multiplexer can integrate multiple functional modules and reduce the need for external components, thereby simplifying the overall circuit design. This integrated design not only reduces the complexity of the system but also lowers manufacturing costs.
[0092] Based on the above embodiments, this application also proposes an electronic device that includes the buffer described above.
[0093] In embodiments of this application, the electronic device may be a vehicle, mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, air conditioner, etc.
[0094] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0095] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0096] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the utility models disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.
[0097] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A buffer, characterized in that, include: A transmission gate module, wherein the input end of the transmission gate module serves as the receiving end of the input signal, and the transmission gate module is used to transmit or block the input signal; A signal processing module, the input of which is connected to the output of the transmission gate module, is used to generate and send a corresponding output signal or enter a high-impedance state according to the state of the transmission gate module.
2. The buffer according to claim 1, characterized in that, The transmission gate module includes a first transmission gate unit and a second transmission gate unit; wherein... The first input terminal of the first transmission gate unit and the first input terminal of the second transmission gate unit are connected to serve as the input terminal of the transmission gate module for receiving the input signal; The output terminal of the first transmission gate unit serves as the first output terminal of the transmission gate module and is connected to the first input terminal of the signal processing module. The output terminal of the second transmission gate unit serves as the second output terminal of the transmission gate module and is connected to the second input terminal of the signal processing module.
3. The buffer according to claim 2, characterized in that, The first transmission gate unit includes: a first transistor and a second transistor; wherein, The first terminal of the first transistor is connected to the first terminal of the second transistor, serving as the input terminal of the first transmission gate unit; The control terminal of the first transistor is used to receive an enable control signal; The control terminal of the second transistor is used to receive the inverted signal of the enable control signal; The second terminal of the first transistor is connected to the second terminal of the second transistor, serving as the output terminal of the first transmission gate unit.
4. The buffer according to claim 2, characterized in that, The second transmission gate unit includes: a third transistor and a fourth transistor; wherein, The first terminal of the third transistor is connected to the first terminal of the fourth transistor, serving as the input terminal of the second transmission gate unit; The control terminal of the third transistor is used to receive an enable control signal; The control terminal of the fourth transistor is used to receive the inverted signal of the enable control signal; The second terminal of the third transistor is connected to the second terminal of the fourth transistor, serving as the output terminal of the second transmission gate unit.
5. The buffer according to claim 1, characterized in that, The signal processing module includes: a fifth transistor and a sixth transistor; wherein, The control terminal of the fifth transistor serves as the first input terminal of the signal processing module. The control terminal of the sixth transistor serves as the second input terminal of the signal processing module. The first terminal of the fifth transistor is connected to the power supply terminal, and the first terminal of the sixth transistor is connected to the ground terminal; The second terminal of the fifth transistor is connected to the second terminal of the sixth transistor, serving as the output terminal of the signal processing module.
6. The buffer according to claim 5, characterized in that, The signal processing module further includes: The seventh transistor has a control terminal for receiving an enable control signal, a first terminal of the seventh transistor connected to the power supply terminal, and a second terminal of the seventh transistor connected to the control terminal of the fifth transistor. The eighth transistor has a control terminal for receiving the inverted signal of the enable control signal, a first terminal of the eighth transistor connected to the ground terminal, and a third terminal of the eighth transistor connected to the control terminal of the sixth transistor.
7. The buffer according to any one of claims 3-6, characterized in that, in, The first transistor, the third transistor, the sixth transistor, and the eighth transistor are all MOS transistors of either NMOS or PMOS types; The second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are all alternative types of MOS transistors, either NMOS or PMOS.
8. A multiplexer, characterized in that, include: Multiple buffers as described in any one of claims 1-7, wherein the multiple buffers are connected in parallel.
9. A chip, characterized in that, include: The multiplexer as described in claim 8.
10. A radio frequency transceiver, characterized in that, include: The multiplexer as described in claim 8.
11. An electronic device, characterized in that, include: The buffer as described in any one of claims 1-7.