Bandgap reference circuit, chip and electronic device

Abstract

The embodiment of the application provides a band gap reference circuit, a chip and an electronic device, the band gap reference circuit comprises a voltage adjusting module and a mirror output module, the voltage adjusting module reduces the voltage of a first node in the case that the voltage of a second node increases, the mirror output module reduces the voltage of the second node in the case that the voltage of the first node decreases, through such a cycle feedback, the voltage of the second node tends to be stable, thereby the voltage of the first node is stabilized, and further, the reference voltage generated based on the voltage of the first node is also stabilized, the phenomenon of excessively high reference voltage is avoided, and the stability is improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a bandgap reference circuit, chip, and electronic device. Background Technology

[0002] Bandgap reference circuits provide a highly stable reference source for electronic systems through temperature compensation mechanisms, and can be used to generate reference voltages with near-zero temperature coefficients.

[0003] However, the aforementioned reference voltage is prone to being higher than the target voltage, resulting in an excessively high reference voltage and reduced stability. Utility Model Content

[0004] In view of the above problems, embodiments of this application provide a bandgap reference circuit, chip, and electronic device to alleviate the aforementioned technical problems.

[0005] In a first aspect, embodiments of this application provide a bandgap reference circuit, which includes a voltage adjustment module and a mirror output module. The voltage adjustment module includes a first node and is used to adjust the voltage of the first node in the reverse direction according to the voltage of the second node. The mirror output module includes the second node and is connected to the first node. The mirror output module is used to adjust the voltage of the second node in the same direction according to the voltage of the first node and generate a reference voltage based on the voltage of the first node.

[0006] Secondly, embodiments of this application also provide a chip that includes the bandgap reference circuit described above.

[0007] Thirdly, embodiments of this application also provide an electronic device, which includes the above-described bandgap reference circuit or chip.

[0008] The bandgap reference circuit, chip, and electronic device provided in this application embodiment reduce the voltage of the first node when the voltage of the second node increases through a voltage adjustment module, and reduce the voltage of the second node when the voltage of the first node decreases through a mirror output module. This cyclic feedback can stabilize the voltage of the second node, thereby stabilizing the voltage of the first node, and consequently stabilizing the reference voltage generated based on the voltage of the first node, avoiding the phenomenon of excessively high reference voltage and improving stability.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A first schematic block diagram of the bandgap reference circuit provided in an embodiment of this application is shown.

[0012] Figure 2 A block diagram of the voltage regulation module is shown.

[0013] Figure 3 The circuit schematic of the first mirror unit and the voltage regulation unit is shown.

[0014] Figure 4 The first principle block diagram of the mirror output module is shown.

[0015] Figure 5 The circuit diagram of the first mirror branch is shown.

[0016] Figure 6 The first principle block diagram of the second mirror branch is shown.

[0017] Figure 7 The circuit schematic of the second mirror unit is shown.

[0018] Figure 8 The circuit schematic of the third mirror unit is shown.

[0019] Figure 9 The second circuit schematic of the second mirror branch is shown.

[0020] Figure 10 A second schematic diagram of the bandgap reference circuit provided in an embodiment of this application is shown.

[0021] Figure 11 The schematic diagram of the clamping module is shown.

[0022] Figure 12 The circuit schematic of the gating unit is shown.

[0023] Figure 13 The circuit schematic of the clamping unit is shown.

[0024] Figure 14 The circuit schematic of the startup module is shown.

[0025] Figure 15 A schematic diagram of the chip structure provided in an embodiment of this application is shown.

[0026] Figure 16 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0027] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0030] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0032] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0033] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0034] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0035] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0036] In related technologies, bandgap reference structures use current mirrors to clamp voltages at certain locations. However, these current mirrors need to operate in the saturation region, requiring higher minimum operating voltages, which contradicts the current trend of increasingly lower chip operating voltages. Furthermore, the reference voltage is prone to exceeding the target voltage, resulting in an excessively high reference voltage.

[0037] Based on this, embodiments of this application provide a bandgap reference circuit 100, such as... Figure 1As shown, the voltage regulation module 10 and the mirror output module 20 in the bandgap reference circuit 100 utilize transistors to generate positive temperature coefficient current. This positive temperature coefficient current is then mirrored onto a resistor to generate a positive temperature coefficient voltage, which is then superimposed with a negative temperature coefficient voltage to ultimately output a zero-temperature coefficient reference voltage VOUT. Because current mirror clamping is not used, but rather the positive temperature coefficient current directly generated by the transistor (NPN device) is employed, the required operating voltage is lower. Furthermore, during startup, the voltage regulation module 10 clamps and limits the current in the output branch, reducing or even eliminating the overshoot (excessive) phenomenon of the reference voltage VOUT.

[0038] This application provides a bandgap reference circuit 100. Please refer to [link to relevant documentation]. Figures 1 to 15 ,like Figure 1 As shown, the bandgap reference circuit 100 includes a voltage adjustment module 10 and a mirror output module 20. The voltage adjustment module 10 includes a first node VBP and is used to adjust the voltage of the first node VBP in the reverse direction according to the voltage of the second node VB. The mirror output module 20 includes a second node VB and is connected to the first node VBP. The mirror output module 20 is used to adjust the voltage of the second node VB in the same direction according to the voltage of the first node VBP and generate a reference voltage VOUT based on the voltage of the first node VBP.

[0039] It is understood that the bandgap reference circuit 100 provided in this application embodiment reduces the voltage of the first node VBP when the voltage of the second node VB increases, and reduces the voltage of the second node VB when the voltage of the first node VBP decreases. Through such cyclic feedback, the voltage of the second node VB can be stabilized, thereby stabilizing the voltage of the first node VBP, and further stabilizing the reference voltage VOUT generated based on the voltage of the first node VBP, avoiding the phenomenon of excessively high reference voltage VOUT and improving stability.

[0040] In some of these embodiments, such as Figure 2 As shown, the voltage regulation module 10 includes a first mirror unit 11 and a voltage regulation unit 12. The first mirror unit 11 is connected to the power supply terminal VDD and the first node VBP. The voltage regulation unit 12 is connected to the second node VB and the first mirror unit 11. The voltage regulation unit 12 is used to reversely adjust the voltage of the first node VBP according to the voltage of the second node VB.

[0041] It should be noted that the first mirror unit 11 is used to generate a first current based on the voltage of the first node VBP. Reverse regulation means that when the voltage amplitude of the second node VB increases, the voltage amplitude of the first node VBP decreases; or, when the voltage amplitude of the second node VB decreases, the voltage amplitude of the first node VBP increases.

[0042] In some of these embodiments, such as Figure 3 As shown, the first mirror unit 11 includes a first transistor PM3. The first terminal of the first transistor PM3 is connected to the power supply terminal VDD, and the control terminal of the first transistor PM3 is connected to the second terminal of the first transistor PM3 and the first node VBP. The voltage regulation unit 12 includes a second transistor NM5 and a first resistor R1. The first terminal of the second transistor NM5 is connected to the control terminal of the first transistor PM3 and the second terminal of the first transistor PM3. The control terminal of the second transistor NM5 is connected to the second node VB. The first terminal of the first resistor R1 is connected to the second terminal of the second transistor NM5, and the second terminal of the first resistor R1 is connected to the ground terminal GND.

[0043] It should be noted that during startup, the voltage amplitude of the second node VB may overshoot, causing the current overshoot generated by the second transistor NM5. The first resistor R1 can limit the current overshoot of the second transistor NM5, thereby pulling down the voltage of the drain and gate of the first transistor PM3 through the second transistor NM5 and the first resistor R1, that is, reducing the voltage amplitude of the first node VBP, and thus limiting the overshoot of the reference voltage VOUT.

[0044] In some of these embodiments, such as Figure 4 As shown, the mirror output module 20 includes a first mirror branch 21 and a second mirror branch 22. The first mirror branch 21 includes a second node VB and a third node VA. The first mirror branch 21 is connected to the first node VBP and is used to reverse adjust the voltage of the second node VB according to the voltage of the third node VA. The second mirror branch 22 is connected to the first node VBP and the third node VA. The second mirror branch 22 is used to reverse adjust the voltage of the third node VA according to the voltage of the first node VBP and generate a reference voltage VOUT based on the voltage of the first node VBP.

[0045] It should be noted that in this embodiment, the voltage of the second node VB and the voltage of the first node VBP are adjusted by the voltage of the third node VA. After the feedback loop, the voltages of the second node VB and the first node VBP can be stabilized, thereby improving the stability of the operation.

[0046] In some of these embodiments, such as Figure 5As shown, the first mirror branch 21 includes a third transistor PM4 and a first transistor Q1. The first terminal of the third transistor PM4 is connected to the voltage regulation module 10 and the power supply terminal VDD, and the control terminal of the third transistor PM4 is connected to the voltage regulation module 10 and the first node VBP. The first terminal of the first transistor Q1 is connected to the second terminal of the third transistor PM4, the control terminal of the first transistor Q1 is connected to the third node VA, and the second terminal of the first transistor Q1 is connected to the ground terminal GND.

[0047] It should be noted that the third transistor PM4 and the first transistor PM3 form a mirror image structure, ensuring that the current flowing through the third transistor PM4 maintains a preset proportional relationship with the current flowing through the first transistor PM3. When the voltage amplitude of the third node VA increases, the first transistor Q1 turns on, thereby lowering the voltage amplitude of the second node VB.

[0048] In some of these embodiments, such as Figure 6 As shown, the second mirror branch 22 includes a second mirror unit 221 and a third mirror unit 222. The second mirror unit 221 is connected to the first node VBP and the third node VA. The second mirror unit 221 is used to reverse adjust the voltage of the third node VA according to the voltage of the first node VBP. The third mirror unit 222 is connected to the first node VBP. The third mirror unit 222 is used to generate a reference voltage VOUT based on the voltage of the first node VBP.

[0049] It should be noted that the second mirror unit 221 can also generate a second current based on the voltage of the first node VBP, and the third mirror unit 222 is also used to generate a reference voltage VOUT based on the voltage of the first node VBP and the second current.

[0050] In some of these embodiments, such as Figure 7 As shown, the second mirror unit 221 includes a fourth transistor PM5, a second transistor Q2, and a second resistor R2. The first terminal of the fourth transistor PM5 is connected to the power supply terminal VDD and the first terminal of the third transistor PM4. The control terminal of the fourth transistor PM5 is connected to the first node VBP and the control terminal of the third transistor PM4. The second terminal of the fourth transistor PM5 is connected to the third node VA. The first terminal of the second transistor Q2 is connected to the control terminal of the second transistor Q2, the second terminal of the fourth transistor PM5, and the third node VA. The first terminal of the second resistor R2 is connected to the second terminal of the second transistor Q2, and the second terminal of the second resistor R2 is connected to the ground terminal GND.

[0051] It should be noted that the fourth transistor PM5 and the first transistor PM3 form a mirror image structure, ensuring that the current flowing through the fourth transistor PM5 maintains a preset proportional relationship with the current flowing through the first transistor PM3. When the voltage amplitude of the first node VBP increases, the first node VBP pulls up the voltage of the third node VA through the fourth transistor PM5.

[0052] In some of these embodiments, such as Figure 8 As shown, the third mirror unit 222 includes a fifth transistor PM6, a third resistor R3, and a third transistor Q3. The first terminal of the fifth transistor PM6 is connected to the power supply terminal VDD, and the control terminal of the fifth transistor PM6 is connected to the first node VBP and the control terminal of the fourth transistor PM5. The first terminal of the third resistor R3 is connected to the second terminal of the fifth transistor PM6 and outputs a reference voltage VOUT. The first terminal of the third transistor Q3 is connected to the control terminal of the third transistor Q3 and the second terminal of the third resistor R3, and the second terminal of the third transistor Q3 is connected to the ground terminal GND.

[0053] It should be noted that the fifth transistor PM6 and the first transistor PM3 form a mirror image structure, ensuring that the current flowing through the fifth transistor PM6 maintains a preset ratio with the current flowing through the first transistor PM3. This, in turn, ensures that the current flowing through the second resistor R2 maintains a preset ratio with the current flowing through the third resistor R3. Therefore, when the voltage amplitude at the first node VBP is stable, the current flowing through the third resistor R3 is also stable, thus stabilizing the reference voltage VOUT.

[0054] In some of these embodiments, such as Figure 9 As shown, the second mirror branch 22 includes a fourth transistor PM5, a second transistor Q2, a second resistor R2, and a third resistor R3. The first terminal of the fourth transistor PM5 is connected to the power supply terminal VDD, and the control terminal of the fourth transistor PM5 is connected to the first node VBP. The first terminal of the second transistor Q2 is connected to the control terminal of the second transistor Q2, the control terminal of the first transistor Q1, and the third node VA. The first terminal of the second resistor R2 is connected to the second terminal of the second transistor Q2, and the second terminal of the second resistor R2 is connected to the ground terminal GND. The first terminal of the third resistor R3 is connected to the second terminal of the fourth transistor PM5 and outputs a reference voltage VOUT. The second terminal of the third resistor R3 is connected to the first terminal of the second transistor Q2, the control terminal of the second transistor Q2, the control terminal of the first transistor Q1, and the third node VA.

[0055] It should be noted that in this embodiment, the third resistor R3 in the above embodiment is moved to the second mirror unit 221, thus saving the third mirror unit 222. This not only reduces the number of mirror branches, but also reduces the number of components and power consumption while achieving the same working principle.

[0056] In some of these embodiments, such as Figure 10 As shown, the bandgap reference circuit 100 also includes a startup module 30 and a clamping module 40. The startup module 30 is connected to the first node VBP and the second node VB. The startup module 30 is used to generate a clamping control signal and the voltage of the second node VB during startup, so as to control the voltage regulation module 10 and the mirror output module 20 to enter the working state through the voltage of the second node VB. The clamping module 40 is connected to the startup module 30 and the second node VB. The clamping module 40 is used to clamp the potential of the second node VB during startup according to the clamping control signal.

[0057] It should be noted that during startup, the startup module 30 provides a high-level voltage to the second node VB, which controls the voltage regulation module 10 and the mirror output module 20 to enter the working state, thus triggering the establishment of the reference voltage VOUT. During startup, the potential of the second node VB is clamped, preventing voltage overshoot of the second node VB, and consequently preventing overshoot of the reference voltage VOUT. Here, VSEP is the clamping control signal.

[0058] In some of these embodiments, such as Figure 11 As shown, the clamping module 40 includes a clamping unit 41 and a gating unit 42. The clamping unit 41 is used to generate a clamping voltage. The gating unit 42 is connected to the clamping unit 41 and the second node VB. The gating unit 42 is used to clamp the voltage of the second node VB as the clamping voltage during the startup process according to the clamping control signal.

[0059] It should be noted that the clamping voltage is the voltage difference across the clamping unit 41, which can be preset to a value to control the voltage of the second node VB within the required range. The gating unit 42 can be turned on during startup and turned off after startup, thus reducing the power consumption of the gating unit 42 and the clamping unit 41.

[0060] In some of these embodiments, such as Figure 12 As shown, the gating unit 42 includes a sixth transistor NM3. The first terminal of the sixth transistor NM3 is connected to the startup module 30 and the second node VB. The control terminal of the sixth transistor NM3 is connected to the clamping control signal. The second terminal of the sixth transistor NM3 is connected to the clamping unit 41.

[0061] It should be noted that during startup, the clamp control signal is at a high level, the sixth transistor NM3 is turned on, and the voltage of the second node VB is maintained at the clamp voltage; after startup, the clamp control signal switches to a low level, the sixth transistor NM3 is turned off, and the voltage of the second node VB also switches to a low level.

[0062] In some of these embodiments, such as Figure 13 As shown, the clamping unit 41 includes at least one seventh transistor NM4. At least one seventh transistor NM4 is connected between the second terminal of the sixth transistor NM3 and the ground terminal GND. The first terminal of each seventh transistor NM4 is connected to the control terminal of the seventh transistor NM4. The first terminal of one seventh transistor NM4 is connected to the second terminal of the sixth transistor NM3 or the second terminal of another seventh transistor NM4. The second terminal of one seventh transistor NM4 is connected to the ground terminal GND or the first terminal of another seventh transistor NM4.

[0063] It should be noted that the clamping unit 41 can also be a diode in other embodiments. Compared with a resistor, this embodiment reduces the area of ​​the clamping unit 41.

[0064] In some of these embodiments, such as Figure 14 As shown, the startup module 30 includes an eighth transistor PM1, at least one ninth transistor, a Schmitt trigger ST, an inverter INV, and a tenth transistor PM2. The first terminal of the eighth transistor PM1 is connected to the power supply terminal VDD, and the control terminal of the eighth transistor PM1 is connected to the voltage regulation module 10. At least one ninth transistor is connected between the second terminal of the eighth transistor PM1 and the ground terminal GND, and the first terminal of each ninth transistor is connected to the control terminal of the ninth transistor. The input terminal of the Schmitt trigger ST is connected to the second terminal of the eighth transistor PM1, and the output terminal of the Schmitt trigger ST is used to output a clamping control signal. The input terminal of the inverter INV is connected to the output terminal of the Schmitt trigger ST. The first terminal of the tenth transistor PM2 is connected to the first terminal of the eighth transistor PM1, the control terminal of the tenth transistor PM2 is connected to the output terminal of the inverter INV, the second terminal of the tenth transistor PM2 is connected to the clamping unit 41, the voltage regulation module 10, and the mirror output module 20, and the second terminal of the tenth transistor PM2 is connected to the second node VB.

[0065] It should be noted that the input voltage VC of the Schmitt trigger ST can be configured as needed. When VC needs to be set to one Vgs, a ninth transistor, such as transistor NM1, can be used. The first terminal of transistor NM1 is connected to its control terminal and the input of the Schmitt trigger ST, and the second terminal of transistor NM1 is connected to ground GND. When VC needs to be set to multiple Vgs, such as two Vgs, two ninth transistors, such as transistors NM1 and NM2, can be used. The first terminal of transistor NM1 is connected to its control terminal and the input of the Schmitt trigger ST, and the second terminal of transistor NM1 is connected to the first terminal and the control terminal of transistor NM2. The second terminal of transistor NM2 is connected to ground GND. Other cases can be deduced similarly.

[0066] When the power supply voltage VDD starts from 0V, the initial current of the eighth transistor PM1 is 0A. Transistors NM1 and NM2 pull VC low, the clamping control signal VSEP output by the Schmitt trigger ST is high, and the output signal VSEN of the inverter INV is low. During startup, the tenth transistor PM2 pulls the voltage of the second node VB high. This high voltage of the second node VB, through the second transistor NM5, pulls the voltage of the first node VBP low. After the voltage of the first node VBP is pulled low, the reference voltage VOUT begins to build up.

[0067] When the voltage at the second node VB is too high, the current flowing through the first transistor PM3 and the fifth transistor PM6 is large, resulting in a high overshoot of the reference voltage VOUT. Therefore, the seventh transistor NM4 in the clamping unit 41 is connected in a MOS diode configuration, which clamps the voltage at the second node VB during startup to prevent it from becoming too high.

[0068] After the voltage regulation module 10 and the mirror output module 20 are started, the current of the eighth transistor PM1 mirroring the first transistor PM3 will pull VC high, VSEP will be low, and VSEN will be high. That is, after the start-up is completed, the sixth transistor NM3 and the tenth transistor PM2 are both disconnected, and the start-up module 30 and the clamping module 40 will no longer affect the normal operation of the voltage regulation module 10 and the mirror output module 20.

[0069] For the voltage regulation module 10 and the mirror output module 20, the loop is first stabilized through negative feedback. Then, a positive temperature coefficient current is generated through a transistor. Finally, the positive temperature coefficient current is mirrored onto a resistor and superimposed on another transistor to generate a zero temperature coefficient reference voltage VOUT. The negative feedback loop is as follows: if the voltage of the second node VB increases, the second transistor NM5 pulls down the voltage of the first node VBP. The voltage of the second node VB then pulls up VA through the fourth transistor PM5. VA then pulls down the voltage of the second node VB through the first transistor Q1. This cyclical negative feedback loop stabilizes the voltage regulation module 10 and the mirror output module 20 at a single operating point, thereby outputting a stable reference voltage VOUT.

[0070] Let IPM3 = A × IPM4 = B × IPM5 = C × IPM6, and let M be the ratio of the number of unit transistors in the second transistor Q2 to the number of unit transistors in the first transistor Q1. Then, the formula 1-1 for calculating the current IR2 flowing through the second resistor R2 is as follows:

[0071]

[0072] Where IPM3 represents the current flowing through the first transistor PM3. IPM4 represents the current flowing through the third transistor PM4. IPM5 represents the current flowing through the fourth transistor PM5. IPM6 represents the current flowing through the fifth transistor PM6. VT represents the thermal voltage, and IS represents the saturation current of the transistor. IC1 represents the collector current of the first transistor Q1, and IC2 represents the collector current of the second transistor Q2. VBE1 represents the voltage difference between the base and emitter of the first transistor Q1. VBE2 represents the voltage difference between the base of the second transistor Q2 and the emitter of the first transistor Q1.

[0073] If we ignore the base current (IB) of the transistor, we can simplify calculation 1-1 into calculation 1-2, as shown below:

[0074]

[0075] The voltage drop across the third resistor R3, i.e., VR3, is calculated using formula 1-3, as shown below:

[0076]

[0077] Where R3 represents the resistance value of the third resistor R3.

[0078] but Figure 7 The calculation formula for the reference voltage VOUT is shown in equation 1-4 below:

[0079]

[0080] Where VBE3 represents the voltage difference between the base of the third transistor Q3 and the emitter of the first transistor Q1. VBE3 is a negative temperature coefficient voltage, and VR3 is a positive temperature coefficient voltage. By setting appropriate values ​​for A, B, C, M, and the ratio of the third resistor R3 to the second resistor R2, a reference voltage VOUT with approximately zero temperature coefficient can be obtained.

[0081] This embodiment does not use a current mirror for clamping; the minimum required operating power supply voltage for the negative feedback loop is approximately VDD. MIN1 =VBE1+VSD PM5 The minimum operating power supply voltage required for the third mirror unit 222 is approximately VDD. MIN2 =VOUT+VSD PM6 Compared to the minimum operating power supply voltage required by traditional technologies, VDD MIN1 VDD MIN2 All are lower, indicating that the embodiments of this application can reduce the minimum operating power supply voltage of the power supply terminal VDD. VSD PM5 This represents the voltage difference between the source and drain of the fourth transistor PM5. (VSD)PM6 This represents the voltage difference between the source and drain of the fifth transistor PM6.

[0082] Figure 9 and Figure 8 The working principle is the same. The current flowing through the second resistor R2 is IR2 = (VBE1 - VBE2) / R2, where IR2 is the positive temperature coefficient current. The second resistor R2 and the third resistor R3 are connected in series in the same branch. The positive temperature coefficient current flows directly through the third resistor R3 without being reflected by the current mirror. The voltage drop across the third resistor R3 is VR3 = (VBE1 - VBE2) / R2 × ​​R3, where VR3 is the positive temperature coefficient voltage.

[0083] VOUT = VBE1 + (VBE1 - VBE2) / R2 × R3. By setting appropriate values ​​for A, B, C, M, and the ratio of the third resistor R3 to the second resistor R2, a reference voltage VOUT with an approximate zero temperature coefficient can be obtained.

[0084] exist Figure 9 In the diagram, the minimum operating voltage of the power supply terminal VDD is VDD. MIN =VOUT+VSD PM5 , with VDD MIN1 same.

[0085] This application embodiment also provides a chip 200, such as Figure 15 As shown, the chip 200 includes the bandgap reference circuit 100 described above. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0086] It is understood that since the chip 200 provided in this application embodiment includes the above-mentioned bandgap reference circuit 100, it can also reduce the voltage of the first node VBP when the voltage of the second node VB increases through the voltage adjustment module 10, and reduce the voltage of the second node VB when the voltage of the first node VBP decreases through the mirror output module 20. Through such cyclic feedback, the voltage of the second node VB can be stabilized, thereby stabilizing the voltage of the first node VBP, and further stabilizing the reference voltage VOUT generated based on the voltage of the first node VBP, avoiding the phenomenon of excessively high reference voltage VOUT and improving stability.

[0087] This application also provides an electronic device 300, such as... Figure 16As shown, the electronic device 300 includes a device body and the aforementioned bandgap reference circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0088] It is understood that since the electronic device 300 provided in this application embodiment includes the above-mentioned bandgap reference circuit 100 or chip 200, it can also reduce the voltage of the first node VBP when the voltage of the second node VB increases through the voltage adjustment module 10, and reduce the voltage of the second node VB when the voltage of the first node VBP decreases through the mirror output module 20. Through such cyclic feedback, the voltage of the second node VB can be stabilized, thereby stabilizing the voltage of the first node VBP, and further stabilizing the reference voltage VOUT generated based on the voltage of the first node VBP, avoiding the phenomenon of excessively high reference voltage VOUT and improving stability.

[0089] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes: A voltage regulation module, comprising a first node, wherein the voltage regulation module is used to reversely regulate the voltage of the first node according to the voltage of the second node; A mirror output module, comprising a second node, is connected to the first node. The mirror output module is used to adjust the voltage of the second node in the same direction as the voltage of the first node, and to generate a reference voltage based on the voltage of the first node.

2. The bandgap reference circuit as described in claim 1, characterized in that, The voltage regulation module includes: The first mirror unit is connected to the power supply and the first node; A voltage regulation unit is connected to the second node and the first mirror unit. The voltage regulation unit is used to adjust the voltage of the first node in reverse according to the voltage of the second node.

3. The bandgap reference circuit as described in claim 2, characterized in that, The first mirror unit includes a first transistor, the first terminal of the first transistor is connected to the power supply terminal, and the control terminal of the first transistor is connected to the second terminal of the first transistor and the first node; The voltage regulation unit includes: The second transistor has its first terminal connected to the control terminal of the first transistor and the second terminal of the first transistor, and its control terminal connected to the second node. A first resistor, the first end of which is connected to the second terminal of the second transistor, and the second end of which is connected to the ground terminal.

4. The bandgap reference circuit as described in claim 1, characterized in that, The mirror output module includes: The first mirror branch includes a second node and a third node. The first mirror branch is connected to the first node and is used to reverse adjust the voltage of the second node according to the voltage of the third node. The second mirror branch is connected to the first node and the third node. The second mirror branch is used to reverse the voltage of the third node according to the voltage of the first node, and to generate the reference voltage based on the voltage of the first node.

5. The bandgap reference circuit as described in claim 4, characterized in that, The first mirror branch includes: The third transistor has its first terminal connected to the power supply terminal and its control terminal connected to the first node. The first transistor has its first terminal connected to the second terminal of the third transistor and the second node, its control terminal connected to the third node, and its second terminal connected to the ground terminal.

6. The bandgap reference circuit as described in claim 4, characterized in that, The second mirror branch includes: The second mirror unit is connected to the first node and the third node, and the second mirror unit is used to reverse the voltage of the third node according to the voltage of the first node; A third mirror unit is connected to the first node and is used to generate the reference voltage based on the voltage of the first node.

7. The bandgap reference circuit as described in claim 6, characterized in that, The second mirror unit includes: The fourth transistor has its first terminal connected to the power supply terminal, its control terminal connected to the first node, and its second terminal connected to the third node. The second transistor, the first terminal of the second transistor is connected to the control terminal of the second transistor, the second terminal of the fourth transistor and the third node; The second resistor has its first end connected to the second terminal of the second transistor, and its second end connected to the ground terminal.

8. The bandgap reference circuit as described in claim 6, characterized in that, The third mirror unit includes: The fifth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the first node. The third resistor has its first terminal connected to the second terminal of the fifth transistor and outputs the reference voltage. The third transistor has its first terminal connected to its control terminal and the second terminal of the third resistor, and its second terminal connected to the ground terminal.

9. The bandgap reference circuit as described in claim 5, characterized in that, The second mirror branch includes: The fourth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the first node. The second transistor has its first terminal connected to the control terminal of the second transistor, the control terminal of the first transistor, and the third node. The second resistor has its first end connected to the second terminal of the second transistor and its second end connected to the ground terminal. The third resistor has its first end connected to the second terminal of the fourth transistor and outputs the reference voltage. The second end of the third resistor is connected to the first terminal of the second transistor, the control terminal of the second transistor, the control terminal of the first transistor, and the third node.

10. The bandgap reference circuit according to any one of claims 1 to 9, characterized in that, The bandgap reference circuit further includes: A startup module is connected to the first node and the second node. The startup module is used to generate a clamping control signal and the voltage of the second node based on the voltage of the first node during the startup process, so as to control the voltage regulation module and the mirror output module to enter the working state through the voltage of the second node. A clamping module is connected to the startup module and the second node. The clamping module is used to clamp the voltage of the second node during the startup process according to the clamping control signal.

11. The bandgap reference circuit as described in claim 10, characterized in that, The clamping module includes: A clamping unit, the clamping unit being used to generate a clamping voltage; A gating unit is connected to the clamping unit and the second node. The gating unit is used to clamp the voltage of the second node as the clamping voltage during the startup process according to the clamping control signal.

12. The bandgap reference circuit as described in claim 11, characterized in that, The gating unit includes a sixth transistor. The first terminal of the sixth transistor is connected to the startup module and the second node. The control terminal of the sixth transistor is connected to the clamping control signal. The second terminal of the sixth transistor is connected to the clamping unit.

13. The bandgap reference circuit as described in claim 12, characterized in that, The clamping unit includes at least one seventh transistor, which is connected between the second terminal of the sixth transistor and the ground terminal. The first terminal of each seventh transistor is connected to the control terminal of the seventh transistor. The first terminal of one seventh transistor is connected to the second terminal of the sixth transistor or the second terminal of another seventh transistor. The second terminal of one seventh transistor is connected to the ground terminal or the first terminal of another seventh transistor.

14. The bandgap reference circuit as described in claim 11, characterized in that, The startup module includes: The eighth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the voltage regulation module. At least one ninth transistor, wherein the at least one ninth transistor is connected between the second terminal of the eighth transistor and the ground terminal, and the first terminal of each ninth transistor is connected to the control terminal of the ninth transistor; A Schmitt trigger, wherein the input terminal of the Schmitt trigger is connected to the second terminal of the eighth transistor, and the output terminal of the Schmitt trigger is used to output the clamping control signal; An inverter, the input of which is connected to the output of the Schmitt trigger; The tenth transistor has its first terminal connected to the first terminal of the eighth transistor, its control terminal connected to the output terminal of the inverter, its second terminal connected to the clamping unit, the voltage regulation module, and the mirror output module, and its second terminal connected to the second node.

15. A chip, characterized in that, The chip includes a bandgap reference circuit as described in any one of claims 1 to 14.

16. An electronic device, characterized in that, The electronic device includes a device body and a chip as described in claim 15 disposed on the device body.

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