A current limiting circuit and an integrated circuit chip

Abstract

The application provides a current limiting circuit and an integrated circuit chip, the circuit comprising an operational amplifier, a power transistor, a current limiting protection module, a bias voltage module and a shunt module, the output end of the operational amplifier being connected with the power transistor, the power transistor being connected with the positive input end of the operational amplifier through a feedback resistor, the input end of the current limiting protection module being connected with the source electrode of the power transistor, the output end of the current limiting protection module being connected with the input end of the bias voltage module and the output end of the shunt module, and the input end of the shunt module being connected with a power supply, without proportionally sampling the power transistor, directly using the current of the power transistor, avoiding the precision error caused by sampling, meanwhile, using M11 and M12 for shunting, ensuring that I3=0 when the current limiting is started, the voltage at point N is high enough, the starting and turning off of M10 can be accurately controlled, and thus the current limiting range can be accurately controlled.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically to an LDO current limiting circuit. Background Technology

[0002] Linear regulators play a crucial role in voltage regulation in electronic devices. However, when operating in high-temperature environments, the current-limiting protection value of traditional linear regulators increases with temperature, which may reduce the overcurrent capacity of metal traces and ultimately damage the circuit. Traditional LDO current-limiting circuits, such as... Figure 1 As shown, using the input reference voltage VREF as a reference, the circuit compares the input voltage with the output voltage feedback signal through an error amplifier. Based on the error signal, the conduction level of the power transistor MP is adjusted, and transistor M2 samples the current of transistor MP. The currents of current mirrors M3 and M7 are compared to determine the potential at point P, controlling the on / off state of transistor M1. This creates a new loop M2-M3-M4-M1 that clamps the gate voltage of the transistor, achieving current limiting. However, the current comparison accuracy of M4 and M5 in this current-limiting circuit is too low, failing to precisely control the turn-off of M1. Furthermore, the circuit is significantly affected by the PVT, resulting in a large variation in the current-limiting range. Therefore, designing a high-precision circuit with a current-limiting range that does not change with temperature is crucial for improving the stability and reliability of linear regulators.

[0003] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be regarded as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, this application provides a current limiting circuit to solve the problem that the current limiting circuit in the prior art is greatly affected by PVT and the current limiting range varies greatly.

[0005] In a first aspect, embodiments of this application provide a current limiting circuit, characterized in that the circuit includes an operational amplifier, a power transistor, a current limiting protection module, a bias module, and a shunt module. The output terminal of the operational amplifier is connected to the power transistor, the power transistor is connected to the positive input terminal of the operational amplifier through a feedback resistor, the input terminal of the current limiting protection module is connected to the source of the power transistor, the output terminal of the current limiting protection module is connected to the input terminal of the bias module and the output terminal of the shunt module, and the input terminal of the shunt module is connected to a power supply.

[0006] In one possible implementation, the operational amplifier AMP has its negative input terminal connected to a reference voltage VREF, its output terminal connected to the gate terminal of a power transistor MP, the drain terminal of the power transistor MP connected to the first terminal of a feedback resistor RF1, the second terminal of the feedback resistor RF1 connected to the first terminal of a feedback resistor RF2 and the positive input terminal of the operational amplifier AMP, and the second terminal of the feedback resistor RF2 grounded.

[0007] In one possible implementation, the shunt module includes transistor M11 and transistor M12, the gate of transistor M12 is connected to the drain and to node N, the source of transistor M12 is connected to the gate and drain of transistor M11, and the source of transistor M11 is connected to a power supply.

[0008] In one possible implementation, the current limiting protection module includes transistors Q1 and Q2. The base and collector of transistor Q1 are shorted together, and the emitter of transistor Q1 is connected to the source of power transistor MP and the first terminal of current limiting resistor R1. The second terminal of current limiting resistor R1 is connected to the power supply. The base of transistor Q2 is connected to the base of transistor Q1, the collector is connected to node N, and the emitter of transistor Q2 is connected to the second terminal of current limiting resistor R1.

[0009] In one possible implementation, the bias module includes transistor M8 and transistor M9, the gate of transistor M8 is connected to the gate of transistor M9 and the reference voltage Vbias, the drain of transistor M8 is connected to the collector of transistor Q1, and the source of transistor M8 is grounded; the drain of transistor M9 is connected to node N, and the source of transistor M9 is grounded.

[0010] In one possible implementation, transistor M10 is also included, with its gate connected to node N, its drain connected to a power supply, and its source connected to power transistor MP.

[0011] In one possible implementation, the width-to-length ratio of transistor M8 and transistor M9 is 1:2.

[0012] In one possible implementation, the ratio of the turn-on threshold voltages of transistor Q1 and transistor Q2 is 4:1.

[0013] In one possible implementation, the current-limiting resistor R1 is a resistor with a positive temperature coefficient.

[0014] Secondly, this application provides an integrated circuit chip that includes any of the possible current-limiting circuits described in the first aspect.

[0015] In this embodiment, the power transistor is not sampled proportionally; instead, its current is used directly, avoiding accuracy errors caused by sampling. Furthermore, a BJT is used as the clamping loop in the current-limiting circuit, reducing mismatch compared to a MOSFET. The selection of the current-limiting value is actually related to V. BE The ratio is related and less affected by PVT, so the actual current limiting value is relatively accurate. At the same time, using M11 / M12 to split the current ensures that I3=0 when the current limiting is enabled, and the N point is high enough to accurately control the opening and closing of M10, thereby precisely controlling the current limiting range. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a traditional LDO current limiting circuit.

[0018] Figure 2 This application provides a current limiting circuit for its embodiments. Detailed Implementation

[0019] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0020] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0021] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] Example: An LDO current limiting circuit mainly includes a reference voltage input terminal VREF, an error amplifier, a power transistor MP, feedback resistors RF1 and RF2, composite transistors Q1 and Q2, a current mirror circuit, and a bias circuit.

[0024] like Figure 1 As shown, the current limiting circuit in the prior art includes: an input reference voltage, an error amplifier, a feedback resistor, a power transistor, and a current limiting and biasing circuit. The reference voltage VREF serves as the positive input terminal of the error amplifier. Power transistors MP and M1 work together to regulate the output current, ensuring the output voltage remains at the set value. Transistors M2 and M3 form a biasing circuit, providing a stable bias current for the error amplifier and the power transistors. A voltage divider network composed of feedback resistors RF1 and RF2 samples the feedback voltage from the output terminal Vbias and inputs it to the negative input terminal of the error amplifier. The error amplifier compares the difference between the reference voltage VREF and the feedback voltage, outputting an error signal to control the conduction of power transistor MP, thereby adjusting the output voltage.

[0025] like Figure 2 As shown, the current limiting circuit of this application includes an operational amplifier, a power transistor, a current limiting protection module, a bias module, and a shunt module. The output terminal of the operational amplifier is connected to the power transistor, and the power transistor is connected to the positive input terminal of the operational amplifier through a feedback resistor. The input terminal of the current limiting protection module is connected to the source of the power transistor, and the output terminal of the current limiting protection module is connected to the input terminal of the bias module and the output terminal of the shunt module. This allows the shunt module to better determine the potential of node N, thereby accurately controlling the operating timing of the current limiting circuit. The input terminal of the shunt module is connected to the power supply VDD, and the output terminal of the bias module is grounded. This application does not perform proportional sampling of the power transistor, but directly uses the current of the power transistor, avoiding the accuracy error caused by sampling.

[0026] Specifically, the operational amplifier AMP has its negative input terminal connected to the reference voltage VREF and its output terminal connected to the gate terminal of the power transistor MP to control the conduction state of the power transistor. The drain terminal of the power transistor MP is connected to the first terminal of the feedback resistor RF1. The second terminal of the feedback resistor RF1 is connected to the first terminal of the feedback resistor RF2 and the positive input terminal of the operational amplifier to provide a feedback signal to the operational amplifier. The second terminal of the feedback resistor RF2 is grounded. The current limiting protection module includes transistors Q1 and Q2. The base and collector of transistor Q1 are shorted to form a diode structure. The emitter of transistor Q1 is connected to the source of power transistor MP and the first terminal of current limiting resistor R1, and the second terminal of current limiting resistor R1 is connected to the power supply. The base of transistor Q2 is connected to the base of transistor Q1, and the collector is connected to node N. The emitter of transistor Q2 is connected to the second terminal of current limiting resistor R1. The gate of transistor M10 is connected to node N, the drain of transistor M10 is connected to the power supply, and the source of transistor M10 is connected to power transistor MP. When the output current is too large, transistor Q2 turns on, reducing the potential of node N, thereby reducing the drive current of the transistor and realizing current limiting protection. The bias module includes transistors M8 and M9. The gate of transistor M8 is connected to the gate of transistor M9 and the reference voltage Vbias. The drain of transistor M8 is connected to the collector of transistor Q1, and its source is grounded. The drain of transistor M9 is connected to node N, and its source is grounded. The bias module provides the necessary voltage bias for subsequent circuits. The shunt module includes two transistors M11 and M12 connected in series as diodes. The gate of transistor M12 is connected to its drain and to node N. The source of transistor M12 is connected to the gate and drain of transistor M11. The source of transistor M11 is connected to the power supply.

[0027] Under low load conditions, the linear regulator loop consists of operational amplifier AMP, power transistor MP, and feedback resistors RF1 and RF2. The current across current-limiting resistor R1 is small, resulting in a small voltage drop. Therefore, the turn-on threshold voltages of transistors Q1 and Q2 are almost equal. Simultaneously, the width-to-length ratio of transistors M8 and M9 is set to 1:2, the current I2 = 2 * I1, and the turn-on threshold voltage ratio of transistors Q1 and Q2 is 4:1. Therefore, under low load conditions, I2 = 2 * I1 = I3 + I4, where I4 ≈ I1 ≈ I3. At this time, the voltage at node N is low, so the gate voltage of transistor M10 is below its threshold voltage and it turns off, and the current-limiting circuit does not operate.

[0028] As the load current increases, the current flowing through the current-limiting resistor R1 also increases, and the resulting voltage drop becomes significant. According to the relationship...

[0029] V BE2 =V BE1 +I R1 ×R1

[0030] This causes the base-emitter voltage VBE2 of transistor Q2 to increase, I4 to rise, I3 to decrease, and the potential at node N to rise. When the current is high enough, it will raise the voltage at point N, causing transistors M11 and M12 to turn off, thus making I3 = 0. When the potential at node N is high enough, transistor M10 will turn on, the current-limiting loop will open, I4 = I2 = 2 * I1, and the gate of power transistor MP will be embedded at a fixed potential, resulting in a constant output current. Ignoring the base current, when the current-limiting circuit is on, the collector currents of Q1 and Q2 are equal, allowing the calculation of the current-limiting value.

[0031]

[0032] In the above formula, The current limiting value is positively correlated with temperature. When the temperature coefficient of the current-limiting resistor R1 is ignored, the current limiting value of the circuit will increase with increasing temperature. However, this is not good for the circuit because the current-carrying capacity of the metal traces decreases with increasing temperature. If a resistor with a positive temperature coefficient is chosen for the current-limiting resistor R1, the numerator V can be effectively offset. T Because of its positive temperature coefficient, by selecting an appropriate resistor, the current limiting value of the circuit can actually decrease as the temperature increases.

[0033] In this embodiment, a BJT is selected as the clamping loop of the current limiting circuit, which reduces mismatch compared to a MOSFET; the selection of the current limiting value is actually related to V. BE The ratio is related and less affected by PVT, so the actual current limiting value is relatively accurate. At the same time, M11 and M12 are used for current shunting to ensure that I3 = 0 when the current limiting is turned on, and the voltage at point N is high enough to accurately control the turning on and off of M10, thereby precisely controlling the current limiting range.

[0034] This application also provides a schematic diagram of an integrated circuit chip, which includes a current limiting circuit. A detailed description of the current limiting circuit can be found above. Figure 2 The description of the current limiting circuit in the illustrated embodiment will not be repeated here.

[0035] In this application embodiment, the integrated circuit chip includes, but is not limited to, microcontroller units (MCUs), DSPs, microprocessors (MPUs), central processing units (CPUs), and other micro central control chips and system-on-a-chip chips that can process digital signals, analog signals, or perform signal control, instruction processing, and arithmetic functions.

[0036] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0037] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A current limiting circuit, characterized in that, The circuit includes an operational amplifier, a power transistor, a current limiting protection module, a bias module, and a shunt module. The output of the operational amplifier is connected to the power transistor, which is connected to the positive input of the operational amplifier through a feedback resistor. The input of the current limiting protection module is connected to the source of the power transistor. The output of the current limiting protection module is connected to the input of the bias module and the output of the shunt module. The input of the shunt module is connected to the power supply.

2. The current limiting circuit according to claim 1, characterized in that, The operational amplifier AMP has its negative input terminal connected to the reference voltage VREF, its output terminal connected to the gate terminal of the power transistor MP, the drain terminal of the power transistor MP connected to the first terminal of the feedback resistor RF1, the second terminal of the feedback resistor RF1 connected to the first terminal of the feedback resistor RF2 and the positive input terminal of the operational amplifier AMP, and the second terminal of the feedback resistor RF2 grounded.

3. The current limiting circuit according to claim 2, characterized in that, The current shunt module includes transistor M11 and transistor M12. The gate of transistor M12 is connected to the drain and to node N. The source of transistor M12 is connected to the gate and drain of transistor M11. The source of transistor M11 is connected to the power supply.

4. The current limiting circuit according to claim 3, characterized in that, The current limiting protection module includes transistors Q1 and Q2. The base and collector of transistor Q1 are shorted together. The emitter of transistor Q1 is connected to the source of power transistor MP and the first terminal of current limiting resistor R1. The second terminal of current limiting resistor R1 is connected to the power supply. The base of transistor Q2 is connected to the base of transistor Q1. The collector of transistor Q2 is connected to node N. The emitter of transistor Q2 is connected to the second terminal of current limiting resistor R1.

5. The current limiting circuit according to claim 4, characterized in that, The bias module includes transistor M8 and transistor M9. The gate of transistor M8 is connected to the gate of transistor M9 and the reference voltage Vbias. The drain of transistor M8 is connected to the collector of transistor Q1, and the source of transistor M8 is grounded. The drain of transistor M9 is connected to node N, and the source of transistor M9 is grounded.

6. The current limiting circuit according to claim 5, characterized in that, It also includes a transistor M10, the gate of which is connected to node N, the drain of which is connected to a power supply, and the source of which is connected to the power transistor MP.

7. The current limiting circuit according to claim 5, characterized in that, The width-to-length ratio of transistor M8 and transistor M9 is 1:

2.

8. The current limiting circuit according to claim 4, characterized in that, The ratio of the turn-on threshold voltages of transistor Q1 and transistor Q2 is 4:

1.

9. The current limiting circuit according to claim 4, characterized in that, The current-limiting resistor R1 is a resistor with a positive temperature coefficient.

10. An integrated circuit chip, characterized in that, It includes the current limiting circuit as described in any one of claims 1-9.

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