Display panel and electronic device

Abstract

A display panel and an electronic device are provided. The display panel includes: a pixel; a signal line electrically connected to the pixel; and a signal pad connected to the signal line. The signal pad includes: a first conductive pattern connected to one side portion of the signal line; a second conductive pattern disposed on the first conductive pattern; and an insulating pattern including a first portion disposed on the first conductive pattern and a second portion disposed on the first portion, the first portion having a columnar shape, and the second portion having a dome shape.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0070986, filed on May 30, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display panel, an electronic device including the display panel, and a method of manufacturing the display panel, and for example, a display panel including pad areas, an electronic device including the display panel, and a method of manufacturing the display panel. Background Technology

[0004] The display device includes a display area that is activated in response to an electrical signal. Through this display area, the display device can sense external input (e.g., input applied from the outside) and simultaneously (e.g., synchronously) display one or more suitable images to provide information to the user.

[0005] The display device includes a display panel and a circuit board. The display panel can be connected to the motherboard via the circuit board. Additionally, a driver chip can be mounted on the display panel. Utility Model Content

[0006] One or more embodiments of this disclosure relate to a display panel with (e.g., having) enhanced (e.g., improved) bonding reliability and an electronic device including the display panel.

[0007] One or more embodiments of this disclosure relate to a method of manufacturing a display panel with improved processability. Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display panel includes: a pixel; a signal line electrically connected to the pixel; and a signal pad connected to the signal line, wherein the signal pad includes: a first conductive pattern connected to a side portion of the signal line; a second conductive pattern on the first conductive pattern; and an insulating pattern including a first portion on the first conductive pattern and a second portion on the first portion, the first portion having a cylindrical shape and the second portion having a dome shape.

[0009] In one or more embodiments, in a plan view, the insulating pattern may be arranged on the inside of each of the first conductive pattern and the second conductive pattern.

[0010] In one or more embodiments, the insulating pattern may be directly disposed on the first conductive pattern, and the second conductive pattern may cover the portion of the insulating pattern and the first conductive pattern on which the insulating pattern is not disposed (e.g., on the portion of the insulating pattern and the first conductive pattern on which the insulating pattern is not disposed).

[0011] In one or more embodiments, the first portion may include an upper surface that contacts the second portion, and the second portion may include a lower surface that contacts the first portion, and the upper surface of the first portion and the lower surface of the second portion may be identical surfaces that match each other. For example, the upper surface of the first portion may coincide with the lower surface of the second portion. For example, the first portion may have an upper surface that contacts the second portion, and the second portion may have a lower surface that contacts the first portion. These surfaces may be identical, meaning that the upper surface of the first portion coincides with the lower surface of the second portion. In one or more embodiments, the first portion may have a quadrilateral shape in a cross-sectional view, and the second portion may include an upper surface that contacts the second conductive pattern, and the upper surface of the second portion may have an upwardly convex shape.

[0012] In one or more embodiments, the elastic modulus of the first portion may be greater than that of the second portion.

[0013] In one or more embodiments, the first portion may be formed of a negative photoresist material, and the second portion may be formed of a positive photoresist material. For example, the first portion may include a structure formed of a negative photoresist material, and the second portion may include a structure formed of a positive photoresist material.

[0014] In one or more embodiments, the first part may have a multi-layered structure.

[0015] In one or more embodiments, both the first portion and the second portion may independently include a polymer.

[0016] In one or more embodiments of this disclosure, an electronic device includes: a display module; a window on the display module; and a receiving member that receives the display module, wherein the display module includes: a pixel; a signal line electrically connected to the pixel; and a signal pad connected to the signal line, wherein the signal pad includes: a first conductive pattern connected to a side portion of the signal line; a second conductive pattern on the first conductive pattern; and an insulating pattern including a first portion on the first conductive pattern and a second portion on the first portion, the first portion having a cylindrical shape and the second portion having a dome shape, and the elastic modulus of the first portion being greater than that of the second portion.

[0017] In one or more embodiments, in a plan view, the insulating pattern may be arranged on the inside of each of the first conductive pattern and the second conductive pattern.

[0018] In one or more embodiments, the insulating pattern may be directly disposed on the first conductive pattern, and the second conductive pattern may cover the portion of the insulating pattern and the first conductive pattern on which the insulating pattern is not disposed (e.g., on the portion of the insulating pattern and the first conductive pattern on which the insulating pattern is not disposed).

[0019] In one or more embodiments, the first portion may include an upper surface that contacts the second portion, the second portion may include a lower surface that contacts the first portion, and the upper surface of the first portion and the lower surface of the second portion may be substantially identical surfaces that match each other. For example, the upper surface of the first portion may coincide with the lower surface of the second portion.

[0020] In one or more embodiments, the first portion may have a cylindrical shape, and the second portion may have a dome shape.

[0021] In one or more embodiments, the first portion may have a quadrilateral shape in a cross-sectional view, the second portion may include an upper surface in contact with the second conductive pattern, and the upper surface of the second portion may have an upwardly convex shape.

[0022] In one or more embodiments, the first portion may be formed of a negative photoresist material, and the second portion may be formed of a positive photoresist material. For example, the first portion may include a structure formed of a negative photoresist material, and the second portion may include a structure formed of a positive photoresist material.

[0023] In one or more embodiments, the first part may have a multi-layered structure.

[0024] In one or more embodiments, both the first portion and the second portion may independently include a polymer.

[0025] In one or more embodiments of this disclosure, a method of manufacturing a display panel includes: providing a preliminary signal pad including a first conductive pattern connected to a side portion of a signal line; and forming an insulating pattern including a first portion and a second portion on the preliminary signal pad, wherein forming the insulating pattern includes: forming the first portion on the preliminary signal pad in a first region using a negative photoresist material; and forming the second portion on the first portion using a positive photoresist material.

[0026] In one or more embodiments, forming a first portion may include: applying a negative photoresist material to a preliminary signal pad; exposing the negative photoresist material in a first region; and forming the first portion in the first region by developing and curing the negative photoresist material. Forming a second portion may include: applying a positive photoresist material to the preliminary signal pad and the first portion; exposing a second region of the positive photoresist material in a plan view surrounding (e.g., around) the first region; and forming the second portion on the first portion by developing and curing the positive photoresist material.

[0027] In one or more embodiments, the first portion may be cylindrical in shape, and the second portion may be dome-shaped.

[0028] In one or more embodiments, the elastic modulus of the first portion may be configured to be greater than that of the second portion. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0030] Figure 1 This is an assembly perspective view of a display device according to one or more embodiments of the present disclosure;

[0031] Figure 2A and Figure 2B All are exploded perspective views of a display device according to one or more embodiments of the present disclosure;

[0032] Figure 3 This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0033] Figure 4 This is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 5 It is a cross-sectional view of a display panel of pixels according to one or more embodiments of the present disclosure;

[0035] Figure 6 This is an enlarged exploded perspective view of the pad area of ​​a display device according to one or more embodiments of the present disclosure;

[0036] Figure 7A This is a schematic plan view of a pad area according to one or more embodiments of this disclosure;

[0037] Figures 7B to 7DAll are cross-sectional views of the pad area according to one or more embodiments of this disclosure;

[0038] Figure 8 This is a cross-sectional view illustrating the joining structure of a display device according to one or more embodiments of the present disclosure; and

[0039] Figures 9A to 9H All are cross-sectional views illustrating the steps (e.g., actions or tasks) of a method for manufacturing a pad area according to one or more embodiments of the present disclosure. Detailed Implementation

[0040] In this specification, it will be understood that if an element (or area, layer, part, etc.) is referred to as being "on" another element, "connected" to another element, or "attached to" another element (for example, when an element (or area, layer, part, etc.) is referred to as being "on" another element, "connected" to another element, or "attached to" another element), then that element may be directly arranged on, directly connected to, or directly attached to the other element, or an intervening element may be arranged therebetween.

[0041] Similar reference numerals or symbols indicate similar elements. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of elements are exaggerated for the purpose of effective description of the technical content. The term "and / or" includes all of one or more combinations that can be defined by the relevant elements.

[0042] Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0043] Furthermore, terms such as “below,” “on the lower side,” “above,” and “on the upper side” may be used herein to describe the relationships between the elements illustrated in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0044] It will be understood that terms such as “comprising” or “having” are used herein (e.g., as used herein) intended to specify the presence of the stated features, integrals, steps, operations, elements, components and / or one or more (e.g., any suitable) combinations thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or one or more (e.g., any suitable) combinations thereof.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0046] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1 This is an assembly perspective view of a display device DD according to one or more embodiments of the present disclosure. Figure 2A and Figure 2B All are exploded perspective views of a display device DD according to one or more embodiments of this disclosure. As an example, Figure 2B The illustration shows that... Figure 2A The display device DD is shown in the diagram with the curved area BA in a curved state.

[0048] refer to Figure 1 As an example, the display device DD is illustrated as a mobile phone terminal. The display device DD according to this disclosure can be applied to small and / or medium-sized electronic devices such as tablet PCs, car navigation systems, game consoles, and / or smartwatches, as well as large electronic devices such as televisions and / or monitors.

[0049] In a plan view, the display device DD may have a rectangular shape with a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, this disclosure is not limited thereto, and the display device DD may have one or more suitable shapes in a plan view, such as a circular shape or a polygonal shape.

[0050] In the following text, the direction substantially orthogonal (e.g., perpendicularly intersecting) to the plane defined by the first direction DR1 and the second direction DR2 will be defined as the third direction DR3. As used herein, the phrase "in a plan view" may refer to the state observed in the third direction DR3.

[0051] A “sectional view” refers to a view taken by cutting through the display device DD along a plane orthogonal or perpendicular to the plane defined by the first direction DR1 and the second direction DR2. This means viewing the internal structure of the display device DD as if the display device had been cut along such a plane, thereby revealing the arrangement and relationship of the internal components in the third direction DR3.

[0052] The display device DD can be rigid or flexible. The term "flexible" can refer to a bendable property, and the display device DD can be any of the following: a fully foldable structure to a structure that is bendable to the nanometer level. For example, the display device DD can include any suitable structure from fully foldable to bendable at the nanometer level. Furthermore, for example, a flexible display device DD can include a bendable display device, a rollable display device, and a foldable display device.

[0053] The display device DD can display the image IM via the display surface DD-IS. An icon image is illustrated as an example of the image IM. The display surface DD-IS may be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0054] The display surface DD-IS may include a display area DD-DA in which an image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area in which the image IM is not displayed. However, this disclosure is not limited thereto, and the non-display area DD-NDA may be adjacent to any side of the display area DD-DA, or a non-display area DD-NDA may not be provided.

[0055] refer to Figure 2A and Figure 2B The display device DD may include a window WM, a display module DM, and a housing component BC.

[0056] A window (WM) can be disposed on a display module (DM) and transmits the image provided by the display module DM to the outside. In some embodiments, the window WM may include a base layer and a functional layer disposed on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM may include glass, sapphire, plastic, etc. The base layer of the window WM may include an optically transparent insulating material. For example, the base layer of the window WM may include a glass or plastic film, or a glass substrate and a plastic film bonded by an adhesive.

[0057] The window WM may include a transmissive region TA and a non-transmissive region NTA. The transmissive region TA may be connected to... Figure 1 The display areas DD-DA in the diagram overlap and have a shape corresponding to the shape of the display areas DD-DA. The non-transmissive area NTA can be... Figure 1 The non-display area DD-NDA in the diagram overlaps and has a shape corresponding to the shape of the non-display area DD-NDA. The non-transmissive area NTA can be an area with relatively low light transmittance compared to the transmissive area TA. The non-transmissive area NTA can be defined by a border pattern in a portion of the base layer of the window WM, and the area where no border pattern is arranged can be defined as the transmissive area TA. However, this disclosure is not limited to this, and a non-transmissive area NTA may not be provided.

[0058] In some embodiments, an anti-reflective layer may be disposed between the window WM and the display module DM. The anti-reflective layer reduces the reflection of external light incident on the display device DD from the outside. The anti-reflective layer may include color filters. The color filters may have an arrangement (e.g., a certain configuration or pattern arrangement). For example, the color filters may be arranged to take into account the color of light emitted from the pixels included in the display panel DP (described in more detail later). In addition, the anti-reflective layer may also include a black matrix adjacent to the color filters.

[0059] According to one or more embodiments of this disclosure, the display module DM may include a display panel DP and an input sensor ISU.

[0060] The display panel DP can be selected from any one of liquid crystal display panels, electrophoretic display panels, microelectromechanical systems (MEMS) display panels, electrowetting display panels, organic light-emitting display panels, inorganic light-emitting display panels, and quantum dot light-emitting display panels. However, this disclosure is not specifically limited thereto. In the following, by way of example, the display panel DP will be described as an organic light-emitting display panel.

[0061] The input sensor ISU may include any one selected from capacitive sensors, optical sensors, ultrasonic sensors, and electromagnetic induction sensors. The input sensor ISU may be formed on the display panel DP by a substantially continuous process, or it may be manufactured separately and then attached to the top of the display panel DP by an adhesive layer, but this disclosure is not limited to any particular embodiment.

[0062] The display device DD may further include a driver chip DC disposed on the display panel DP. The display device DD may also include a circuit board PB disposed on the display panel DP. In this embodiment, the circuit board PB may be a flexible circuit board, but this disclosure is not limited thereto. In some embodiments, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP and the main circuit board.

[0063] The driver chip DC may include driving elements (e.g., data driving circuitry) for driving the pixels of the display panel DP. Figure 2A The illustration shows a structure in which the driver chip DC is mounted on the display panel DP, but this disclosure is not limited thereto. For example, the driver chip DC may be mounted on a circuit board PB. In this embodiment, the circuit board PB and the driver chip DC, which are directly mounted on the display panel DP, may be referred to as (e.g., collectively) electronic components.

[0064] The display panel DP may include a curved area BA and a first non-curved area NBA1 and a second non-curved area NBA2 arranged therebetween in a first direction DR1, spaced apart and / or separated (e.g., spaced apart or separated) from each other.

[0065] The bending region BA can be defined as the region where the display panel DP bends along a dummy bending axis BX extending in the second direction DR2. A first non-bending region NBA1 can be defined as the region overlapping with the transmissive region TA, and a second non-bending region NBA2 can be defined as the region to which the circuit board PB is connected or mounted. When the bending region BA bends relative to the bending axis BX, the circuit board PB and the driver chip DC can bend in a direction toward the rear surface of the display panel DP and are arranged below the rear surface of the display panel DP. In some embodiments, additional components can be arranged to compensate for a step (e.g., height difference) between the rear surface of the display panel DP and the circuit board PB formed by the bending region BA.

[0066] According to one or more embodiments, in the second direction DR2, the width of the first non-curved region NBA1 may be greater than the width of the curved region BA and greater than the width of the second non-curved region NBA2. However, this disclosure is not limited to this, and the curved region BA may have a shape in which the width of the curved region BA in the second direction DR2 decreases from the first non-curved region NBA1 toward the second non-curved region NBA2, and is not limited to any one or more embodiments. For example, the curved region BA may have a shape in which the width of the curved region BA in the second direction DR2 is the same as or similar to the width of the first non-curved region NBA1 and gradually decreases along the first direction DR1 toward the second non-curved region NBA2.

[0067] like Figure 2B As shown in the diagram, because a portion of the display panel DP is bent, the circuit board PB, which is electrically bonded to the display panel DP, can be arranged on the rear surface of the display panel DP.

[0068] The housing component BC can accommodate the display module DM and can be connected to the window WM. The circuit board PB can be arranged on one end of the display panel DP and electrically connected to the reference... Figure 3 The circuit element layer DP-CL is described in more detail. In some embodiments, the display device DD may also include a motherboard, an electronic module mounted on the motherboard, a camera module, a power module, etc.

[0069] While the mobile phone terminal described above is an example of a display device DD, according to some embodiments, the display device DD may include at least two (or more) coupled electronic components. In some embodiments, the display panel DP and the driver chip DC mounted on the display panel DP may correspond to (e.g., be considered) different electronic components, and the display device DD may only be configured with (e.g., may only be constructed with) the display panel DP and the driver chip DC mounted on the display panel DP. In some embodiments, the display panel DP and the circuit board PB connected to the display panel DP may also correspond to (e.g., be considered) different electronic components, and the display device DD may only be configured with (e.g., may only be constructed with) the display panel DP and the circuit board PB connected to the display panel DP. Furthermore, in some embodiments, the display device DD may only be configured with (e.g., may only be constructed with) a motherboard and electronic modules mounted on the motherboard. Hereinafter, the display device DD according to this disclosure will be described focusing on the coupling structure of the display panel DP and the driver chip DC mounted on the display panel DP.

[0070] Figure 3 This is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0071] refer to Figure 3 The display panel (DP) may include a base layer (BL), a circuit element layer (DP-CL), a display element layer (DP-OLED), and an upper insulating layer (TFL). The input sensor (ISU) may be arranged on the upper insulating layer (TFL).

[0072] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP can be connected to... Figure 1 The display area shown in the middle diagram is DD-DA or Figure 2A The transmissive region TA in the diagram corresponds to the non-display region DP-NDA, and the non-display region DP-NDA can be associated with... Figure 1 The non-display area DD-NDA shown in the middle diagram or Figure 2A The non-transmissive region NTA is shown in the diagram.

[0073] The base layer BL may include at least one plastic film (e.g., a polymer film). The base layer BL may be a flexible substrate and includes plastic (e.g., polymer) substrates, glass substrates, metal substrates, organic / inorganic composite substrates, etc.

[0074] The circuit element layer DP-CL may include at least one intermediate insulating layer and circuit elements. The intermediate insulating layer may include at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements may include signal lines, pixel driving circuits, etc. The insulating layer, semiconductor layer, and conductive layer may be formed by coating, deposition, etc. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by photolithography and etching processes. Through these processes, semiconducting patterns, conductive patterns, signal lines, etc., are formed. Patterns arranged on the same layer may be formed by substantially the same process. In the following, the statement "patterns are formed by substantially the same process" means that the patterns are formed to include the same materials and the same stacking structure.

[0075] The display element layer of a DP-OLED may include multiple light-emitting elements. The display element layer of a DP-OLED may also include an organic layer such as a pixel-defining film.

[0076] The upper insulating layer TFL can encapsulate the display element layer DP-OLED. The upper insulating layer TFL can be disposed on the display element layer DP-OLED. The upper insulating layer TFL can overlap with the display area DP-DA and the non-display area DP-NDA. The upper insulating layer TFL can overlap with at least a portion of the non-display area DP-NDA (e.g., a portion of the non-display area DP-NDA). For example, the upper insulating layer TFL can include a thin film encapsulation layer. The thin film encapsulation layer can include a stacked structure of inorganic layers, organic layers, and inorganic layers. The upper insulating layer TFL can protect the display element layer DP-OLED from moisture, oxygen, and / or foreign matter such as dust particles. However, this disclosure is not limited thereto, and in addition to the thin film encapsulation layer, the upper insulating layer TFL may also include additional insulating layers. For example, the upper insulating layer TFL may also include an optical insulating layer for controlling the refractive index.

[0077] In one or more embodiments of this disclosure, an encapsulation substrate may be provided instead of the upper insulating layer TFL. In this case, the encapsulation substrate may be opposite to the base layer BL (e.g., it may be arranged opposite to the base layer BL (e.g., facing the base layer BL)), and the circuit element layer DP-CL and the display element layer DP-OLED may be arranged between the encapsulation substrate and the base layer BL.

[0078] The input sensor ISU can be directly disposed on the display panel DP. As used herein, the phrase "component A is directly disposed on component B" means that no separate layer (e.g., an intermediate layer) is disposed between component A and component B. In this embodiment, the input sensor ISU can be manufactured together with the display panel DP through a substantially continuous process. However, the spirit of this disclosure is not limited thereto, and the input sensor ISU can be provided as a separate panel and attached to the display panel DP via an adhesive layer. In one or more embodiments, the input sensor ISU may not be provided.

[0079] Figure 4 This is a plan view of a display panel DP according to one or more embodiments of the present disclosure.

[0080] refer to Figure 4 The display panel DP may include multiple pixels PX, gate drive circuit GDC, multiple signal lines SGL and multiple signal pads DP-PD.

[0081] Pixels PX may be arranged in the display area DP-DA. Each pixel PX includes a light-emitting element and a pixel driving circuit connected to the light-emitting element. In one or more embodiments, the light-emitting element may be an organic light-emitting element. A gate driving circuit GDC sequentially outputs gate signals to a plurality of gate lines GL (described in more detail later). The transistors of the gate driving circuit GDC and the transistors of the pixel PX may be formed using substantially the same process (e.g., a low-temperature polycrystalline silicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process). The display panel DP may also include another driving circuit that provides light emission control signals to the pixels PX.

[0082] The signal line SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Multiple gate lines GL can be connected to corresponding pixels PX among multiple pixels PX, and multiple data lines DL can be connected to corresponding pixels PX among multiple pixels PX. The power line PL can be connected to the pixel PX. The control signal line CSL provides control signals to the scan drive circuitry.

[0083] Signal lines SGL can overlap with the display area DP-DA and the non-display area DP-NDA. Multiple signal lines SGL can each include a line portion LP. Signal lines SGL can also include pad portions. Line portions LP can overlap with the display area DP-DA and the non-display area DP-NDA. Pad portions can be connected to one end of the line portion LP.

[0084] Multiple signal pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. The area where the first pad PD1 and the second pad PD2 are arranged may be defined as the first pad area PA1, and the area where the third pad PD3 is arranged may be defined as the second pad area PA2.

[0085] The first pad area PA1 can be used with... Figure 2AThe diagram illustrates the overlapping area of ​​the driver chip DC, and the second pad area PA2 may be the area overlapping with the circuit board PB. The first pad area PA1 may include a first area B1 in which a first pad PD1 is arranged and a second area B2 in which a second pad PD2 is arranged. The first pad area PA1 and the second pad area PA2 may be arranged in the non-display area DP-NDA. The first pad area PA1 and the second pad area PA2 may be spaced apart and / or separated from each other in the first direction DR1 (e.g., spaced apart or separated). As an example, two pad rows are illustrated in the first pad area PA1, but one or more embodiments of this disclosure are not limited thereto, and at least three pad rows may be arranged in the first pad area PA1.

[0086] Multiple first pads PD1 can be connected to corresponding data lines DL among multiple data lines DL. In some embodiments, first pads PD1 and second pads PD2 can be electrically connected to each other. Second pads PD2 can be connected to third pads PD3 via connection signal line SCLn.

[0087] The circuit board PB may include multiple board bump electrodes PB-BP. The board bump electrodes PB-BP may be arranged on the second direction DR2. The board bump electrodes PB-BP of the circuit board PB may contact and connect with the third pad PD3 of the second pad area PA2.

[0088] Figure 5 This is a cross-sectional view of a display panel DP of a pixel PX according to one or more embodiments of the present disclosure.

[0089] refer to Figure 5 The display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA. Multiple pixel PXs may each include a light-emitting element (OLED) and pixel driving circuitry connected to the OLED. For example, a pixel PX may include a transistor TR and an OLED.

[0090] As an example, Figure 5 The illustration shows a transistor TR, but this disclosure is not limited thereto. A pixel PX according to one or more embodiments may include two or more (e.g., seven) transistors TR and at least one capacitor, and the two or more (e.g., seven) transistors TR and the capacitor may be electrically connected to each other. However, the number of transistors TR and capacitors constituting a pixel PX is not limited to any one or more embodiments.

[0091] The display panel (DP) may include multiple insulating layers, semiconducting patterns, conductive patterns, signal lines, etc. Insulating layers, semiconductor layers, and conductive layers can be formed through coating, deposition, etc. Subsequently, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned using photolithography. This process can form semiconducting patterns, conductive patterns, signal lines, etc., included in the display element layer (DP-OLED) and the circuit element layer (DP-CL).

[0092] The base layer BL may include a synthetic resin film. The base layer BL may have a multilayer structure. For example, the base layer BL may have a three-layer structure consisting of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. In some embodiments, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. Furthermore, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc.

[0093] In one or more embodiments, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, a first insulating layer 10 to a sixth insulating layer 60, a transistor TR, a connection signal line SCLd, an upper electrode UE, a first connection electrode CNE1, and a second connection electrode CNE2.

[0094] At least one inorganic layer is disposed on the upper surface of the base layer BL. The inorganic layer may be formed of multiple layers. The barrier layer BRL may be disposed on the base layer BL. The buffer layer BFL may be disposed on the barrier layer BRL. Both the barrier layer BRL and the buffer layer BFL may be inorganic layers.

[0095] A semiconductive pattern is disposed on the buffer layer BFL. The semiconductive pattern may include polycrystalline silicon. However, this disclosure is not limited thereto, and the semiconductive pattern may include amorphous silicon or metal oxide.

[0096] Figure 5 The illustration shows a partial semiconducting pattern, and in a plan view, the semiconducting pattern can be further arranged in another region of pixel PX. The semiconducting pattern can be arranged across pixel PX according to certain rules. Depending on whether the semiconducting pattern is doped, it has different electrical properties. The semiconducting pattern may include a first region and a second region. The first region may be doped with N-type (negative) or P-type (positive) dopant. A P-type transistor includes a doped region doped with P-type dopant.

[0097] The first region may have greater conductivity than the second region and is essentially used as an electrode or signal line. The second region may be a region with a low doping concentration or undoped and essentially corresponds to the active region (or channel) of the transistor. For example, a portion of the semiconducting pattern (e.g., the first portion) may be the active region of the transistor, another portion of the semiconducting pattern (e.g., the second portion) may be the source or drain of the transistor, and yet another portion of the semiconducting pattern (e.g., the third portion) may be a connection electrode or a connection signal line.

[0098] like Figure 5 As shown in the diagram, the source S, active region A, and drain D of transistor TR can be formed by a semiconducting pattern.

[0099] Figure 5 A portion of a connection signal line SCLd formed by a semiconducting pattern is illustrated. In one or more embodiments, the connection signal line SCLd may be electrically connected to the drain of any one of a plurality of transistors in a pixel PX.

[0100] A first insulating layer 10 is disposed on a buffer layer BFL. The first insulating layer 10 may cover a semiconductive pattern. The first insulating layer 10 may overlap with a plurality of pixels PX in a common ground (e.g., as a common layer). A gate G may be disposed on the first insulating layer 10. The gate G may be part of a metal pattern. The gate G may overlap with an active region A. The gate G may be used as a mask in a process of doping the semiconductive pattern.

[0101] A second insulating layer 20 covering the gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may overlap with a plurality of pixels PX in a common ground (e.g., as a common layer). An upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the gate G of the transistor TR. The upper electrode UE may be part of a metal pattern. A portion of the gate G and the upper electrode UE overlapping that portion of the gate G may define a capacitor.

[0102] The third insulating layer 30 covering the upper electrode UE can be disposed on the second insulating layer 20. The first connection electrode CNE1 disposed on the third insulating layer 30 can be connected to the connection signal line SCLd through the contact hole CNT-1 penetrating the first insulating layer 10 to the third insulating layer 30.

[0103] The fourth insulating layer 40 covering the first connecting electrode CNE1 can be disposed on the third insulating layer 30. The first insulating layer 10 to the fourth insulating layer 40 can all be inorganic layers and / or organic layers, and can have a single-layer or multi-layer structure.

[0104] The first connecting electrode CNE1 may be disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50. In one or more embodiments, it may include both a first connecting electrode disposed on the third insulating layer 30 and covered by the fourth insulating layer 40 and a first connecting electrode disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50.

[0105] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through the contact hole CNT-2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50.

[0106] A sixth insulating layer 60 covering the second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connecting electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60.

[0107] The circuit element layer DP-CL may include multiple connection electrodes connected to the transistor TR, and some of these connection electrodes may be arranged on different layers. In some embodiments, the first connection electrode CNE1 may extend and be connected to the transistor TR. The location of the multiple connection electrodes is not limited to any one or more embodiments.

[0108] The display element layer DP-OLED may include a pixel-defining film PDL and a light-emitting element OLED. A pixel aperture OPN may be defined within the pixel-defining film PDL. The pixel aperture OPN of the pixel-defining film PDL may expose at least a portion of the first electrode AE. In this embodiment, the light-emitting region PXA may be defined to correspond to the portion of the first electrode AE ​​exposed by the pixel aperture OPN.

[0109] A hole control layer (HCL) may be commonly arranged in the emitting region (PXA) and the non-emitting region (NPXA) (e.g., as a common layer). The hole control layer (HCL) may include a hole transport layer and / or a hole injection layer. An emission layer (EML) may be arranged on the hole control layer (HCL). The emission layer (EML) may be arranged in the region corresponding to the pixel aperture (OPN). For example, the emission layer (EML) may be formed individually in each of the plurality of pixels (PX). However, this disclosure is not limited thereto, and the emission layer (EML) may be commonly formed in the plurality of pixels (PX) using an open mask.

[0110] An electronic control layer (ECL) may be disposed on an emitter layer (EML). The ECL may include an electron transport layer and / or an electron injection layer. A hole control layer (HCL) and the ECL may be commonly formed in a pixel (PX) using an open mask. A second electrode (CE) may be disposed on the ECL. The second electrode (CE) may be integrated and may be commonly disposed in multiple pixels (PX). An upper insulating layer (TFL) may be disposed on the second electrode (CE). The upper insulating layer (TFL) may include multiple thin films.

[0111] Figure 6 This is an enlarged exploded perspective view of the first pad area PA1 and the second pad area PA2 of a display device DD according to one or more embodiments of the present disclosure. For example, Figure 6 The diagram illustrates the removal of the driver chip DC and circuit board PB from the display panel DP. Because... Figure 6 The first pad PD1, the second pad PD2, the connecting signal line SCLn, and the third pad PD3 shown in the diagram can all be independently connected to... Figure 4 The first pad PD1, the second pad PD2, the connecting signal line SCLn, and the third pad PD3 shown in the diagram are the same, so a description of them will not be provided or will be provided only briefly.

[0112] refer to Figure 4 and Figure 6 The driver chip DC can be bonded to the first pad area PA1 via the first adhesive layer CF1. The circuit board PB can be bonded to the second pad area PA2 via the second adhesive layer CF2. Both the first adhesive layer CF1 and the second adhesive layer CF2 may comprise adhesive synthetic resin. Both the first adhesive layer CF1 and the second adhesive layer CF2 may be non-conductive films. For example, the first adhesive layer CF1 and the second adhesive layer CF2 may not include (e.g., exclude) (e.g., any) conductive balls (e.g., conductive particles) and may only comprise adhesive synthetic resin.

[0113] The driver chip DC may include a driver integrated circuit D-IC and a chip bump electrode DC-BP mounted in the driver chip DC. The driver integrated circuit D-IC may include an upper surface DC-US and a lower surface DC-DS, and the lower surface DC-DS may be a surface facing the first pad PD1 and the second pad PD2. The chip bump electrode DC-BP may be disposed on the lower surface DC-DS of the driver integrated circuit D-IC.

[0114] The chip bump electrode DC-BP may include a plurality of first bumps BP1 electrically connected to a plurality of first pads PD1 and a plurality of second bumps BP2 electrically connected to a plurality of second pads PD2. The plurality of first bumps BP1 may be arranged along a second direction DR2, and the plurality of second bumps BP2 may be spaced apart from the first bumps BP1 in a first direction DR1 (e.g., spaced apart or separated) and arranged along the second direction DR2.

[0115] The driver chip DC can receive a first signal from the outside via the second pad PD2 and the second bump BP2. The driver chip DC can provide a second signal generated based on the first signal to the first pad PD1 via the first bump BP1. For example, the driver chip DC may include data driving circuitry. The first signal may be an image signal as a digital signal applied (e.g., provided) from the outside, and the second signal may be a data signal as an analog signal. The driver chip DC can generate an analog voltage corresponding to the grayscale value of the image signal. The data signal can be... Figure 4 The data line DL shown in the diagram provides data to pixel PX.

[0116] In some embodiments, the first bump BP1 and the second bump BP2 may protrude from the lower surface DC-DS of the driver integrated circuit D-IC and may be exposed to the outside. When the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed in a state of contact with each other, and the second pad PD2 and the second bump BP2 may be fixed in a state of contact with each other (e.g., electrical contact and / or physical contact).

[0117] The circuit board PB may include a base layer P-BS and board bump electrodes PB-BP mounted on the circuit board PB. The circuit board PB may include an upper surface PB-US and a lower surface PB-DS, and the lower surface PB-DS may be a surface facing a third pad PD3. The board bump electrodes PB-BP may be disposed on the lower surface PB-DS of the base layer P-BS. Multiple board bump electrodes PB-BP may be electrically connected to multiple third pads PD3, respectively. The multiple board bump electrodes PB-BP may be arranged along a second direction DR2. The circuit board PB may provide image signals, drive voltages, and any other control signals to the driver chip DC.

[0118] In some embodiments, the board bump electrode PB-BP may protrude from the lower surface PB-DS of the base layer P-BS and may be exposed to the outside. When the second adhesive layer CF2 cures, the third pad PD3 and the board bump electrode PB-BP may be fixed in contact with each other (e.g., electrical contact and / or physical contact).

[0119] The electronic component may include a substrate and bump electrodes disposed on the underside of the substrate. Where the electronic component corresponds to a driver chip DC, the substrate may correspond to the driver integrated circuit D-IC of the driver chip DC, and the bump electrodes may correspond to the chip bump electrodes DC-BP. In one or more embodiments, where the electronic component corresponds to a circuit board PB, the substrate may correspond to the base layer P-BS of the circuit board PB, and the bump electrodes may correspond to the board bump electrodes PB-BP.

[0120] Figure 7A This is a schematic plan view of a first pad area PA1 and a second pad area PA2 according to one or more embodiments of the present disclosure. Figures 7B to 7D These are cross-sectional views of the first pad area PA1 and the second pad area PA2 according to one or more embodiments of this disclosure. Figure 8 This is a cross-sectional view illustrating the bonding structure of a display device DD according to one or more embodiments of the present disclosure. Figure 7B It is along Figure 7A A cross-sectional view of the first pad area PA1 and the second pad area PA2, taken by line A-A', and Figure 7C and Figure 7D All along Figure 7A A cross-sectional view of the first pad area PA1 and the second pad area PA2, taken by line B-B'.

[0121] Figures 7A to 8 The signal pad DP-PD (or signal pad structure) shown in the diagram can be used as a reference. Figure 4 and Figure 6 The first pad PD1 to the third pad PD3 described. Figure 7A The illustration shows an example of a data line DL comprising end portions DL-E and line portions DL-S with different widths as a signal line SCL, but this disclosure is not limited thereto. Here, width may refer to the length or width of the end portion DL-E or the line portion DL-S in the second direction DR2. In some embodiments, the signal line SCL may be another signal line SCL besides the data line DL, and may have a substantially uniform width without being divided into end portions DL-E and line portions DL-S. The end portion DL-E may be related to reference... Figure 4 The description corresponds to the pad portion.

[0122] In the following text, the description of the first pad area PA1, in which the data line DL is arranged, will focus on the second pad area PA2. The description of the first pad area PA1 can also be applied to the second pad area PA2, except for the connection of the signal line SCLn (see Figure 4 It is placed in the second pad area PA2 instead of outside the data line DL.

[0123] refer to Figure 7A The signal pad DP-PD may include a first conductive pattern CL1, a second conductive pattern CL2, and at least one insulating pattern SP. The first conductive pattern CL1 can be connected to the end portion DL-E of the data line DL through at least one contact hole OP-C. As an example, Figure 7A The diagram illustrates the signal pad DP-PD, which includes seven contact holes (OP-C) and six insulating patterns (SP), but the number of contact holes (OP-C) and insulating patterns (SP) is not limited to this.

[0124] In a plan view, the end portion DL-E may have a shape that extends in the first direction DR1. For example, the length or width of the end portion DL-E in the first direction DR1 may be greater than the length and width of the end portion DL-E in the second direction DR2.

[0125] In a plan view, contact holes OP-C may overlap with end portions DL-E. Multiple contact holes OP-C may be arranged along a first direction DR1. The multiple contact holes OP-C may be arranged to be spaced apart and / or separated from each other in the first direction DR1 (e.g., spaced apart or separated). In a plan view, a portion of a first conductive pattern CL1 may overlap with the contact holes OP-C.

[0126] In a plan view, the insulating pattern SP may overlap with the second conductive pattern CL2. In a plan view, the insulating pattern SP may be arranged spaced apart from and / or separated from the contact hole OP-C (e.g., spaced apart or separated). In this embodiment, multiple insulating patterns SP may be arranged along a first direction DR1. Multiple insulating patterns SP may be arranged spaced apart from and / or separated from each other along the first direction DR1 (e.g., spaced apart or separated).

[0127] In this embodiment, the insulating pattern SP can be arranged between adjacent contact holes OP-C. As an example, Figure 7A The illustration shows six insulating patterns SP arranged on six planes between the seven contact holes OP-C, but the arrangement is not limited to this.

[0128] As an example, Figure 7A The illustration shows multiple insulating patterns SP, all of which have a circular shape in a plan view, but this disclosure is not limited thereto. The planar shape of each of the multiple insulating patterns SP may be changed to an elliptical shape. Furthermore, the shapes of the insulating patterns SP are not limited to being all identical.

[0129] refer to Figures 7B to 7D The end portion DL-E can be disposed on the first insulating layer 10. The end portion DL-E can be connected with... Figure 5 The gate G shown in the diagram is arranged on the same layer. The terminal portion DL-E can be connected to the gate G (see diagram). Figure 5 It is formed using substantially the same process. The terminal portion DL-E can be connected to the gate G (see...). Figure 5 (Includes the same materials.)

[0130] However, the location of the end portion DL-E is not limited to this. In some embodiments, the end portion DL-E may be... Figure 5 The upper electrode UE shown in the diagram is arranged in the same layer, comprises the same material, and has the same stacked structure. In one or more embodiments, some of the multiple signal lines SCL can be connected to the gate G (see Figure 1). Figure 5Formed through substantially the same process, and other signals in the SCL can be connected to the upper electrode UE (see...). Figure 5 It is formed through substantially the same process.

[0131] A data line DL can be arranged on a single layer and have an integrated form, but this disclosure is not limited thereto. A data line DL may include multiple parts arranged on different layers. For example, a line section DL-S may include at least two parts.

[0132] A first conductive pattern CL1 may be disposed on the fourth insulating layer 40. The first conductive pattern CL1 can be connected to the end portion DL-E through a contact hole OP-C penetrating the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. For example, the first conductive pattern CL1 can contact the end portion DL-E through the contact hole OP-C. The second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 can be... Figure 5 The second insulating layer 20, third insulating layer 30, and fourth insulating layer 40 of the display area DP-DA shown in the figure are formed by substantially the same process. In this document, the insulating layer disposed between the end portion DL-E and the first conductive pattern CL1 can be defined as a pad insulating layer IL-P. In this embodiment, the second insulating layer 20, third insulating layer 30, and fourth insulating layer 40 can be defined as a pad insulating layer IL-P. The stacking structure of the pad insulating layer IL-P can be based on the circuit element layer DP-CL (see...). Figure 5 The stacking structure can be modified. In one or more embodiments, the contact hole OP-C may be defined by more or fewer insulating layers than the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40.

[0133] The first conductive pattern CL1 and the end portion DL-E can be distinguished by the pad insulating layer IL-P (e.g., the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40) arranged therebetween.

[0134] A second conductive pattern CL2 may be arranged on the first conductive pattern CL1. The area of ​​the second conductive pattern CL2 that does not overlap with the insulating pattern SP may contact the first conductive pattern CL1. The area of ​​the second conductive pattern CL2 that overlaps with the insulating pattern SP may contact the insulating pattern SP.

[0135] In one or more embodiments, the first conductive pattern CL1 may be related to a reference. Figure 5 The first connecting electrode CNE1 described is formed using substantially the same process, and the second conductive pattern CL2 is comparable to the reference. Figure 5 The second connecting electrode CNE2 described is formed using substantially the same process. The first conductive pattern CL1 may be associated with the first connecting electrode CNE1 (see...). Figure 5The second conductive pattern CL2 may be connected to the second connecting electrode CNE2 (see...). Figure 5 (Including the same material.) As an example, Figures 7B to 7D The illustration shows one or more embodiments in which the first conductive pattern CL1 is arranged on the fourth insulating layer 40. According to one or more embodiments, the first conductive pattern CL1 may be arranged on the third insulating layer 30, and in this case, the fourth insulating layer 40 may not be arranged in the first pad area PA1 and the second pad area PA2. However, this disclosure is not limited thereto, and / or combinations of connection electrodes formed with the first conductive pattern CL1 and the second conductive pattern CL2 using substantially the same process (e.g., any suitable combination) may be made according to the circuit element layer DP-CL (see [link to circuit element layer DP-CL]). Figure 5 Various options can be made for the stacked structure, as long as it can provide a first conductive pattern CL1 and a second conductive pattern CL2 of different layers.

[0136] As an example, the illustration shows, in a plan view, a second conductive pattern CL2 having a larger area than a first conductive pattern CL1, and the edges of the second conductive pattern CL2 extending outwards and covering the edges of the first conductive pattern CL1 (e.g., the second conductive pattern CL2 has a larger area than the first conductive pattern CL1 and extends beyond the edges of the first conductive pattern CL1, thereby covering the first conductive pattern CL1), but this disclosure is not limited thereto. In some embodiments, the second conductive pattern CL2 may have substantially the same area as the first conductive pattern CL1, and the edges of the second conductive pattern CL2 may be substantially aligned with the edges of the first conductive pattern CL1.

[0137] A portion of the second conductive pattern CL2 may include the portion overlapping the insulating pattern SP in a plan view. In a cross-sectional view, the insulating pattern SP may be disposed between the first conductive pattern CL1 and the second conductive pattern CL2. The insulating pattern SP may be disposed on the first conductive pattern CL1 and covered by the second conductive pattern CL2. The second conductive pattern CL2 may cover the upper surface of the insulating pattern SP. The insulating pattern SP may be disposed on the inside of each of the first conductive pattern CL1 and the second conductive pattern CL2 in a plan view.

[0138] In one or more embodiments, the second conductive pattern CL2 may have a multilayer structure. For example, the second conductive pattern CL2 may have a three-layer structure with a first layer, a second layer, and a third layer stacked sequentially. The second layer may have higher conductivity than the first and third layers. For example, the first and third layers may include titanium (Ti), and the second layer may include aluminum (Al).

[0139] The upper surface of the insulating pattern SP can be defined as the curved portion of the surface of the insulating pattern SP that contacts the second conductive pattern CL2. The lower surface of the insulating pattern SP can be defined as the surface of the insulating pattern SP that contacts the first conductive pattern CL1. The side surface of the insulating pattern SP can be defined as the surface connecting the upper and lower surfaces. For example, the side surface of the insulating pattern SP can be the portion of the surface of the insulating pattern SP that contacts the second conductive pattern CL2 that is orthogonal (e.g., perpendicular) to the lower surface.

[0140] The insulating pattern SP includes a first portion SP1 and a second portion SP2. The first portion SP1 is disposed on a first conductive pattern CL1. The first portion SP1 can be directly disposed on the first conductive pattern CL1. The lower surface of the first portion SP1 can correspond to the lower surface of the insulating pattern SP. The side surface of the first portion SP1 can contact the second conductive pattern CL2. The side surface of the first portion SP1 can correspond to the side surface of the insulating pattern SP. The second portion SP2 is disposed on the first portion SP1. The second portion SP2 can be directly disposed on the first portion SP1. The upper surface of the second portion SP2 can contact the second conductive pattern CL2. The upper surface of the second portion SP2 can correspond to the upper surface of the insulating pattern SP. The lower surface of the second portion SP2 can correspond to the upper surface of the first portion SP1. The lower surface of the second portion SP2 and the upper surface of the first portion SP1 can be substantially identical surfaces that match each other (e.g., in shape and size). That is, the upper surface of the first portion SP1 coincides with the lower surface of the second portion SP2.

[0141] The first part SP1 may have a cylindrical shape. For example, the first part SP1 may have a cylindrical shape or a polygonal prism shape. A cylindrical shape may refer to a shape in which the upper and lower surfaces are substantially flat and the side surfaces are substantially orthogonal (e.g., perpendicular) to the lower surface. For example, the upper and lower surfaces of the first part SP1 may be substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. Furthermore, the side surfaces of the first part SP1 may be substantially parallel to the third direction DR3.

[0142] The planar shape of the first part SP1 can be like... Figure 7A The insulating pattern SP shown in the figure has a circular shape. However, the planar shape of the first part SP1 is not limited to this and may be, for example, an elliptical or polygonal shape.

[0143] The cross-sectional shape of the first part SP1 can be as follows: Figure 7CThe first portion SP1 is shown in the diagram as a rectangle. However, the cross-sectional shape of the first portion SP1 is not limited to this and may be, for example, a square shape. The height of the first portion SP1 (its length in the third direction DR3) may be, for example, from about 0.5 μm to about 3.5 μm. The width of the first portion SP1 (its length in the second direction DR2) may be, for example, from about 1.6 μm to about 4.6 μm. The height and width of the first portion SP1 are not limited to the examples above and may vary depending on the process and specific design.

[0144] The second part SP2 may have a dome shape. For example, the second part SP2 may have a shape in which the upper surface is hemispherical. A dome shape may refer to a shape in which the lower surface is substantially flat and the upper surface includes an upwardly convex curve. For example, the lower surface of the second part SP2 may be substantially parallel to the plane defined by the first direction DR1 and the second direction DR2. Furthermore, the upper surface of the second part SP2 may have a shape that convexes in the third direction DR3.

[0145] The planar shape of the second part SP2 can be circular. However, the planar shape of the second part SP2 is not limited to this, and can be, for example, elliptical or polygonal.

[0146] like Figure 7C As shown in the diagram, the cross-sectional shape of the second part SP2 can be a shape in which the upper surface is an upwardly convex curve and the lower surface is a straight line. Figure 7C The illustration shows that the width of the second portion SP2 (the length of its lower surface in the second direction DR2) is greater than the height of the second portion SP2 (the length in the third direction DR3), but the shape of the second portion SP2 is not limited to this. For example, the width of the second portion SP2 (the length of its lower surface in the second direction DR2) may be smaller than the height of the second portion SP2 (the length in the third direction DR3). The height of the second portion SP2 may be, for example, from about 0.3 μm to about 2.3 μm. The height of the second portion SP2 is not limited to the above example and may vary depending on the process and specific design.

[0147] Because the first portion SP1 has a cylindrical shape and the second portion SP2 disposed on the first portion SP1 has a dome shape, if pressure is applied to the insulating pattern SP on the third-party DR3 (e.g., when pressure is applied to the insulating pattern SP on the third-party DR3), the first portion SP1 can withstand the pressure and maintain its restoring force, the second portion SP2 can allow the resin of the adhesive film to be expelled during bonding, and the pressure can be concentrated on the second portion SP2. Therefore, if an electronic component such as a driver chip DC is pressed and bonded to the display panel DP (e.g., when an electronic component such as a driver chip DC is pressed and bonded to the display panel DP), the pressure can be concentrated on the second portion SP2, and thus the amount of deformation of the second portion SP2 can be increased, and the film included in the second conductive pattern CL2 disposed on the second portion SP2 (e.g., the third layer described above) can be easily torn. Because the film (third layer) included in the second conductive pattern CL2 is easily torn, the second layer disposed under the third layer can be easily exposed, and this can facilitate the bonding of the second layer with the bump BP1 (see Figure 8 Contact between them.

[0148] Both the first part SP1 and the second part SP2 may comprise polymers. Both the first part SP1 and the second part SP2 may comprise thermosetting polymers. However, this disclosure is not limited thereto, and the insulating pattern SP may comprise thermoplastic polymers. The modulus (e.g., elastic modulus) of the first part SP1 may be greater than the modulus (e.g., elastic modulus) of the second part SP2. For example, the modulus of the first part SP1 may be from about 6 GPa to about 7 GPa, and the modulus of the second part SP2 may be from about 2.5 GPa to about 3 GPa.

[0149] Because the modulus of the first portion SP1 is greater than that of the second portion SP2, if pressure is applied to the insulating pattern SP on the third-party DR3 (e.g., when pressure is applied to the insulating pattern SP on the third-party DR3), the deformation rate of the first portion SP1 can be smaller, and the deformation rate of the second portion SP2 can be larger. Therefore, if an electronic component such as a driver chip DC is press-bonded to the display panel DP (e.g., when an electronic component such as a driver chip DC is press-bonded to the display panel DP), the pressure can be concentrated on the second portion SP2, and thus the deformation of the second portion SP2 can be increased, and the thin film (e.g., the third layer described above) included in the second conductive pattern CL2 disposed on the second portion SP2 can be easily torn. Because the thin film (third layer) included in the second conductive pattern CL2 is easily torn, the second layer disposed below the third layer can be easily exposed, and this can facilitate the connection between the second layer and the bump BP1 (see...). Figure 8 Contact between them.

[0150] Part 1, SP1, can be formed from a negative photoresist material. A negative photoresist material refers to the material whose unexposed portions dissolve in the developer. Part 2, SP2, can be formed from a positive photoresist material. A positive photoresist material refers to the material whose exposed portions dissolve in the developer.

[0151] The first portion SP1 can be formed from a negative photoresist material, and therefore can be formed into a cylindrical shape without additional process steps (e.g., actions or tasks). The second portion SP2 can be formed from a positive photoresist material, and therefore can be formed into a dome shape without additional process steps (e.g., actions or tasks). For example, the first portion SP1 is formed from a negative photoresist material in which the unexposed portion dissolves in the developer, thereby forming a cylindrical shape without additional process steps (e.g., actions or tasks). The second portion SP2 is formed from a positive photoresist material (where the exposed portion dissolves in the developer), thereby forming a dome shape without additional process steps (e.g., actions or tasks). (See reference...) Figures 9A to 9H The process for forming the first part SP1 and the second part SP2 is described in more detail.

[0152] Compared to other portions of the second conductive pattern CL2, the portion of the second conductive pattern CL2 that covers the insulating pattern SP may protrude further from the first conductive pattern CL1 on the third-direction DR3. This protruding portion of the second conductive pattern CL2 may be referred to as the protruding portion CL2-T. The second conductive pattern CL2 may contact the upper surface of the first conductive pattern CL1 that does not overlap with the insulating pattern SP and the upper surface of the insulating pattern SP. The protruding portion CL2-T of the second conductive pattern CL2 may correspond to the portion that contacts the upper surface of the insulating pattern SP.

[0153] refer to Figure 7D The first portion SP1-a of the insulating pattern SP-a may have a multilayer structure. The first portion SP1-a may include a first portion SP1-1 disposed on the first conductive pattern CL1 and a first portion SP1-2 disposed on the first portion SP1-1. As an example, Figure 7D The illustration shows that the first part SP1-a has a two-layer structure, but this disclosure is not limited thereto. For example, the first part SP1-a may have a structure with at least three layers.

[0154] Part 1-1, SP1-1, may have a cylindrical shape. Part 1-2, SP1-2, may have a cylindrical shape. Part 2, SP2, may have a dome shape. Both Part 1-1, SP1-1, and Part 1-2, SP1-2, may be formed from a negative photoresist material, and therefore can be formed into a cylindrical shape without additional processing. Part 2, SP2, may be formed from a positive photoresist material, and therefore can be formed into a dome shape without additional processing. In one or more embodiments, Part 1-1, SP1-1, may be formed from a negative photoresist material, and both Part 1-2, SP1-2, and Part 2, SP2, may be formed from a positive photoresist material.

[0155] Each of the modulus (e.g., elastic modulus) of part 1-1 SP1-1 and the modulus (e.g., elastic modulus) of part 1-2 SP1-2 may be greater than the modulus (e.g., elastic modulus) of part 2 SP2. Therefore, if pressure is applied to DR3 by a third party (e.g., when pressure is applied to DR3 by a third party), parts 1-1 SP1-1 and 1-2 SP1-2 can withstand the pressure and maintain the restoring force, and the pressure can be concentrated on part 2 SP2. The modulus (e.g., elastic modulus) of part 1-1 SP1-1 may be greater than the modulus (e.g., elastic modulus) of part 1-2 SP1-2, but this disclosure is not limited thereto.

[0156] As an example, Figure 8 The diagram illustrates a DC driver chip used as an electronic component. Figure 8 The diagram illustrates the chip bump electrode DC-BP of the driver chip DC (see [reference]). Figure 6 The first bump BP1 and the first pad PD1 (see) Figure 6 The contact state. First pad PD1 (see...) Figure 6 )exist Figure 8 The image shows the signal pads DP-PD.

[0157] The first bump BP1 of the driver chip DC can penetrate the first adhesive layer CF1 and can contact the second conductive pattern CL2 of the signal pad DP-PD via a bonding process. The display device DD of this disclosure may not include (e.g., may exclude) conductive balls (e.g., conductive particles), thereby preventing or reducing short circuits caused by conductive balls and / or power failures in cases where conductive balls are not arranged between the signal pad DP-PD and the bump electrode, even if the signal pads DP-PD are densely arranged, thus being advantageous or desirable for providing high-resolution panels.

[0158] In the insulating pattern SP according to this disclosure, the first portion SP1 may be formed of a negative photoresist material and thus may be formed into a cylindrical shape without additional process steps (e.g., actions or tasks). The second portion SP2 may be formed of a positive photoresist material and thus may be formed into a dome shape without additional process steps (e.g., actions or tasks).

[0159] Because the first part SP1 has a cylindrical shape and the second part SP2 arranged on the first part SP1 has a dome shape, if pressure is applied to the insulating pattern SP on the third direction DR3 (e.g., when pressure is applied to the insulating pattern SP on the third direction DR3), the first part SP1 can withstand the pressure and maintain the restoring force, the second part SP2 can allow the resin of the adhesive film to be discharged during bonding, and the pressure can be concentrated on the second part SP2.

[0160] Furthermore, because the modulus (e.g., elastic modulus) of the first part SP1 is greater than the modulus (e.g., elastic modulus) of the second part SP2, if pressure is applied to the insulating pattern SP on the third-party DR3 (e.g., when pressure is applied to the insulating pattern SP on the third-party DR3), then as Figure 8 As illustrated in the diagram, the deformation rate of the first portion SP1 can be relatively small, while the deformation rate of the second portion SP2 can be relatively large. Therefore, if an electronic component such as a driver chip DC is pressed and bonded to the display panel DP (e.g., when an electronic component such as a driver chip DC is pressed and bonded to the display panel DP), the pressure can be concentrated on the second portion SP2, and thus the deformation of the second portion SP2 can be increased, and the thin film (e.g., the third layer described above) included in the second conductive pattern CL2 disposed on the second portion SP2 can be easily torn.

[0161] Because the thin film (e.g., the third layer) included in the second conductive pattern CL2 is easily torn, the second layer disposed beneath the third layer can be easily exposed, and contact between the second layer and the bump BP1 can be facilitated. For example, in a display device DD including a display panel DP according to the present disclosure, bonding reliability can be improved, and thus initial resistance and reliability resistance can be improved.

[0162] Figures 9A to 9H All are cross-sectional views illustrating the steps (e.g., actions or tasks) of a method for manufacturing a pad area according to one or more embodiments of the present disclosure.

[0163] For ease of description, Figures 9A to 9H All illustrations show the following along Figure 7A The cross-section taken by line B-B'. Figures 9A to 9H In the middle, for reference Figures 4 to 7CThe above description can be applied to the same components, and no detailed description of them will be provided.

[0164] A method for manufacturing a display panel DP according to one or more embodiments includes providing a preliminary signal pad P-PD and forming an insulating pattern SP on the preliminary signal pad P-PD.

[0165] Figure 9A The diagram schematically illustrates a preliminary signal pad P-PD. The preliminary signal pad P-PD may include a first conductive pattern CL1 (see [reference]). Figure 7C The initial signal pads P-PD may also include the base layer BL (see...). Figure 7C ), barrier layer BRL (see Figure 7C ), buffer layer BFL (see Figure 7C ), first insulating layer 10 (see Figure 7C ), second insulating layer 20 (see Figure 7C ), third insulating layer 30 (see Figure 7C ) and the fourth insulating layer 40 (see Figure 7C ) and the terminal portion DL-E of the signal line SCL (see Figure 7C ).

[0166] Figures 9B to 9G The diagrams schematically illustrate the formation of an insulating pattern SP on the initial signal pads P-PD. Forming the insulating pattern SP includes forming a first portion SP1 and forming a second portion SP2.

[0167] Figures 9B to 9D The diagrams schematically illustrate the formation of a first portion SP1 on the initial signal pad P-PD. The first portion SP1 can be formed on the initial signal pad P-PD in the first region AR1 using a negative photoresist material NPR.

[0168] The first region AR1 may refer to the region in which the insulating pattern SP will be formed in a plan view. The second region AR2 may refer to the region adjacent to and surrounding (e.g., around) the first region AR1 in a plan view, where the insulating pattern SP will not be formed. The first region AR1 may have a circular, elliptical, or polygonal shape in a plan view.

[0169] refer to Figure 9B Forming the first portion SP1 may include applying a negative photoresist material NPR to the initial signal pad P-PD. The negative photoresist material NPR may coat the entire surface of the initial signal pad P-PD, but this disclosure is not limited thereto, and may coat a portion of the initial signal pad P-PD.

[0170] refer to Figure 9CForming the first portion SP1 may include exposing a first region AR1 of an applied negative photoresist material NPR. During exposure of the first region AR1, a first mask MSK1 may be applied. The first mask MSK1 transmits light in the first region AR1 and blocks light in a second region AR2. The light during exposure may be ultraviolet light.

[0171] refer to Figure 9D Forming the first portion SP1 may include forming the first portion SP1 in the first region AR1 by developing and curing a negative photoresist material NPR. The negative photoresist material NPR of the exposed portion (i.e., the negative photoresist material NPR of the first region AR1) can be retained. The negative photoresist material NPR of the unexposed portion (i.e., the negative photoresist material NPR of the second region AR2) can be removed by a developer. The first portion SP1 can be formed from the negative photoresist material NPR, and therefore can be formed into a cylindrical shape without additional processes.

[0172] Figures 9E to 9G The diagrams schematically illustrate the formation of a second portion SP2 on a first portion SP1. The second portion SP2 can be formed by using a positive photoresist material PPR to form the second portion SP2 on the first portion SP1.

[0173] refer to Figure 9E Forming the second portion SP2 may include applying a positive photoresist material PPR to the initial signal pad P-PD and the first portion SP1. While covering the first portion SP1, the positive photoresist material PPR may be coated on the initial signal pad P-PD on which the first portion SP1 is not formed.

[0174] refer to Figure 9F Forming the second part SP2 may include exposing a second region AR2 of the applied positive photoresist material PPR. During exposure of the second region AR2, a second mask MSK2 may be applied. The second mask MSK2 blocks light in the first region AR1 and transmits light in the second region AR2. The light during exposure may be ultraviolet light.

[0175] refer to Figure 9G Forming the second portion SP2 may include forming the second portion SP2 on the first portion SP1 by developing and curing a positive photoresist material PPR. The positive photoresist material PPR of the exposed portion (i.e., the positive photoresist material PPR of the second region AR2) can be removed. The positive photoresist material PPR of the unexposed portion (i.e., the positive photoresist material PPR of the first region AR1) can be retained. The second portion SP2 can be formed from the positive photoresist material PPR, and therefore can be formed into a dome shape without additional processes.

[0176] refer to Figure 9H One or more embodiments of the method for manufacturing a display panel DP may further include forming a second conductive pattern CL2. (See above references) Figure 7C The same description applies to the second conductive pattern CL2, and therefore no description of it will be provided.

[0177] According to the manufacturing method of the display panel disclosed herein, a cylindrical shape and a dome shape on the cylindrical shape can be provided without additional processes. Therefore, processability can be improved. Furthermore, as described above, because the insulating pattern SP includes a first portion SP1 in a cylindrical shape and a second portion SP2 in a dome shape, bonding reliability can be improved, and because the modulus (e.g., elastic modulus) of the first portion SP1 is greater than the modulus (e.g., elastic modulus) of the second portion SP2, bonding reliability can be further improved.

[0178] Based on the above description, the display panel of this disclosure may include an insulating pattern comprising pillars and domes, and thus improves bonding reliability. Furthermore, the display panel of this disclosure may include an insulating pattern comprising materials with different moduli (e.g., elastic modulus), and thus improve bonding reliability.

[0179] Furthermore, the method for manufacturing the display panel disclosed herein eliminates the need for additional processes to provide curvature for the upper surface of the insulating pattern, thereby improving processability.

[0180] For example, according to the manufacturing method of the display panel described in this disclosure, a cylindrical shape and a dome shape on the cylindrical shape can be provided without additional process steps, thereby improving processability. The insulating pattern SP includes a first cylindrical portion SP1 made of a negative photoresist material NPR and a second dome-shaped portion SP2 made of a positive photoresist material PPR. This configuration enhances bonding reliability because the first portion SP1 has a higher modulus (e.g., elastic modulus) than the second portion SP2, enabling it to better withstand pressure and maintain resilience. When pressure is applied during bonding, the second portion SP2 allows resin to drain and concentrate pressure, thereby promoting tearing of the film in the second conductive pattern CL2 and improving contact between the second layer and the bump BP1.

[0181] Furthermore, for example, the display panel of this disclosure may include an insulating pattern with materials having different moduli (e.g., elastic modulus), thereby further enhancing bonding reliability. The combination of columnar and dome shapes in the insulating pattern improves the overall bonding reliability of the display panel, thereby ensuring better initial resistance and reliability resistance.

[0182] Furthermore, for example, the manufacturing method described in this disclosure does not require additional processes to provide curvature to the upper surface of the insulating pattern, which simplifies the manufacturing process and improves processability. This method allows for the efficient production of high-resolution display panels with enhanced bonding reliability and reduced risk of short-circuit or power-on failures.

[0183] As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. As used herein, expressions such as “at least one of…,” “one of…,” and “selected from…” modify the entire column of elements before / after a column of elements, but not individual elements of that column. For example, “at least one of a, b, and c,” “at least one of a, b, or c,” and “at least one of a, c, and / or b” may indicate only a, only b, only c, both a and b (e.g., both a and b), both a and c (e.g., both a and c), both b and c (e.g., both b and c), all or variations of a, b, and c.

[0184] In describing the implementation of this application, the word "may" refers to "one or more implementations of this application".

[0185] As used herein, the term “about” and similar terms are used as approximations and not as terms of degree, and are intended to explain the inherent bias of a measured or calculated value as would be recognized by one of ordinary skill in the art. Taking into account the errors associated with the measurement and with a particular number of measurements (such as limitations of the measurement system), “about” as used herein includes the value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value.

[0186] Furthermore, any numerical ranges listed herein are intended to include all subranges of the same numerical precision falling within the listed range. For example, the range “1.0 to 10.0” is intended to include all subranges between the listed minimum value 1.0 and the listed maximum value 10.0 (and includes both the listed minimum value 1.0 and the listed maximum value 10.0), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits falling within it, and any minimum numerical limit listed herein is intended to include all higher numerical limits falling within it. Therefore, the applicant reserves the right to amend this specification (including the claims) to explicitly list any subranges falling within the range explicitly listed herein.

[0187] Here, unless otherwise specified, a step, task, or action listed in a particular order should not necessarily imply that the application or claims require that particular order. That is, the general rule is that unless the steps, tasks, or actions of a method (e.g., a method claim) are actually listed in order, they should not be interpreted as requiring a specific order.

[0188] In view of the full contents of this disclosure, those skilled in the art will recognize that various suitable features of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, the various embodiments may be implemented independently of each other or in combination with each other in any suitable way.

[0189] The display device, electronic device, means for manufacturing thereof, and / or any other related means or components according to embodiments of this application described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on a single integrated circuit (IC) chip or on separate IC chips. Furthermore, various components of the device may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in memory implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0190] Although described with reference to one or more embodiments of this disclosure, it should be understood that this disclosure is not intended to be limited to these embodiments, but rather that one or more suitable changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure as claimed in the appended claims. Therefore, the technical scope of this disclosure is not limited to what is described in the detailed description of the specification, but should be determined by the appended claims and their equivalents.

Claims

1. A display panel, characterized by, include: Pixel; Signal lines, which are electrically connected to the pixels; as well as Signal pads, which are connected to the signal lines. The signal pads include: A first conductive pattern is connected to one side portion of the signal line; A second conductive pattern, the second conductive pattern being on the first conductive pattern; and An insulating pattern comprising a first portion on the first conductive pattern and a second portion on the first portion. The first part has a cylindrical shape, and The second part has a dome shape.

2. The display panel according to claim 1, characterized in that, In a plan view, the insulating pattern is on the inside of each of the first conductive pattern and the second conductive pattern.

3. The display panel according to claim 1, characterized in that, The insulating pattern is directly on the first conductive pattern, and The second conductive pattern covers the portion of the insulating pattern and the first conductive pattern that is not covered by the insulating pattern.

4. The display panel according to claim 1, characterized in that, The first portion includes an upper surface that contacts the second portion. The second portion includes a lower surface that contacts the first portion, and The upper surface of the first part coincides with the lower surface of the second part.

5. The display panel according to claim 1, characterized in that, The first part has a quadrilateral shape in the cross-sectional view, and The second portion includes an upper surface that contacts the second conductive pattern, and the upper surface of the second portion has an upwardly convex shape.

6. The display panel according to claim 1, characterized in that, The upper and lower surfaces of the first portion are parallel to a plane defined by a first direction and a second direction.

7. The display panel according to claim 1, characterized in that, The first part has a cylindrical shape or a polygonal prism shape, and The second part has a shape with a hemispherical upper surface.

8. The display panel according to claim 1, characterized in that, The first part has a multi-layered structure.

9. The display panel according to claim 8, characterized in that, The first part has a two-layer structure.

10. An electronic device, characterized in that, include: Display module; Window, the window being on the display module; as well as A receiving component that houses the display module. The display module includes: Pixel; Signal lines, the signal lines being electrically connected to the pixels; and Signal pads, which are connected to the signal lines. The signal pads include: A first conductive pattern is connected to one side portion of the signal line; A second conductive pattern, the second conductive pattern being on the first conductive pattern; and An insulating pattern comprising a first portion on the first conductive pattern and a second portion on the first portion. The first part has a cylindrical shape, and the second part has a dome shape.

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