128mhz ultra-low noise amplifier circuit based on cascode structure

Abstract

The utility model discloses a kind of 128MHz ultra-low noise amplifier circuit based on common-source common-gate structure, comprising: input matching module, receives radio frequency input signal by π-type matching network;First-stage amplification module, the common-source common-gate structure of double-gate GaAs FET is adopted, and its input end is connected with the output end of π-type matching network;Bias circuit, including dynamic bias voltage generation module, gate voltage compensation network and drain current stabilizing circuit;Second-stage amplification module, using SiGe HBT darlington structure, for further amplifying signal and output.The utility model is cascaded with the design of the common-source common-gate structure of double-gate GaAs FET and SiGe HBT darlington structure, combined with optimized π-type matching network and source negative feedback inductance, 0.38dB of ultra-low noise coefficient and ±0.15dB of in-band gain flatness are realized, simultaneously using the dynamic bias compensation of PTAT current source and double-layer Guard Ring noise isolation technology, compared with traditional common-source structure noise reduction, applicable to low-frequency high-sensitivity demanding scene.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency communication technology, specifically a 128MHz ultra-low noise amplifier circuit based on a common source and common gate structure. Background Technology

[0002] In the existing technology, current 128MHz band amplifiers still have the following technical problems: the traditional common-source structure exhibits poor noise performance in the low-frequency band, with noise figures generally >1.5dB, which cannot meet the requirements of high-sensitivity receiving systems; the bias circuit has significant thermal noise problems, affecting the overall noise performance of the amplifier; in order to meet low noise requirements, existing input matching networks usually adopt a high Q value design, which significantly limits the amplifier's operating bandwidth; and there is a lack of effective temperature compensation mechanisms, with the operating point shifting significantly with temperature changes, leading to noise degradation.

[0003] Based on this, a 128MHz ultra-low noise amplifier circuit based on a common source and common gate structure is proposed. Utility Model Content

[0004] The purpose of this invention is to overcome or at least partially solve the above problems by proposing a 128MHz ultra-low noise amplifier circuit based on a common source and common gate structure.

[0005] To achieve the above objectives, this utility model adopts the following technical solution: a 128MHz ultra-low noise amplifier circuit based on a common source, common gate structure, comprising:

[0006] The input matching module receives radio frequency input signals through a π-type matching network, including a first capacitor C1, a first inductor L1, and a second capacitor C2 connected in sequence.

[0007] The first-stage amplification module adopts a common-source, common-gate structure composed of dual-gate GaAs FETs. Its input terminal is connected to the output terminal of the π-type matching network, which is used to amplify the matched signal with low noise.

[0008] The bias circuit, including a dynamic bias voltage generation module, a gate voltage compensation network, and a drain current stabilization circuit, is used to provide temperature-compensated bias voltage and current for the first-stage amplification module.

[0009] The interstage matching module is connected to the output of the first-stage amplification module and is used to transmit the amplified signal to the second-stage amplification module.

[0010] The second-stage amplification module, employing a SiGe HBT Darlington structure, is used to further amplify the signal and output it.

[0011] The output matching module is connected to the output of the second-stage amplification module;

[0012] The common source, common gate structure includes:

[0013] A series MOSFET M2 has its first gate G2 connected to a second capacitor C2, and its source is connected to a second inductor L2.

[0014] A series MOSFET M1 has its second gate G1 connected to a bias circuit. The source of the series MOSFET M1 is connected to the drain of the series MOSFET M2 to form a common source and common gate structure. The drain of the series MOSFET M1 is connected to an interstage matching module.

[0015] In a preferred embodiment, the first capacitor C1 is a 22pF NPO capacitor, the inductor L1 is 12nH with a Q value > 50, and the second capacitor C2 is an 18pF film capacitor.

[0016] In a preferred embodiment, the gate length of the dual-gate GaAs FET is 0.15 μm, and the second inductor L2 is 5.6 nH.

[0017] In a preferred embodiment, in the bias circuit, the dynamic bias voltage generation module includes a PTAT current source, the gate voltage compensation network includes a 1kΩ±1% thin film resistor R1 and a 100nF X7R capacitor C3, and the drain current stabilization circuit dynamically compensates for the influence of temperature changes on the drain current through a MOSFET adjustment array with a temperature sensor.

[0018] In a preferred embodiment, a noise suppression module is further included, comprising:

[0019] The power supply filtering unit consists of a three-stage π-type filter network with a cutoff frequency of 10MHz.

[0020] The substrate noise isolation ring uses a double-layer guard ring structure to surround the critical signal path;

[0021] The gold wire bonding grounding unit achieves low-impedance grounding at critical noise-sensitive nodes of the amplifier via gold wire.

[0022] Compared with existing technologies, this invention provides a 128MHz ultra-low noise amplifier circuit based on a common-source cascode structure. Through the cascade design of a common-source cascode structure composed of dual-gate GaAs FETs and a SiGe HBT Darlington structure, combined with an optimized π-type matching network and a source negative feedback inductor, an ultra-low noise figure of 0.38dB and an in-band gain flatness of ±0.15dB are achieved. At the same time, dynamic bias compensation of PTAT current source and double-layer Guard Ring noise isolation technology are adopted to ensure that the gain fluctuation is less than ±0.2dB in the range of -40℃ to 85℃ and the input VSWR is better than 1.25:1. Compared with the traditional common-source structure, the noise is reduced, making it suitable for scenarios with stringent requirements for low-frequency and high-sensitivity operation. Attached Figure Description

[0023] Figure 1 This is a structural block diagram of the present utility model;

[0024] Figure 2 This is a block diagram of the ultra-low noise matching input network of this utility model;

[0025] Figure 3 This is a block diagram of the bias circuit of this utility model;

[0026] Figure 4 This is a layout diagram of the present utility model. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings.

[0028] This specific embodiment is merely an explanation of the present utility model and is not intended to limit the present utility model. After reading this description, those skilled in the art can make creative modifications to this embodiment as needed, but as long as they are within the scope of the claims of the present utility model, they are protected by patent law.

[0029] This invention discloses a 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure, which solves the technical problems in the prior art. The overall concept is as follows:

[0030] Please see Figures 1-4 A 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure, comprising:

[0031] The input matching module receives radio frequency input signals through a π-type matching network. It includes a first capacitor C1, a first inductor L1, and a second capacitor C2 connected in sequence. The first capacitor C1 is a 22pF NPO capacitor, the inductor L1 is 12nH and has a Q value > 50, and the second capacitor C2 is an 18pF thin film capacitor.

[0032] The first-stage amplification module adopts a common-source, common-gate structure composed of dual-gate GaAs FETs. Its input is connected to the output of a π-type matching network to amplify the matched signal with low noise. The gate length of the dual-gate GaAs FET is 0.15μm.

[0033] The bias circuit, including a dynamic bias voltage generation module, a gate voltage compensation network, and a drain current stabilization circuit, is used to provide temperature-compensated bias voltage and current for the first-stage amplification module.

[0034] The interstage matching module is connected to the output of the first-stage amplification module and is used to transmit the amplified signal to the second-stage amplification module.

[0035] The second-stage amplification module, employing a SiGe HBT Darlington structure, is used to further amplify the signal and output it.

[0036] The output matching module is connected to the output of the second-stage amplification module;

[0037] Common source, common gate structure includes:

[0038] A series MOSFET M2 has its first gate G2 connected to a second capacitor C2. The source of the series MOSFET M2 is connected to a second inductor L2, which has a capacity of 5.6nH. The second inductor L2 acts as negative feedback to achieve optimal noise matching.

[0039] A series MOSFET M1 has its second gate G1 connected to a bias circuit. The source of the series MOSFET M1 is connected to the drain of the series MOSFET M2 to form a common source and common gate structure. The drain of the series MOSFET M1 is connected to an interstage matching module.

[0040] In specific implementation, the dynamic bias voltage generation module in the bias circuit includes a PTAT current source, the gate voltage compensation network includes a 1kΩ±1% thin film resistor R1 and a 100nF X7R capacitor C3, and the drain current stabilization circuit dynamically compensates for the influence of temperature changes on the drain current through a MOSFET adjustment array with a temperature sensor.

[0041] In practical implementation, it also includes a noise suppression module, which includes:

[0042] The power supply filtering unit consists of a three-stage π-type filter network with a cutoff frequency of 10MHz.

[0043] The substrate noise isolation ring uses a double-layer guard ring structure to surround the critical signal path;

[0044] The gold wire bonding grounding unit achieves low-impedance grounding at critical noise-sensitive nodes of the amplifier via gold wire.

[0045] In practical implementation, the input matching network parameters were optimized as follows: ADS simulation determined that within the range of 128±5MHz, S11<−20dB and the coincidence of the optimal noise circle and the input impedance circle>90%, indicating that the noise matching effect was good.

[0046] Bias point settings: First stage Vds=2.8V, Id=8mA. At this operating point, the noise performance of GaAs FET is optimal; Second stage Vce=3.3V, Ic=15mA. This allows the SiGe HBT Darlington structure to operate in the linear region, ensuring the linearity of signal amplification.

[0047] Layout implementation: The input stage devices adopt an interdigitated structure (8 fingers, each finger 30μm wide). The interdigitated structure can increase the aspect ratio of the device, improve the transconductance of the device, and also benefit heat dissipation and high-frequency performance. Sensitive signal paths use 45° angled traces to reduce right-angle reflections of the signal path, reduce signal integrity issues and noise radiation. The copper thickness of the power traces is ≥3μm. Thicker copper traces can reduce power trace resistance and power supply noise.

[0048] Example: Implemented using TSMC 0.18μm RFCMOS technology, chip area 1.2×0.8mm². Measured results: 1dB compression point: +12.5dBm. IIP3: +22.3dBm, an indicator of amplifier linearity; higher values ​​indicate better linearity. Power consumption: 48mW@3.3V supply, achieving low power consumption while maintaining performance.

[0049] The above description of the embodiments is provided to facilitate understanding and use of the present invention by those skilled in the art. It is obvious to those skilled in the art that various modifications can be made to the embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope of the present invention should be within the protection scope of the present invention.

Claims

1. A 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure, characterized in that, include: The input matching module receives radio frequency input signals through a π-type matching network, including a first capacitor C1, a first inductor L1, and a second capacitor C2 connected in sequence. The first-stage amplification module adopts a common-source, common-gate structure composed of dual-gate GaAs FETs. Its input terminal is connected to the output terminal of the π-type matching network, which is used to amplify the matched signal with low noise. The bias circuit, including a dynamic bias voltage generation module, a gate voltage compensation network, and a drain current stabilization circuit, is used to provide temperature-compensated bias voltage and current for the first-stage amplification module. The interstage matching module is connected to the output of the first-stage amplification module and is used to transmit the amplified signal to the second-stage amplification module. The second-stage amplification module, employing a SiGe HBT Darlington structure, is used to further amplify the signal and output it. The output matching module is connected to the output of the second-stage amplification module; The common source, common gate structure includes: A series MOSFET M2 has its first gate G2 connected to a second capacitor C2, and its source is connected to a second inductor L2. A series MOSFET M1 has its second gate G1 connected to a bias circuit. The source of the series MOSFET M1 is connected to the drain of the series MOSFET M2 to form a common source and common gate structure. The drain of the series MOSFET M1 is connected to an interstage matching module.

2. The 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure according to claim 1, characterized in that: The first capacitor C1 is a 22pF NPO capacitor, the inductor L1 is 12nH and has a Q value > 50, and the second capacitor C2 is an 18pF film capacitor.

3. The 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure according to claim 2, characterized in that: The gate length of the dual-gate GaAs FET is 0.15 μm, and the second inductor L2 is 5.6 nH.

4. The 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure according to claim 3, characterized in that: In the bias circuit, the dynamic bias voltage generation module includes a PTAT current source, the gate voltage compensation network includes a 1kΩ±1% thin film resistor R1 and a 100nF X7R capacitor C3, and the drain current stabilization circuit dynamically compensates for the influence of temperature changes on the drain current through a MOSFET adjustment array with a temperature sensor.

5. The 128MHz ultra-low noise amplifier circuit based on a common-source, common-gate structure according to claim 4, characterized in that: It also includes a noise suppression module, which includes: The power supply filtering unit consists of a three-stage π-type filter network with a cutoff frequency of 10MHz. The substrate noise isolation ring uses a double-layer guard ring structure to surround the critical signal path; The gold wire bonding grounding unit achieves low-impedance grounding at critical noise-sensitive nodes of the amplifier via gold wire.

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