MOSFET for improving device reliability

Abstract

A MOSFET designed to improve device reliability relates to the field of semiconductor technology. An active region trench is provided on the epitaxial layer, within which gate polysilicon and a first source polysilicon are spaced vertically and filled by a first dielectric layer. The first dielectric layer comprises a first gate oxide layer, a second gate oxide layer, and an insulating polysilicon oxide layer connected in sequence to form a stepped gate oxide layer. Compared to traditional device structures, this significantly increases the IPO thickness, reduces device dynamic parameters, and improves reliability, while not increasing the cost of additional photomasks in the manufacturing process.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a MOSFET that improves device reliability. Background Technology

[0002] Discrete power devices are an important category of discrete semiconductor devices, primarily used in power electronic systems for the conversion, control, and regulation of electrical energy. Among discrete power devices, Split-Gate Trench (SGT) MOSFETs have become the mainstream choice for medium- and low-voltage (30V-250V) applications due to their low gate charge (Qg), high switching speed, and figure of merit (FOM). Their core structure reduces on-resistance (Rds_on) and switching losses by using a split gate trench—isolating the gate poly from the source poly using inter-poly oxide.

[0003] Shielded gate trench (SGT) MOSFETs have become core components of high-efficiency power systems due to their excellent balance between on-resistance (Rds(on)) and gate charge (Qg). However, the existing insulated polysilicon oxide (IPO) layer design has long constrained the deep optimization of device performance, leading to increased gate-source reverse leakage current and, under extreme conditions, reliability failures. Utility Model Content

[0004] To address the above problems, this utility model provides a MOSFET that improves device reliability by avoiding increased gate-source reverse leakage current and thus preventing reliability failure, based on the original product design specifications.

[0005] The technical solution of this utility model is:

[0006] A MOSFET for improving device reliability includes, from bottom to top, a substrate, an epitaxial layer, an ILD dielectric layer, a metal layer and a passivation layer;

[0007] The epitaxial layer is provided with:

[0008] An active region trench is provided, wherein a gate polysilicon and a first source polysilicon are spaced vertically within the active region trench and filled by a first dielectric layer; the first dielectric layer includes a first gate oxide layer, a second gate oxide layer, and an insulating polysilicon oxide layer connected in sequence; the width of the second gate oxide layer is greater than the width of the first gate oxide layer.

[0009] A terminal trench, wherein a second source polysilicon is disposed in the terminal trench and filled by a second dielectric layer; the second dielectric layer extends upward to the space between the ILD dielectric layer and the epitaxial layer.

[0010] The first body region P-body is located on the side of the active region trench and extends downward from the top of the epitaxial layer;

[0011] The first source region is located at the top of the first body region P-body;

[0012] The second body region P-body is located between the terminal region trench and the active region trench, and extends downward from the top of the epitaxial layer.

[0013] The ILD dielectric layer is provided with a first metal connection region extending to the first body region P-body, a second metal connection region extending to the second body region P-body, and a third metal connection region extending to the second source polysilicon.

[0014] Specifically, the depth range of the first source region is 0.2~0.5um.

[0015] Specifically, the depth range of both the first body region P-Body and the second body region P-Body is 0.5~1.5um.

[0016] Specifically, the gate polysilicon includes an upper gate polysilicon and a lower gate polysilicon connected in sequence.

[0017] Specifically, the lateral length of the upper gate polysilicon is greater than the lateral length of the lower gate polysilicon.

[0018] Specifically, the bottom of the lower gate polysilicon has a downwardly extending boss.

[0019] This invention increases the IPO thickness by combining a stepped gate oxide layer with heavy doping of polysilicon to enhance the oxidation effect. Compared to the traditional SGT device structure, this significantly increases the IPO thickness, reduces device dynamic parameters, and improves reliability without increasing the cost of additional photomasks. It also solves the problem of electric field concentration at the gate corner due to the thin oxide layer in the design of devices with low VTH under thin gate oxide, where traditional IPOs are relatively thin. Attached Figure Description

[0020] Figure 1 This is a structural schematic diagram of step one of this utility model.

[0021] Figure 2 This is a structural schematic diagram of step two of this utility model.

[0022] Figure 3 This is a structural diagram of step three of this utility model.

[0023] Figure 4 This is a structural schematic diagram of step four of this utility model.

[0024] Figure 5This is a structural diagram of step five of this utility model.

[0025] Figure 6 This is a structural diagram of step six of this utility model.

[0026] Figure 7 This is a structural diagram of step seven of this utility model.

[0027] Figure 8 This is a structural schematic diagram of step eight of this utility model.

[0028] Figure 9 This is a structural diagram of step nine of this utility model.

[0029] Figure 10 This is a structural diagram of step ten of this utility model.

[0030] Figure 11 This is a structural schematic diagram of step eleven of this utility model.

[0031] Figure 12 This is a structural schematic diagram of step twelve of this utility model.

[0032] Figure 13 This is a structural schematic diagram of step thirteen of this utility model.

[0033] Figure 14 This is a CIS simulation graph showing the relationship between inter-poly oxide thickness and input capacitance;

[0034] In the diagram, 100 represents the substrate, 200 represents the epitaxial layer, 300 represents the ILD dielectric layer, 400 represents the metal layer, and 500 represents the passivation layer.

[0035] 600 is the active region trench, 610 is the gate polysilicon, 620 is the first source polysilicon, and 630 is the first dielectric layer.

[0036] 700 is the terminal trench, 710 is the second source polysilicon layer, and 720 is the second dielectric layer.

[0037] 810 is the first-body region (P-body), and 820 is the second-body region (P-body).

[0038] 900 is the first source pole region.

[0039] A10 First metal connection area, A20 Second metal connection area, A30 Third metal connection area. Detailed Implementation

[0040] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0041] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0042] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0043] A MOSFET for improving device reliability includes, from bottom to top, a substrate 100, an epitaxial layer 200, an ILD dielectric layer 300, a metal layer 400 and a passivation layer 500.

[0044] The epitaxial layer 200 is provided with:

[0045] An active region trench 600 is provided in which a gate polysilicon 610 and a first source polysilicon 620 are disposed vertically and spaced apart, and are filled by a first dielectric layer 630.

[0046] The gate polysilicon 610 of this invention includes an upper gate polysilicon and a lower gate polysilicon connected in sequence. The lateral length of the upper gate polysilicon is greater than the lateral length of the lower gate polysilicon. The bottom of the lower gate polysilicon is provided with a downwardly extending boss.

[0047] The first dielectric layer 630 includes a gate oxide layer 631, a gate oxide layer 632, and an insulating polycrystalline silicon oxide (IPO) 633 connected in sequence; the gate oxide layer 631 and the gate oxide layer 632 form a stepped structure with a thickness difference, that is, the lateral width of the gate oxide layer 632 is greater than the lateral width of the gate oxide layer 631.

[0048] The stepped structure design increases the IPO thickness while maintaining the same gate oxide layer (-631). The IPO thickness can be adjusted according to the product voltage, specifically defined as 30V to 150V. The distance h1 from the silicon surface to the trench bottom is 1.5µm to 6µm, the distance h2 from the bottom of the IPO to the silicon surface is 0.5µm to 1.5µm, and the distance from the bottom of the IPO to the top surface is 0.1µm to 0.4µm. Taking an 80V product as an example, the distance from the silicon surface to the trench bottom is 4.5µm, and the distance from the bottom of the IPO to the silicon surface is 1µm.

[0049] A terminal trench 700 is provided in which a second source polysilicon 710 is provided and filled by a second dielectric layer 720; the second dielectric layer 720 extends upward to between the ILD dielectric layer 300 and the epitaxial layer 200.

[0050] The first body region P-body810 is located on the side of the active region trench 600 and extends downward from the top of the epitaxial layer 200, with a gap between it and the bottom surface of the epitaxial layer 200.

[0051] The first source region 900 is located at the top of the first body region P-body 810;

[0052] The second body region P-body 820 is located between the terminal region trench 700 and the active region trench 600, and extends downward from the top of the epitaxial layer 200;

[0053] The ILD dielectric layer 300 is provided with a first metal connection region A10 extending to the first body region P-body 810, a second metal connection region A20 extending to the second body region P-body 820, and a third metal connection region A30 extending to the second source polysilicon 710.

[0054] The second dielectric layer 720 extends to the top surface of the epitaxial layer 200, serving to separate the ILD dielectric layer 300 from the passivation layer 200, the gate polysilicon 610, the first source region 900, and the second body region P-Body 820. In this case, the first metal connection region A10, the second metal connection region A20, and the third metal connection region A30 are all made of tungsten metal.

[0055] The first source polar region has a depth range of 0.2~0.5um at 900.

[0056] The depth range of both the first body region P-Body810 and the second body region P-Body820 is 0.5~1.5um.

[0057] Regardless of whether the inter-cell oxide thickness is at high or low threshold voltage (VTH), the thickness can be adjusted according to the product's dynamic parameter input capacitor CISS requirements; for example... Figure 14 The simulation of the relationship between inter-polyoxide (IP) thickness and input capacitance ciss shows that as the IPO thickness increases, the input capacitance ciss decreases.

[0058] A method for fabricating a MOSFET to improve device reliability includes the following steps:

[0059] Step 1: Grow an epitaxial layer on substrate 100, deposit silicon dioxide on the epitaxial layer to form a hard mask, and coat it with photoresist, such as... Figure 1 As shown;

[0060] Step 2: Define the trench area on the hard mask using a trench mask, form multiple trenches through an etching process, and then remove the hard mask and photoresist.

[0061] The trenches include active (cell) region trenches and terminal region trenches, such as Figure 2 As shown;

[0062] Step 3: After growing and forming the field dielectric layer (liner oxide) on the trench and epitaxial layer, source polysilicon is filled into the trench and then etched back to the trench surface, such as... Figure 3 As shown;

[0063] Step Four: As Figure 4 As shown, the area to be etched is defined using a source polysilicon photomask, and the source polysilicon is etched back. The etch-back depth depends on the product voltage, generally between 0.8 and 2 μm. After etching, the same photomask is used again to heavily dope the source polysilicon, improving the oxidation effect for subsequent IPO growth. High concentrations of phosphorus atoms entering the silicon lattice generate a large number of electrons. To maintain charge neutrality, more vacancies are generated in the silicon lattice. These vacancies provide more channels and reaction sites for oxygen atoms to diffuse in silicon, thus accelerating the oxidation reaction. A relatively thick (typically 1500A~7000A; and the thickness increases with the product breakdown voltage BV, such as 5000A~6000A for 100V products) liner oxide acts as a barrier layer for the hard mask. The heavy doping concentration is greater than 1 e 21 The dopant ion is arsenic (As).

[0064] Step 5: Without removing the photomask, use a wet process, such as... Figure 5 The field dielectric layer with a thickness of 1 / 3 to 2 / 3 of the active region trench area is removed, and the source polysilicon is etched back again with a etch depth of 1 to 2 μm.

[0065] Step Six: Remove the photomask and use a wet process to remove the remaining field oxide layer on the sidewalls of the active area trenches, such as... Figure 6 As shown;

[0066] Step Seven: As Figure 7 As shown, an oxide layer with a thickness of 500~1500 Å is grown on the active region trench to form a relatively thick inter-poly oxide. Typically, the oxide layer grown at the IPO position is 1.5~2 times thicker than the trench sidewall.

[0067] Step 8: Deposit gate polysilicon in the active region trench and etch it back to the silicon surface height, such as... Figure 8 As shown;

[0068] Step Nine: Etch back the gate polysilicon to the designed trench depth, typically between 0.6 and 2 μm; then use a wet etching process to continue etching the remaining sidewall gate oxide layer to between 300 and 1000 Å, which is the required gate oxide thickness for the device, forming gate oxide layers of varying thicknesses for the cell trenches, such as... Figure 9 As shown;

[0069] Step 10: Deposit and anneal the gate polysilicon within the source trench, such as... Figure 10 As shown;

[0070] Step 11: Ion implantation process for the P-body and source regions to form the channel region of the device, such as... Figure 11 As shown;

[0071] Step 12: Deposit the dielectric layer ILD and define the device's connection source via a photomask, such as... Figure 12 As shown;

[0072] Step 13: Sputtering of the front-side metal and deposition of the passivation layer ultimately form the complete device structure, such as... Figure 13 As shown.

[0073] Regarding the information disclosed in this case, the following points need to be clarified:

[0074] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0075] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0076] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A MOSFET for improving device reliability, characterized by, It includes a substrate (100), an epitaxial layer (200), an ILD dielectric layer (300), a metal layer (400), and a passivation layer (500) arranged sequentially from bottom to top. The epitaxial layer (200) is provided with: An active region trench (600) is provided with gate polysilicon (610) and first source polysilicon (620) spaced vertically within the active region trench (600), and is filled by a first dielectric layer (630); the first dielectric layer (630) includes a first gate oxide layer (631), a second gate oxide layer (632), and an insulating polysilicon oxide layer (633) connected in sequence; the width of the second gate oxide layer (632) is greater than the width of the first gate oxide layer (631); A terminal trench (700) is provided in which a second source polysilicon (710) is provided and filled by a second dielectric layer (720); the second dielectric layer (720) extends upward between the ILD dielectric layer (300) and the epitaxial layer (200); The first body region P-body (810) is located on the side of the active region trench (600) and extends downward from the top of the epitaxial layer (200); The first source pole region (900) is located on top of the first body region P-body (810); The second body region P-body (820) is located between the terminal region trench (700) and the active region trench (600), and extends downward from the top of the epitaxial layer (200); The ILD dielectric layer (300) is provided with a first metal connection region (A10) extending to the first body region P-body (810), a second metal connection region (A20) extending to the second body region P-body (820), and a third metal connection region (A30) extending to the second source polysilicon (710).

2. The MOSFET of claim 1, wherein, The depth range of the first source pole region (900) is 0.2~0.5um.

3. The MOSFET for improving device reliability according to claim 1, characterized in that, The depth range of the first body region P-Body (810) and the second body region P-Body (820) is 0.5~1.5um.

4. A MOSFET for improving device reliability according to claim 1, characterized in that, The gate polysilicon (610) includes an upper gate polysilicon and a lower gate polysilicon connected in sequence.

5. A MOSFET for improving device reliability according to claim 4, characterized in that, The lateral length of the upper gate polysilicon is greater than the lateral length of the lower gate polysilicon.

6. A MOSFET for improving device reliability according to claim 4, characterized in that, The bottom of the lower gate polysilicon has a downwardly extending boss.

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