A relay turn-off delay circuit

Abstract

This utility model discloses a relay disconnection delay circuit, belonging to the technical field of new energy vehicle control circuits. The relay disconnection delay circuit includes a first circuit, a second circuit, and a third circuit. The delay circuit is composed of common components such as resistors, capacitors, transistors, and MOSFETs, eliminating the need for dedicated chips to achieve the relay delay disconnection function, thus reducing design costs. Furthermore, the delay time can be controlled based on the values ​​of resistor R6 and capacitor C1.

Description

Technical Field

[0001] This utility model belongs to the field of new energy vehicle control circuit technology, specifically relating to a relay disconnection delay circuit. Background Technology

[0002] With the development of electrification and intelligentization, more and more cars are equipped with electronic and electrical systems, such as electric drive systems, power steering systems, and autonomous driving systems. The original mechanical components are being replaced by electronic devices. However, the introduction of such complex electronic and electrical systems poses a great risk to the safety of the entire vehicle. Especially in the last two years, safety accidents involving new energy vehicles have occurred frequently, and the functional safety requirements for electric vehicles are becoming increasingly stringent. Therefore, most vehicle manufacturers require that the BMS (Battery Management System) must have two or more completely independent disconnection relay functional paths when the vehicle enters a safe state, and at the same time, the disconnection of the high-voltage circuit must have a time delay function.

[0003] Currently, many BMS systems require the use of expensive PMIC chips with built-in delay functions, which are costly. Alternatively, they may use specific delay chips to achieve relay delay disconnection, which results in problems such as non-adjustable delay time, high design costs, long procurement cycles, and unstable supply. Utility Model Content

[0004] The purpose of this invention is to provide a relay disconnection delay circuit to solve the problem of high implementation cost of the delay function of existing PMIC chips mentioned in the background art.

[0005] To achieve the above objectives, this utility model provides the following technical solution: a relay disconnection delay circuit, comprising:

[0006] The first circuit includes transistors Q1 and Q2. The base of transistor Q1 is connected to the signal output terminal of the PMIC, the emitter of transistor Q2 is connected to the voltage output terminal of the PMIC, and the collector of transistor Q1 is connected to the base of transistor Q2.

[0007] The second circuit includes a MOSFET T1, a resistor R6, and a capacitor C1. The drain of the MOSFET T1 is connected to the collector of the transistor Q2. One end of the resistor R6 is grounded and the other end is connected to the drain of the MOSFET T1. One end of the capacitor C1 is grounded and the other end is connected to the drain of the MOSFET T1.

[0008] The third circuit includes transistor Q3. The emitter of transistor Q3 is connected to the voltage output terminal of PMIC, the base of transistor Q3 is connected to the gate of MOSFET T1, and the collector of transistor Q3 is the output terminal of the delay circuit.

[0009] This application uses common components such as resistors, capacitors, transistors and MOSFETs to form a delay circuit, which can realize the relay delay disconnection function without the need for a dedicated chip, thus reducing the design cost. At the same time, the delay time can be controlled based on the values ​​of resistor R6 and capacitor C1.

[0010] Furthermore, the delay circuit also includes a diode D1, the anode of which is connected to the collector of transistor Q2, and the cathode of which is connected to the drain of MOSFET T1.

[0011] Furthermore, the second circuit also includes a resistor R5, one end of which is connected to the drain of the MOSFET T1, and the other end is connected to the cathode of the diode D1.

[0012] Furthermore, the emitter of transistor Q1 is grounded.

[0013] Furthermore, the source of MOSFET T1 is grounded.

[0014] Furthermore, the input terminal of the PMIC is connected to the output terminal of an external battery.

[0015] Furthermore, the delay circuit also includes resistors R1 and R2. One end of resistor R1 is connected to the base of transistor Q1, and the other end is connected to the signal output terminal of PMIC. One end of resistor R2 is grounded, and the other end is connected to the base of transistor Q1.

[0016] Furthermore, the delay circuit also includes resistors R3 and R4. One end of resistor R3 is connected to the emitter of transistor Q2 and the other end is connected to the base of transistor Q2. One end of resistor R4 is connected to the collector of transistor Q1 and the other end is connected to the base of transistor Q2.

[0017] Furthermore, the delay circuit also includes resistors R7 and R8. One end of resistor R7 is connected to the base of transistor Q3, and the other end is connected to the emitter of transistor Q3. One end of resistor R8 is connected to the base of transistor Q3, and the other end is connected to the gate of MOSFET T1.

[0018] Furthermore, the collector of the transistor Q3 is connected to an external relay drive circuit. Attached Figure Description

[0019] Figure 1 This is a block diagram of a delay circuit. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] A relay disconnection delay circuit includes a PMIC (Power Management Integrated Circuit). The input terminal of the PMIC is connected to the output terminal of an external battery (e.g., a lead-acid battery), i.e., the output voltage of the lead-acid battery is used as the input voltage of the PMIC. The PMIC has a voltage output terminal and a signal output terminal. (Refer to...) Figure 1 The aforementioned delay circuit also includes a first circuit, a second circuit, and a third circuit.

[0022] Reference Figure 1 The first circuit includes transistors Q1 and Q2. For example, transistor Q1 is an NPN transistor, and transistor Q2 is a PNP transistor. Transistors Q1 and Q2 are combined to serve as a charging switch. Specifically, the base of transistor Q1 is connected to the signal output terminal of the PMIC, the emitter of transistor Q2 is connected to the voltage output terminal of the PMIC, the collector of transistor Q1 is connected to the base of transistor Q2, and the emitter of transistor Q1 is grounded. Correspondingly, the second circuit includes a MOSFET T1, a resistor R6, and a capacitor C1. The source of MOSFET T1 is grounded, and the drain of MOSFET T1 is connected to the transistor... The collector of Q2 is connected to the drain of MOSFET T1 via one end of resistor R6 and the other end of capacitor C1. In the second circuit, capacitor C1 acts as the charging and discharging capacitor for the delay circuit, and resistor R6 serves as the discharge resistor for capacitor C1 in the delay circuit. Without considering the relay closing delay, resistor R5 has a smaller resistance to ensure rapid charging of capacitor C1. The selection of resistor R6 and capacitor C1 needs to be based on system requirements and calculated using subsequent formulas to obtain appropriate values. Furthermore, the selection of resistor R5, resistor R6, and capacitor C1 needs to consider temperature range variations, and the smaller the temperature drift (temperature coefficient), the better.

[0023] Continue to refer to Figure 1The aforementioned third circuit includes transistor Q3. For example, transistor Q3 is a PNP transistor. Specifically, the emitter of transistor Q3 is connected to the voltage output terminal of the PMIC, the base of transistor Q3 is connected to the gate of MOSFET T1, and the collector of transistor Q3 is the output terminal of the delay circuit, that is, the collector of transistor Q3 is connected to the external relay drive circuit. In the third circuit, transistor Q3 and MOSFET T1 in the second circuit together constitute a switch for the delayed disconnect drive enable signal.

[0024] In some embodiments, the delay circuit further includes a diode D1 disposed between the collector of transistor Q2 and the drain of MOSFET T1. The anode of diode D1 is connected to the collector of transistor Q2, and the cathode of diode D1 is connected to the drain of MOSFET T1, so as to allow current to flow from the collector of transistor Q2 to the drain of MOSFET T1, that is, to unidirectionally transmit the collector signal of transistor Q2 to the drain of MOSFET T1.

[0025] In some embodiments, the second circuit further includes a resistor R5, one end of which is connected to the drain of the MOSFET T1, and the other end is connected to the cathode of the diode D1.

[0026] In some embodiments, the delay circuit further includes resistors R1 and R2. One end of resistor R1 is connected to the base of transistor Q1, and the other end is connected to the signal output terminal of PMIC. One end of resistor R2 is grounded, and the other end is connected to the base of transistor Q1. Resistors R1 and R2 can be configured as the built-in resistors of transistor Q1. The resistance values ​​of resistors R1 and R2 are 10kΩ±1%.

[0027] In some embodiments, the delay circuit further includes resistors R3 and R4. One end of resistor R3 is connected to the emitter of transistor Q2 and the other end is connected to the base of transistor Q2. One end of resistor R4 is connected to the collector of transistor Q1 and the other end is connected to the base of transistor Q2. Resistors R3 and R4 can be configured as built-in resistors of transistor Q2. The resistance values ​​of resistors R3 and R4 are 10kΩ±1%.

[0028] In some embodiments, the delay circuit further includes resistors R7 and R8, wherein one end of resistor R7 is connected to the base of transistor Q3 and the other end is connected to the emitter of transistor Q3, and one end of resistor R8 is connected to the base of transistor Q3 and the other end is connected to the gate of MOSFET T1. Resistors R7 and R8 can be configured as built-in resistors of transistor Q3, and the resistance values ​​of resistors R7 and R8 are 10kΩ±1%.

[0029] Reference Figure 1The working principle of the delay circuit is explained using the diagram. SSPB is the safety state output signal of the PMIC, and VCC is the voltage output signal of the PMIC. Under normal BMS (battery management system) conditions, SSPB is set to a high level, which turns on transistor Q1, thereby turning on transistor Q2 (circuit 1 switch is turned on). VCC then charges capacitor C1 through R5. Since there is no delay requirement when the relay is closed, the resistor R5 is generally selected to be relatively small, so that capacitor C1 charges to VCC voltage relatively quickly. The charging time t=RC. At this time, MOSFET T1 turns on (circuit 2 switch is turned on).

[0030] After MOSFET T1 is turned on, transistor Q3 is turned on, and VCC can drive the relay to close (circuit 3 switch is turned on).

[0031] When the BMS detects a fault, SSPB is set to low level, and transistors Q1 and Q2 are both turned off. Without a delay circuit, T1 and Q3 would be turned off immediately, causing the relay to disconnect immediately, thus failing to achieve the delayed disconnection function. In this application, the presence of capacitor C1 and resistor R6 allows capacitor C1 to discharge slowly through resistor R6, causing the GS terminal voltage of MOSFET T1 to decrease slowly, thereby achieving the delayed disconnection function of loop 2, which in turn achieves the delayed disconnection function of loop 3, thus realizing the delayed disconnection function of the relay.

[0032] The on-state voltage V of the MOSFET T1 can be found in the manual. GSth The recommended voltage range is such that, in order to ensure that MOSFET T1 does not turn off, the gate-source voltage V1 of T1 needs to be greater than V. GSth The minimum voltage;

[0033] If the required delay time is t, the voltage of capacitor C1 before discharge is U0=VCC, and the voltage of capacitor C1 after discharge time t is U0. t =V GSth

[0034] (1)

[0035] According to equation (1), t can be derived:

[0036] (2)

[0037] In the specific implementation plan, t is the set delay time, U0 is VCC, and U t For V GSth RC is a parameter for design selection, which can be derived and calculated using equation (2) to determine whether the RC selection meets the preliminary requirements.

[0038] Furthermore, the delay time calculation needs to consider the influence of ambient temperature, V GSthThe effects of error, the parasitic resistance and capacitance of the MOS, and the need for actual testing of the circuit under different temperature conditions are all taken into consideration. The parameters of this delay circuit are selected to meet the set delay time (i.e., the required delay time).

[0039] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A relay turn-off delay circuit characterized by comprising: include: The first circuit includes transistors Q1 and Q2. The base of transistor Q1 is connected to the signal output terminal of the PMIC, the emitter of transistor Q2 is connected to the voltage output terminal of the PMIC, and the collector of transistor Q1 is connected to the base of transistor Q2. The second circuit includes a MOSFET T1, a resistor R6, and a capacitor C1. The drain of the MOSFET T1 is connected to the collector of the transistor Q2. One end of the resistor R6 is grounded and the other end is connected to the drain of the MOSFET T1. One end of the capacitor C1 is grounded and the other end is connected to the drain of the MOSFET T1. The third circuit includes transistor Q3. The emitter of transistor Q3 is connected to the voltage output terminal of PMIC, the base of transistor Q3 is connected to the gate of MOSFET T1, and the collector of transistor Q3 is the output terminal of the delay circuit.

2. A relay turn-off delay circuit according to claim 1, characterized in that: The delay circuit also includes a diode D1, whose anode is connected to the collector of transistor Q2 and whose cathode is connected to the drain of MOSFET T1.

3. A relay turn-off delay circuit according to claim 2, characterized in that: The second circuit also includes a resistor R5, one end of which is connected to the drain of the MOSFET T1, and the other end is connected to the cathode of the diode D1.

4. The relay opening delay circuit according to claim 1, characterized by: The emitter of transistor Q1 is grounded.

5. The relay turn-off delay circuit according to claim 1, characterized by: The source of MOSFET T1 is grounded.

6. The relay turn-off delay circuit according to claim 1, characterized by: The input terminal of the PMIC is connected to the output terminal of an external battery.

7. A relay disconnection delay circuit according to claim 1, characterized in that: The delay circuit also includes resistors R1 and R2. One end of resistor R1 is connected to the base of transistor Q1, and the other end is connected to the signal output terminal of PMIC. One end of resistor R2 is grounded, and the other end is connected to the base of transistor Q1.

8. A relay disconnection delay circuit according to claim 1, characterized in that: The delay circuit also includes resistors R3 and R4. One end of resistor R3 is connected to the emitter of transistor Q2 and the other end is connected to the base of transistor Q2. One end of resistor R4 is connected to the collector of transistor Q1 and the other end is connected to the base of transistor Q2.

9. A relay disconnection delay circuit according to claim 1, characterized in that: The delay circuit also includes resistors R7 and R8. One end of resistor R7 is connected to the base of transistor Q3 and the other end is connected to the emitter of transistor Q3. One end of resistor R8 is connected to the base of transistor Q3 and the other end is connected to the gate of MOSFET T1.

10. A relay disconnection delay circuit according to claim 1, characterized in that: The collector of transistor Q3 is connected to an external relay drive circuit.

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