A planar gate SiC MOSFET device and its fabrication method
By employing N+ and P+ self-alignment processes during the fabrication of planar gate SiC MOSFET devices and utilizing a two-stage source region development and exposure process, the overlay error problem was solved, resulting in smaller cell size and better specific on-resistance, while avoiding mask alignment problems caused by wafer warping.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XILI MICROELECTRONICS (SHENZHEN) CO LTD
- Filing Date
- 2026-02-06
- Publication Date
- 2026-06-19
AI Technical Summary
In the existing technology, planar gate SiC MOSFET devices have a misalignment problem between N+ source injection and Pwell injection during the manufacturing process, which leads to device leakage and reliability issues. In addition, traditional self-alignment processes are easily affected by wafer warpage.
By changing the process steps and adopting N+ and P+ self-alignment processes, and using two source region development and exposure processes, the P+ mask alignment problem is avoided and the registration deviation is reduced. The specific steps include covering the P-type region with a nitride layer and a polysilicon layer, performing planarization treatment, and then etching to form the P+ implantation window.
It achieves a self-alignment process without P+ mask, reduces registration error, improves the accuracy of the injection window area, saves costs, enables the device to be made with smaller cell size, and optimizes the specific on-resistance.
Smart Images
Figure CN122248766A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SiC MOSFET device fabrication, and more particularly to a planar gate SiC MOSFET device and its fabrication method. Background Technology
[0002] MOSFET (Metal-oxide-semiconductor Field-Effect Transistor) devices, as one of the most important power semiconductor devices, are widely used in various circuits. Silicon carbide (SiC), as a third-generation semiconductor material, has become the representative for high-temperature, high-frequency, and high-voltage applications due to its high critical breakdown electric field, high thermal conductivity, and high electron mobility and drift velocity. Systems using silicon carbide (SiC) devices have higher conversion efficiency, thus allowing for a significant reduction in size and overall system weight.
[0003] In the prior art, silicon carbide (SiC) MOSFET devices can be divided into planar gate devices and trench gate devices in terms of device structure. Planar gate devices have a simpler structure than trench gate devices. In the manufacturing process of planar gate SiC MOSFET devices, due to the high interface state density of SiC MOSFET channels, short trenches are required to improve channel mobility. However, there is a misalignment between the traditional Pwell injection mask and the N+ injection mask, which can easily lead to inconsistent channel lengths. At the same time, impurities in silicon carbide materials require extremely high temperatures to diffuse, and excessively high temperatures will affect the material. Therefore, the existing channel formation method uses a spacer self-alignment process to form the channel, achieving N+ region implantation through a single self-alignment process. The process steps are as follows: Step 1: Form a lightly doped N-epitaxial layer on a SiC substrate; Step 2: Implant N ions into the lightly doped N-epitaxial layer to form a current diffusion layer; Step 3: Deposit a polysilicon layer on the lightly doped N-epitaxial layer, form a polysilicon etching window by exposure and development, then etch the polysilicon to form a Pwell implantation window, and then perform Al ion implantation to form a bulk region. Step 4: Deposit silicon dioxide on the lightly doped N- epitaxial layer, remove silicon dioxide by dry etching. After etching, the silicon dioxide is thickest at the sidewall of the polysilicon layer, forming the Spacer sidewall. This sidewall and the polysilicon layer together form the mask for N+ source region implantation. The width of the Spacer sidewall is the channel length. Step 5: Remove the mask and silicon dioxide, re-deposit a polysilicon mask on the lightly doped N- epitaxial layer, and etch the polysilicon mask to form a P+ implantation window.
[0004] In the aforementioned self-aligned process, due to the presence of sidewalls, there is no overlay misalignment between N+ source region injection and Pwell injection, thus the channel length can be controlled. However, for P+ injection, a new Mask-defined injection window is used, and the self-aligned process is not employed. When wafer warping and photoresist overlay misalignment occur, the injection window may deviate from the actual Mask-defined window, which can easily lead to device leakage and affect reliability. Summary of the Invention
[0005] This invention aims to at least partially solve one of the problems in related technologies. Therefore, the object of this invention is to provide a method for fabricating a planar gate SiC MOSFET device. By changing the process steps, it eliminates the need for a P+ mask, enabling self-alignment of N+ and P+ layers. This avoids mask alignment problems caused by wafer warpage, reduces registration deviation, improves the accuracy of the injection window region, saves costs, and allows for smaller cell sizes and optimized specific on-resistance.
[0006] A method for fabricating a planar gate SiC MOSFET device, wherein the planar gate SiC MOSFET device comprises a plurality of cells, each cell including, from the inside out, a JFET region, a source region, and a P-type region; the fabrication method includes: S1: An epitaxial layer and a first polysilicon layer are sequentially formed on a silicon carbide substrate; S2: Photolithography, development, and etching are performed on the first polysilicon layer to form a Pwell implantation window; Al ions are implanted into the Pwell implantation window to form a bulk region; S3: Deposit the first silicon oxide layer, and form an N+ source region implantation window mask by photolithography, development and etching of the first silicon oxide layer; perform ion implantation in the N+ source region implantation window to form the source region; S4: A first nitride layer is applied to the surface of the first silicon oxide layer above the P-type region; S5: Deposit a second silicon oxide layer, a second nitride layer, and a second polysilicon layer; the thickness of the second polysilicon layer is greater than the groove depth between the first polysilicon layers; S6: Using the second nitride layer as a barrier layer, the second polysilicon layer is planarized, and the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region are sequentially etched away to form a P+ implantation window; the P+ region is implanted by ion implantation to form a P-type region. S7: Remove the second polysilicon layer, the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer; S8: The JFET region, gate, source metal layer and drain metal layer are formed sequentially.
[0007] Furthermore, the thickness of the epitaxial layer is 5µm-25µm; the doping concentration of the epitaxial layer is 1e. 16 -5e 16 ions / cm 2 .
[0008] Further, in step S3, a first photoresist layer is coated on the surface of the first silicon oxide layer. The first silicon oxide layer located on the upper surface of the P-type region and the silicon oxide sidewall located on the sidewall of the first polysilicon layer are formed by photolithography, development and etching of the first silicon oxide layer. The silicon oxide sidewall, the first silicon oxide layer located on the upper surface of the P-type region and the first polysilicon layer form the N+ source region implantation window mask.
[0009] Furthermore, step S4 specifically includes: A first nitride layer and a photoresist layer are sequentially deposited on the surface of the first silicon oxide layer. The first nitride layer is formed on the surface of the first silicon oxide layer above the P-type region by photolithography, development, and etching of the first nitride layer.
[0010] Furthermore, the thickness of the first silicon oxide layer is 1000A-2000A, and the thickness of the first nitride layer is 500A-1000A.
[0011] Furthermore, the thickness of the second silicon oxide layer is 500A-2000A, the thickness of the second nitride layer is 500A-2000A, and the thickness of the second polysilicon layer is 10000A-40000A.
[0012] Furthermore, during the planarization process of the second polysilicon layer in step S6, the surface of the P-type region is covered with a first silicon oxide layer and a first nitride layer, making the thickness of the second polysilicon layer on the upper surface of the P-type region less than the thickness of other regions; after the planarization process of the second polysilicon layer is completed with the second nitride layer as a barrier layer, the second nitride layer on the upper surface of the P-type region is exposed, and the upper surfaces of other regions are still covered with the second polysilicon layer.
[0013] Further, in step S6, the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region are sequentially etched away. This means that the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer on the upper surface of the P-type region are sequentially etched away. The second silicon oxide layer, the second nitride layer, and the second polysilicon layer in the area outside the P-type region form a mask for the P+ region implantation window.
[0014] Further, step S8 includes: S81: Deposit a third polysilicon layer, and form a JFET implantation window by photolithography, development and etching, and form a JFET region by ion implantation; S82: Forms the gate oxide layer, the gate polysilicon layer, and the interlayer dielectric layer; S83: Forms the source metal layer and the drain metal layer.
[0015] The second objective of this application is to provide a planar gate SiC MOSFET device, which is fabricated based on the fabrication method described above.
[0016] Compared with the prior art, the technical solution provided in this application has the following advantages: After forming the N+ source region implantation window mask, this application first covers the surface of the first silicon oxide layer above the P-type region with a first nitride layer, so that the height of the upper surface of the P-type region is higher than that of other regions; then, the second silicon oxide layer, the second nitride layer, and the second polysilicon layer are deposited sequentially, and the thickness of the second polysilicon layer is greater than the groove depth between the first polysilicon layers, that is, the second polysilicon layer completely fills the gap between the first polysilicon layers; the second nitride layer is used as a barrier layer to planarize the second polysilicon layer, ensuring that when the planarization process is completed, the second polysilicon layer on the upper surface of the P-type region is completely removed, while the second polysilicon layer in the area outside the P-type region is not completely removed. The second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region are etched and removed sequentially, and the area outside the P-type region is protected by the second nitride layer, the second silicon oxide layer, and the second polysilicon layer, forming the P+ implantation window. This application enables N+ and P+ self-alignment processes by changing the process steps, eliminating the need for a P+ mask. It also avoids mask alignment problems caused by wafer warpage, reduces registration deviation, improves the accuracy of the injection window area, saves costs, and allows devices to be made with smaller cell sizes, thus optimizing the specific on-resistance. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] In the attached image: In the attached image: Figure 1 This is a schematic diagram of a planar gate SiC MOSFET structure; Figure 2 This is a schematic diagram of the epitaxial layer growth in an embodiment of the present invention; Figure 3This is a schematic diagram of the formation of the Pwell body region in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the formation of the N+ source region injection window during the first exposure of the N+ region in an embodiment of the present invention; Figure 5 This is a schematic diagram of the source region of the Pwell injection formation in an embodiment of the present invention; Figure 6 This is a schematic diagram of the second N+ region exposure in an embodiment of the present invention; Figure 7 This is a schematic diagram of the first silicon oxide layer 1 above the P-type region covered with a first nitride layer in an embodiment of the present invention; Figure 8 This is a schematic diagram of the deposition of the second silicon oxide layer, the second nitride layer, and the second polysilicon layer in an embodiment of the present invention; Figure 9 This is a schematic diagram of etching away the second polysilicon layer in an embodiment of the present invention; Figure 10 This is a schematic diagram illustrating the formation of the P+ injection window in an embodiment of the present invention; Figure 11 This is a schematic diagram of P+ injection in an embodiment of the present invention; Figure 12 This is a schematic diagram showing the process after removing the second polysilicon layer, the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer in an embodiment of the present invention. Reference numerals in the figures: 1. Substrate; 2. Epitaxial layer; 3. Bulk region; 4. Source region; 5. P-type region; 6. JFET region; 7. Gate oxide layer; 8. Gate polysilicon; 9. Interlayer dielectric layer; 10. Source metal layer; 11. Drain metal layer; 121. First polysilicon layer; 122. Second polysilicon layer; 131. First silicon oxide layer; 132. Second silicon oxide layer; 14. Photoresist; 151. First nitride layer; 152. Second nitride layer. Detailed Implementation
[0020] To provide a clearer understanding of the technical features, objectives, and effects of this invention, specific embodiments are now described in detail with reference to the accompanying drawings. In the following description, it should be understood that the orientations or positional relationships indicated by terms such as "front," "rear," "upper," "lower," "left," "right," "longitudinal," "horizontal," "vertical," "horizontal," "top," "bottom," "inner," "outer," "head," and "tail" are based on the orientations or positional relationships shown in the accompanying drawings, and are constructed and operated in a specific orientation. They are only for the convenience of describing this technical solution and do not indicate that the referred mechanism or element must have a specific orientation; therefore, they should not be construed as limitations on this invention.
[0021] It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," "fixing," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. When an component is referred to as being "on" or "below" another component, the component can be located "directly" or "indirectly" on the other component, or there may be one or more intermediary components. The terms "first," "second," "third," etc., are only for the convenience of describing this technical solution and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.
[0022] In the following description, specific details such as particular system structures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, mechanisms, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.
[0023] Example 1 like Figure 1 As shown, this application also provides a planar gate SiC MOSFET device, fabricated based on the method described below. The planar gate SiC MOSFET device comprises a plurality of cells, each cell including, from the inside out, a JFET region 6, a source region 4, and a P-type region 5; a channel is formed between the JFET region 6 and the source region 4. The source region 4 and the P-type region 5 are formed within the body region 3 by ion implantation. The gate is located above the source region 4, the channel, and the JFET region 6. The source metal layer 10 is located above the gate and connected to the source region 4 through a contact hole. The drain metal layer 11 is located on the back side of the substrate 1.
[0024] like Figures 1-12 As shown, this application also provides a method for fabricating a planar gate SiC MOSFET device, comprising: S1: An epitaxial layer 2 and a first polysilicon layer 121 are sequentially formed on a silicon carbide substrate 1; S2: Photolithography, development and etching are performed on the first polysilicon layer 121 to form a Pwell implantation window; Al ions are implanted into the Pwell implantation window to form the bulk region 3; S3: Deposit the first silicon oxide layer 131, and form the N+ source region 4 implantation window mask by photolithography, development and etching of the first silicon oxide layer 131; perform ion implantation in the N+ source region 4 implantation window to form the source region 4. S4: A first nitride layer 151 is covered on the surface of the first silicon oxide layer 131 above the P-type region 5; S5: Deposit a second silicon oxide layer 132, a second nitride layer 152, and a second polysilicon layer 122; the thickness of the second polysilicon layer 122 is greater than the groove depth between the first polysilicon layers 121; S6: Using the second nitride layer 152 as a barrier layer, planarize the second polysilicon layer 122, and sequentially etch away the second nitride layer 152, the second silicon oxide layer 132, the first nitride layer 151, and the first silicon oxide layer 131 above the P-type region 5 to form a P+ implantation window; then implant the P+ region by ion implantation to form the P-type region 5. S7: Remove the second polysilicon layer 122, the second nitride layer 152, the second silicon oxide layer 132, the first nitride layer 151, and the first silicon oxide layer 131; S8: JFET region 6, gate, source metal layer 10 and drain metal layer 11 are formed sequentially.
[0025] After forming the injection window mask of the N+ source region 4, this application first covers the surface of the first silicon oxide layer 131 above the P-type region 5 with a first nitride layer 151, making the height of the upper surface of the P-type region 5 higher than other regions; then, the second silicon oxide layer 132, the second nitride layer 152, and the second polysilicon layer 122 are deposited sequentially, and the thickness of the second polysilicon layer 122 is greater than the groove depth between the first polysilicon layers 121, that is, the second polysilicon layer 122 completely fills the gap between the first polysilicon layers; using the second nitride layer 152 as a barrier layer, the first polysilicon layer 132 is used to block the injection window mask of the P-type region 5. The second polysilicon layer 122 is planarized to ensure that at the end of the planarization process, the second polysilicon layer 122 on the upper surface of the P-type region 5 is completely removed, while the second polysilicon layer 122 outside the P-type region 5 is not completely removed. The second nitride layer 152, the second silicon oxide layer 132, the first nitride layer 151, and the first silicon oxide layer 131 above the P-type region 5 are then sequentially etched away. The area outside the P-type region 5 is protected by the second nitride layer 152, the second silicon oxide layer 132, and the second polysilicon layer 122, forming a P+ implantation window. This application, by changing the process steps, eliminates the need for a P+ mask, enabling self-alignment of N+ and P+ processes. It also avoids mask alignment problems caused by wafer warpage, reduces registration deviation, improves the accuracy of the implantation window area, saves costs, and allows for smaller cell sizes and optimized specific on-resistance.
[0026] Example 2 like Figure 1As shown, this application also provides a planar gate SiC MOSFET device, fabricated based on the method described below. The planar gate SiC MOSFET device comprises a plurality of cells, each cell including a substrate 1 and an epitaxial layer 2. The epitaxial layer 2, from the inside out, includes a JFET region 6, a source region 4, and a P-type region 5; a channel is formed between the JFET region 6 and the source region 4. The source region 4 and the P-type region 5 are formed in the body region 3 by ion implantation, and the body region 3 is formed in the epitaxial layer 2 by ion implantation. During each ion implantation process, a corresponding mask is required to form a corresponding implantation window.
[0027] The gate includes a gate oxide layer 7 and a gate polysilicon layer 8. The gate oxide layer 7 and the gate polysilicon layer 8 are located above the source region 4, the channel and the JFET region 6. The interlayer dielectric layer 9 covers the outside of the gate oxide layer 7 and the gate polysilicon layer 8. The source metal layer 10 is located above the gate. A connection via is provided in the interlayer dielectric layer 9. The source metal layer 10 is connected to the source region 4 through the connection via. The drain metal layer 11 is located on the back side of the substrate 1.
[0028] This application also provides a method for fabricating a planar gate SiC MOSFET device, comprising: S1: As Figure 2 As shown, an epitaxial layer 2 and a first polysilicon layer 121 are sequentially formed on a silicon carbide substrate 1.
[0029] The epitaxial layer 2 is a lightly doped N-type epitaxial layer 2; the thickness of the epitaxial layer 2 is 5µm-25µm; the thickness of the first polysilicon layer 121 is 10000Å-40000Å; and the doping concentration of the epitaxial layer 2 is 1e. 16 -5e 16 ions / cm 2 .
[0030] S2: As Figure 3 As shown, the first polysilicon layer 121 is photolithographically etched, developed, and etched, leaving the first polysilicon layer 121 above the JFET region 6, forming a Pwell implantation window. Al ions are implanted into the Pwell implantation window to form the Pwell region, i.e., the bulk region 3.
[0031] S3: Deposit the first silicon oxide layer 131, and form the N+ source region 4 implantation window mask by photolithography, development and etching of the first silicon oxide layer 131; perform ion implantation in the N+ source region 4 implantation window to form the source region 4.
[0032] Specifically, such as Figure 4As shown, a first silicon oxide layer 131 and a photoresist layer 14 are deposited. Through photolithography, development, and etching, a first silicon oxide layer 131 is formed on the upper surface of the P-type region 5 and on the sidewall of the first polysilicon layer 121. The thickness of the first silicon oxide layer 131 is 1000 Å-2000 Å.
[0033] Since the first polysilicon layer 121 protrudes from the surface of the bulk region 3, that is, the first silicon oxide layer 131 on the sidewall of the first polysilicon is relatively thick, after photolithography, development and etching, a silicon oxide sidewall is formed on the sidewall of the first polysilicon. The first polysilicon layer 121 masks the JFET region 6, the silicon oxide sidewall masks the channel region, and the first silicon oxide on the upper surface of the P-type region 5 masks the P-type region 5. That is, the silicon oxide sidewall, the first silicon oxide layer 131 on the upper surface of the P-type region 5 and the first polysilicon layer 121 form the N+ source region 4 implantation window mask.
[0034] like Figure 5 As shown, ion implantation is performed in the N+ source region 4 implantation window to form source region 4.
[0035] S4: A first nitride layer 151 is covered on the surface of the first silicon oxide layer 131 above the P-type region 5.
[0036] Specifically, such as Figure 6 As shown, a first nitride layer 151 and a photoresist layer 14 are sequentially deposited on the surface of the first silicon oxide layer 131. Through photolithography, development, and etching of the first nitride layer 151, the first nitride layer 151 is formed on the surface of the first silicon oxide layer 131 above the P-type region 5. Figure 7 As shown. The thickness of the first nitride layer 151 is 500 Å-1000 Å.
[0037] This step involves covering the residual first silicon oxide surface with a first nitride layer 151, which in turn covers the residual first silicon oxide layer 131. The purpose of this step is to increase the height of the cover layer on the upper surface of the P-type region 5, so as to facilitate the subsequent formation of the P+ region injection window.
[0038] S5: As Figure 8 As shown, a second silicon oxide layer 132, a second nitride layer 152, and a second polysilicon layer 122 are deposited; the thickness of the second polysilicon layer 122 is greater than the groove depth between the first polysilicon layers 121.
[0039] The thickness of the second silicon oxide layer 132 is 500 Å-2000 Å, the thickness of the second nitride layer 152 is 500 Å-2000 Å, and the thickness of the second polysilicon layer 122 is 10000 Å-40000 Å. That is, the thickness of the second silicon oxide layer 132 and the second nitride layer 152 is relatively small, while the thickness of the second polysilicon layer 122 is relatively large. The second polysilicon layer 122 needs to completely fill the gap between the silicon oxide sidewalls and the remaining first silicon oxide layer 131; and after filling the second polysilicon layer 122, the entire upper surface of the substrate 1 is basically flush.
[0040] S6: As Figure 9 As shown, the second polysilicon layer 122 is planarized using the second nitride layer 152 as a barrier layer. The planarization process can specifically be chemical mechanical polishing or wet etching. During the planarization of the second polysilicon layer 122, the surface of the P-type region 5 is covered by the first silicon oxide layer 131 and the first nitride layer 151, making the thickness of the second polysilicon layer 122 on the upper surface of the P-type region 5 less than the thickness of other regions. After the planarization of the second polysilicon layer 122 using the second nitride layer 152 as a barrier layer is completed, the second nitride layer 152 on the upper surface of the P-type region 5 is exposed, while the upper surfaces of other regions are still covered by the second polysilicon layer 122.
[0041] like Figure 10 As shown, the second nitride layer 152, the second silicon oxide layer 132, the first nitride layer 151, and the first silicon oxide layer 131 above the P-type region 5 are sequentially etched away using either dry etching or wet etching. When etching the second nitride layer 152, the second silicon oxide layer 132 is used as an etching barrier layer. When etching the second silicon oxide layer 132, the first nitride layer 151 is used as an etching barrier layer. When etching the first nitride layer 151, the first silicon oxide layer 131 is used as an etching barrier layer. When etching the first silicon oxide layer 131, the body region 3 is used as an etching barrier layer. Since the upper surface of the area outside the P-type region 5 still has a second polysilicon layer 122 remaining, during the etching process described above, only the second nitride layer 152, the second silicon oxide layer 132, the first nitride layer 151, and the first silicon oxide layer 131 above the P-type region 5 are etched. The area outside the P-type region 5 is still covered by the first silicon oxide layer 131, the first nitride layer 151, the second silicon oxide layer 132, the second nitride layer 152, and a small amount of the second polysilicon layer 122. The small amount of the second polysilicon layer 122 provides a shielding protection for the first silicon oxide layer 131, the first nitride layer 151, the second silicon oxide layer 132, and the second nitride layer 152 below them. The second silicon oxide layer 132, the second nitride layer 152, and the second polysilicon layer 122 in the area outside the P-type region 5 form a mask for the P+ region implantation window; the final P+ implantation window is as follows: Figure 10 As shown.
[0042] like Figure 11 As shown, P+ region implantation is performed by high-temperature ion implantation to form P-type region 5; In this application, when forming the P+ region implantation window, a first nitride layer 151, a second silicon oxide layer 132, a second nitride layer 152, and a second polysilicon layer 122 are sequentially deposited on the surface of the first silicon oxide layer 131. The purpose of depositing the first nitride layer 151 is to raise the height of the upper surface of the P-type region 5. While ensuring that the second polysilicon layer 122 is flush, the thickness of the second polysilicon layer 122 on the upper surface of the P-type region 5 is smaller than that in other regions. In this way, when the second polysilicon layer 122 is planarized, the second polysilicon layer 122 on the upper surface of the P-type region 5 can be completely removed, while the second polysilicon layer 122 in the regions other than the P-type region 5 is retained.
[0043] The second polysilicon layer 122, which has a relatively large deposition thickness, is deposited to completely fill the groove between the first silicon oxide layer 131 and the silicon oxide sidewall, and a mask is also formed in the groove area.
[0044] The reason for using the second silicon oxide layer 132 and the second nitride layer 152 simultaneously to form the P+ region implantation window is to avoid over-etching during planarization removal of the second polysilicon layer 122. That is, if the second polysilicon layer 122 outside the P-type region 5 is over-etched, and there is only one dielectric layer between the second polysilicon layer 122 and the first polysilicon layer 121, then when the dielectric layer above the P-type region 5 is etched away, that dielectric layer will also be etched away, which means that a mask for the JFET region 6 and the channel region cannot be formed. In this application, a second silicon oxide layer 132 and a second nitride layer 152 are deposited sequentially. Even when the second polysilicon layer 122 is removed during planarization, there is an over-etching phenomenon. Since an additional first nitride layer 151 is added to the upper surface of the P-type region 5, the dielectric layer on the upper surface of the P-type region 5 and the upper surface of other regions are different after over-etching. At this time, by utilizing the different materials of the dielectric layer in different regions, the corresponding etching solution can be selected to remove the dielectric layer on the upper surface of the P-type region 5 and retain the dielectric layer on the upper surface of other regions.
[0045] S7: Remove the second polysilicon layer 122, the second nitride layer 152, the second silicon oxide layer 132, the first nitride layer 151, and the first silicon oxide layer 131; as follows Figure 12 As shown.
[0046] S8: JFET region 6, gate, source metal layer 10, and drain metal layer 11 are formed sequentially; specifically including: S81: Deposit a third polysilicon layer, and form a JFET implantation window by photolithography, development and etching, and form JFET region 6 by high-temperature ion implantation; the thickness of the third polysilicon layer is 10000A-40000A.
[0047] S82: Form gate oxide layer 7 and gate polysilicon layer 8; the thickness of the gate oxide layer is 400A-1000A, and the thickness of the gate polysilicon layer 8 is 4000A-8000A.
[0048] After photolithography, development, and etching, interlayer dielectric layer 9 is deposited, and interconnecting vias are formed in interlayer dielectric layer 9 after photolithography.
[0049] S83: After sputtering metal on the front side of substrate 1, photolithography, development, and etching are performed to form the source metal layer 10. The source metal layer 10 is connected to the source region 4 through a via. The source metal layer 10 forms an ohmic contact with the epitaxial layer 2 and the source region 4. A metal layer is deposited on the back side of substrate 1 to form the drain metal layer 11. The final device is as follows: Figure 1 As shown.
[0050] This application achieves N+ and P+ self-alignment processes by utilizing a two-stage source region 4 development and exposure process, eliminating the need for a P+ mask. This avoids mask alignment issues caused by wafer warpage, reduces registration deviation, and improves the accuracy of the implantation window area. The first source region 4 development and exposure occurs during… Figures 4-5 When the N+ source region 4 injection window is formed, the second source region 4 exposure occurs. Figures 6-7 When forming the first nitride layer 151 covering the first silicon oxide layer 131.
[0051] This application achieves P+ self-aligned implantation by adding an exposure, development, and etching process to the Pwell implantation and N+ implantation processes, thereby saving costs. Unlike the existing technology where P+ implantation requires an additional mask, the P+ self-aligned process enables the device to have a smaller cell size and optimize the specific on-resistance.
[0052] It is understood that the above embodiments only illustrate preferred embodiments of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can freely combine the above technical features without departing from the concept of the present invention, and can also make several modifications and improvements, all of which fall within the protection scope of the present invention. Therefore, all equivalent transformations and modifications made with respect to the scope of the claims of the present invention should fall within the scope of the claims of the present invention.
Claims
1. A method for fabricating a planar gate SiC MOSFET device, characterized in that, The planar gate SiC MOSFET device comprises several cells, each cell including, from the inside out, a JFET region, a source region, and a P-type region; the fabrication method includes: S1: An epitaxial layer and a first polysilicon layer are sequentially formed on a silicon carbide substrate; S2: Photolithography, development, and etching are performed on the first polysilicon layer to form a Pwell implantation window; Al ions are implanted into the Pwell implantation window to form a bulk region; S3: Deposit the first silicon oxide layer, and form an N+ source region implantation window mask by photolithography, development and etching of the first silicon oxide layer; perform ion implantation in the N+ source region implantation window to form the source region; S4: A first nitride layer is applied to the surface of the first silicon oxide layer above the P-type region; S5: Deposit a second silicon oxide layer, a second nitride layer, and a second polysilicon layer; the thickness of the second polysilicon layer is greater than the groove depth between the first polysilicon layers; S6: Using the second nitride layer as a barrier layer, the second polysilicon layer is planarized, and the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region are sequentially etched away to form a P+ implantation window; the P+ region is implanted by ion implantation to form a P-type region. S7: Remove the second polysilicon layer, the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer; S8: The JFET region, gate, source metal layer and drain metal layer are formed sequentially.
2. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, The thickness of the epitaxial layer is 5um-25um; the doping concentration of the epitaxial layer is 1e 16 -5e 16 ions / cm 2 .
3. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, In step S3, a first photoresist layer is coated on the surface of the first silicon oxide layer. The first silicon oxide layer located on the upper surface of the P-type region and the silicon oxide sidewall located on the sidewall of the first polysilicon layer are formed by photolithography, development and etching of the first silicon oxide layer. The silicon oxide sidewall, the first silicon oxide layer located on the upper surface of the P-type region and the first polysilicon layer form the N+ source region implantation window mask.
4. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, Step S4 specifically includes: A first nitride layer and a photoresist layer are sequentially deposited on the surface of the first silicon oxide layer. The first nitride layer is formed on the surface of the first silicon oxide layer above the P-type region by photolithography, development, and etching of the first nitride layer.
5. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, The thickness of the first silicon oxide layer is 1000A-2000A, and the thickness of the first nitride layer is 500A-1000A.
6. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, The thickness of the second silicon oxide layer is 500A-2000A, the thickness of the second nitride layer is 500A-2000A, and the thickness of the second polysilicon layer is 10000A-40000A.
7. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, In step S6, when the second polysilicon layer is planarized, the surface of the P-type region is covered with a first silicon oxide layer and a first nitride layer, so that the thickness of the second polysilicon layer on the upper surface of the P-type region is less than the thickness of other regions. After the second polysilicon layer is planarized with the second nitride layer as a barrier layer, the second nitride layer on the upper surface of the P-type region is exposed, and the upper surfaces of other regions are still covered with the second polysilicon layer.
8. The method for fabricating a planar gate SiC MOSFET device according to claim 7, characterized in that, In step S6, the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region are etched and removed sequentially. This means that the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer on the upper surface of the P-type region are etched and removed sequentially. The second silicon oxide layer, the second nitride layer, and the second polysilicon layer in the area outside the P-type region form a mask for the P+ region implantation window.
9. The method for fabricating a planar gate SiC MOSFET device according to claim 1, characterized in that, Step S8 includes: S81: Deposit a third polysilicon layer, and form a JFET implantation window by photolithography, development and etching, and form a JFET region by ion implantation; S82: Forms the gate oxide layer, the gate polysilicon layer, and the interlayer dielectric layer; S83: Forms the source metal layer and the drain metal layer.
10. A planar gate SiC MOSFET device, characterized in that, Prepared according to the preparation method described in any one of claims 1-9.