A non-linear node explorer

Abstract

This invention relates to a nonlinear node detector, comprising an RF signal processing module, a baseband signal processing module, and a logic control module. The baseband signal processing module is connected to both the RF signal processing module and the logic control module. This invention uses dual VCOs to isolate DC interference, which not only enhances signal quality but also improves the system's anti-interference capability and reduces the impact of DC components on mixer performance. By improving polyphase coding technology to generate an optimized fundamental frequency, the signal-to-noise ratio and detection accuracy are effectively improved. Combined with Kalman filtering to suppress noise and polyphase decoding to improve the harmonic signal-to-noise ratio, real-time spectrum analysis and target type identification are achieved. It can automatically select the frequency point with the least interference for operation, further improving anti-interference capability.

Description

Technical Field

[0001] This utility model relates to the field of nonlinear node detection technology, and in particular to a nonlinear node detector. Background Technology

[0002] With the increasing sophistication and technological advancements in eavesdropping on classified activities, information security has become an indispensable and crucial barrier in the national security system. Nonlinear nodal detectors, as core equipment for physical environment security detection, are finding increasingly widespread and in-depth applications in both military and civilian sectors, including public security technical investigation, armed police security checks and bomb disposal, and physical environment security inspections of important locations. However, most commercially available nonlinear nodal detectors are concentrated in the 0.9GHz or 2.4GHz frequency bands and are primarily imported, making it difficult to effectively identify ultra-small electronic devices manufactured using processes below 7 nanometers, posing new challenges to information security protection.

[0003] The existing technology has the following main drawbacks:

[0004] 1. Low-frequency detection failure:

[0005] Most existing devices use carrier frequencies of 0.9 GHz or 2.4 GHz, which are difficult to effectively detect microelectronic devices with processes below 7 nanometers.

[0006] As semiconductor technology advances to smaller processes (such as 5 nanometers and 7 nanometers), traditional frequency band detectors are unable to cope with the latest miniature eavesdropping devices.

[0007] 2. Weak anti-interference capability:

[0008] The 2.4GHz band overlaps with the frequency bands of wireless devices such as Wi-Fi and Bluetooth, and the fixed frequency transmission mode is susceptible to interference from other devices on the same frequency.

[0009] Multipath effects cause severe distortion of echo signals, and the anti-interference algorithms of traditional equipment are slow to respond to dynamic interference.

[0010] 3. High-end products rely on imports, resulting in an unbalanced supply structure:

[0011] Currently, the market mainly relies on imports for nonlinear node detectors, and there is a lack of domestic production capacity.

[0012] When faced with targets in stealth modes such as shutdown or standby, existing equipment cannot capture harmonic characteristics in the inactive state, resulting in a detection blind zone.

[0013] 4. Lagging technology iteration and insufficient scenario coverage:

[0014] Mainstream equipment performs poorly in detecting ultra-small devices and in complex interference environments due to technological bottlenecks, but it still dominates the market.

[0015] The ability to protect against semiconductor process iterations and new electronic threats is lagging behind, failing to meet the needs of military, classified, and public safety scenarios for "precision, efficiency, and full adaptability".

[0016] 5. Weak industrial synergy, making it difficult to build a closed-loop ecosystem:

[0017] There is a disconnect between research and development and application in the field of nonlinear node detectors in China, resulting in low efficiency in the transformation of scientific research results.

[0018] Industry standards lag behind technological development, allowing low-quality, low-priced products to take advantage of standard gaps and crowd out the market, thus inhibiting the iteration of innovative products. Utility Model Content

[0019] This invention proposes a nonlinear node detector to solve the problems mentioned in the prior art.

[0020] To achieve the above objectives, this utility model provides the following technical solution:

[0021] A nonlinear node detector includes a radio frequency signal processing module, a baseband signal processing module, and a logic control module;

[0022] The radio frequency signal processing module adopts a two-stage filtering structure and is connected to the baseband signal processing module.

[0023] The baseband signal processing module is based on an FPGA, which is connected to the radio frequency signal processing module and the logic control module.

[0024] The logic control module is based on an STM32 microcontroller and is connected to the baseband signal processing module via the FSMC bus.

[0025] As a further technical solution of this utility model: the radio frequency signal processing module includes a radio frequency switch circuit, a transmitter, and a receiver. The transmitter includes two transmitting-end low-pass filter circuits, a transmitting-end frequency synthesis circuit, a transmitting-end quadrature modulation circuit, a radio frequency power amplifier circuit, a second low-pass filter circuit, and a transmitting antenna. The two transmitting-end low-pass filter circuits and the transmitting-end frequency synthesis circuit are both connected to the transmitting-end quadrature modulation circuit. The transmitting-end quadrature modulation circuit, the radio frequency power amplifier circuit, the second low-pass filter circuit, and the transmitting antenna are connected in sequence. The receiver includes a receiving antenna, a band-pass filter circuit, a receiving-end frequency synthesis circuit, a receiving-end quadrature modulation circuit, two radio frequency filter amplifier circuits, and two receiving-end low-pass filter circuits connected in sequence. The receiving antenna is connected to the receiving-end quadrature modulation circuit through the radio frequency switch circuit and the band-pass filter circuit. The receiving-end quadrature modulation circuit is connected to the receiving-end frequency synthesis circuit and the two radio frequency filter amplifier circuits respectively. The two radio frequency filter amplifier circuits are connected to the two receiving-end low-pass filter circuits in sequence.

[0026] As a further technical solution of this utility model: the baseband signal processing module includes an FPGA core circuit, an ADC circuit and a DAC circuit. The FPGA core circuit is connected to the ADC circuit and the DAC circuit respectively. The DAC circuit is connected to the two transmitting end low-pass filter circuits of the transmitter. The two receiving end low-pass filter circuits of the receiver are connected to the ADC circuit. The FPGA core circuit is also connected to the receiving end frequency synthesis circuit and the transmitting end frequency synthesis circuit respectively.

[0027] As a further technical solution of this utility model: the logic control module includes a human-computer interaction platform, an STM32 core circuit, an early warning circuit, and a power monitoring module. The STM32 core circuit is connected to the FPGA core circuit, the human-computer interaction platform, the early warning circuit, and the power monitoring module, respectively.

[0028] As a further technical solution of this utility model: the passband of the bandpass filter is 3.56GHz-3.64GHz, and the stopband rejection is ≥30dB.

[0029] As a further technical solution of this utility model: the transmitting antenna and the receiving antenna are circularly polarized ultra-wideband planar spiral antennas, which adopt an Archimedean spiral structure. The arm length of the Archimedean spiral structure is 1 / 4 of the wavelength corresponding to 3.6GHz, the radiation efficiency is ≥85%, and the axial ratio is ≤3dB.

[0030] As a further technical solution of this utility model: the FPGA core circuit adopts the XILINX A7 series XC7A100T chip, the signal output terminal of the FPGA core circuit is connected to the input terminal of the DAC circuit, the signal input terminal of the FPGA core circuit is connected to the output terminal of the ADC circuit, and the control terminal of the FPGA core circuit is connected to the STM32 core circuit of the logic control module through the FSMC bus, with a data transmission rate ≥100Mbps.

[0031] As a further technical solution of this utility model: the STM32 core circuit adopts the STM32F767 chip with ARM Cortex-M7 core.

[0032] As a further technical solution of this utility model: the logic control module also includes a FLASH circuit, the input terminal of which is connected to the STM32 core circuit and is used to store system firmware and detection historical data.

[0033] As a further technical solution of this utility model: the human-computer interaction platform includes a 3.5-inch capacitive touch screen, the signal interface of the touch screen is connected to the STM32 core circuit of the logic control module, and is used to set system operating parameters and display detection results. The resolution of the touch screen is ≥480×320 pixels.

[0034] The technical effects and advantages provided by this utility model in the above technical solution are as follows:

[0035] Carrier frequency selection: This invention also uses a 3.6GHz carrier frequency for signal transmission and reception, but further optimizes the signal processing algorithm and system architecture, improving detection accuracy and anti-interference capability.

[0036] Dual VCO design: This invention uses dual VCOs to isolate DC interference, which not only enhances signal quality but also improves the system's anti-interference capability and reduces the impact of DC components on mixer performance.

[0037] Polyphase coding technology: This invention generates an optimized fundamental frequency by improving polyphase coding technology, which effectively improves the signal-to-noise ratio and detection accuracy of the signal.

[0038] Kalman filtering and polyphase decoding: This invention combines Kalman filtering to suppress noise and polyphase decoding to improve the harmonic signal-to-noise ratio, thereby realizing real-time spectrum analysis and target type identification.

[0039] Automatic frequency selection: This invention can automatically select the frequency point with the least interference to operate, further improving the anti-interference capability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a hardware block diagram of the present invention.

[0042] Figure 2 This is the circuit diagram for the logic control module.

[0043] Figure 3 This is a schematic diagram of the present invention.

[0044] Figure 4 This is a diagram showing the processing of the transmitted waveform signal.

[0045] Figure 5 This is a diagram showing the processing of the received waveform signal. Detailed Implementation

[0046] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0047] It should be noted that the terms "vertical," "horizontal," "up," "down," "left," "right," and similar expressions used in this article are for illustrative purposes only and do not represent the only possible implementation.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used herein in the description of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention; the term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] Example 1, as Figures 1-5 As shown, this utility model provides a nonlinear node detector, including a radio frequency signal processing module, a baseband signal processing module, and a logic control module, wherein the baseband signal processing module is connected to the radio frequency signal processing module and the logic control module respectively.

[0050] The radio frequency (RF) signal processing module includes an RF switch circuit, a transmitter, and a receiver. The transmitter includes two transmitter low-pass filter circuits, a transmitter frequency synthesis circuit, a transmitter quadrature modulation circuit, an RF power amplifier circuit, a second low-pass filter circuit, and a transmitting antenna. The two transmitter low-pass filter circuits and the transmitter frequency synthesis circuit are both connected to the transmitter quadrature modulation circuit. The transmitter quadrature modulation circuit, the RF power amplifier circuit, the second low-pass filter circuit, and the transmitting antenna are connected in sequence. The receiver includes a receiving antenna, a band-pass filter circuit, a receiving frequency synthesis circuit, a receiving quadrature modulation circuit, two RF filter amplifier circuits, and two receiving low-pass filter circuits connected in sequence. The receiving antenna is connected to the receiving quadrature modulation circuit through the RF switch circuit and the band-pass filter circuit. The receiving quadrature modulation circuit is connected to the receiving frequency synthesis circuit and the two RF filter amplifier circuits, respectively. The two RF filter amplifier circuits are connected to the two receiving low-pass filter circuits in sequence.

[0051] The baseband signal processing module includes an FPGA core circuit, an ADC circuit, and a DAC circuit. The FPGA core circuit is connected to the ADC circuit and the DAC circuit respectively. The DAC circuit is connected to the two transmitting end low-pass filter circuits of the transmitter. The two receiving end low-pass filter circuits of the receiver are connected to the ADC circuit. The FPGA core circuit is also connected to the receiving end frequency synthesis circuit and the transmitting end frequency synthesis circuit respectively.

[0052] The logic control module includes a human-machine interaction platform, an STM32 core circuit, an early warning circuit, and a power monitoring module. The STM32 core circuit is connected to the FPGA core circuit, the human-machine interaction platform, the early warning circuit, and the power monitoring module, respectively.

[0053] Example 2: Based on Example 1, this design adopts a two-stage filtering structure and adds a metal cover to improve the isolation between filters, thereby reducing crosstalk, avoiding signal overlap, optimizing system performance, and avoiding misjudgment of the target signal.

[0054] Example 3, based on Example 1, uses a circularly polarized ultrawide planar spiral antenna with an Archimedean spiral structure. The arm length of the Archimedean spiral structure is 1 / 4 of the wavelength corresponding to 3.6 GHz, with a radiation efficiency of ≥85% and an axial ratio of ≤3dB. It can provide circular polarization, reduce multipath effects and signal attenuation, and has high radiation efficiency.

[0055] Example 4, based on Example 1, uses the XILINX A7 series XC7A100T chip as the FPGA core circuit. The FPGA drives two ADCs to convert the demodulated signal into a digital signal. After Kalman filtering preprocessing, the polyphase encoded signal is decoded, effectively reducing noise while enhancing the second and third harmonic echo signals. The frequency domain characteristics of the harmonic signal are extracted using FFT, and the obtained spectrum is sent to the MCU via the FSMC bus. The MCU then controls the human-machine interface platform to display the spectrum on a visualization screen.

[0056] Example 5: Based on Example 1, the STM32 core circuit uses the STM32F767 chip with an ARM Cortex-M7 core as a bridge between the FPGA and the user. The detection results processed by the FPGA are displayed to the user through the human-computer interaction platform, and the user commands are received and parsed to control the working status of the entire system.

[0057] The logic control module also includes a FLASH circuit, the input of which is connected to the STM32 core circuit and is used to store system firmware and detection history data.

[0058] The human-computer interaction platform uses a 3.5-inch capacitive touchscreen and is developed based on the UCGUI graphical interface framework, providing an intuitive, user-friendly, and fully functional human-computer interaction process. Users transmit operation commands to the MCU via touch according to their actual application scenarios. The MCU parses the commands and transmits them to the FPGA through the FSMC bus to complete functions such as transmit power adjustment, carrier frequency adjustment, firmware encryption, and upgrades.

[0059] The above technical solutions give this design the following advantages:

[0060] 1. High-frequency detection capability: Utilizing 3.6GHz as the operating frequency improves the spatial resolution of the detector, enabling effective detection of microelectronic devices manufactured using processes below 7 nanometers. The system is highly integrated, modular, and portable.

[0061] 2. Anti-interference and accurate identification: Two independent VCOs are used to generate the local oscillator signals for modulation and demodulation respectively, enhancing signal quality and anti-interference capability. A built-in high-gain antenna provides a long detection range, with particularly high sensitivity to SIM card devices, ensuring rapid detection of espionage and mobile communication devices.

[0062] 3. High Sensitivity: Kalman filtering phase denoising improves signal quality and ensures accurate detection results. It achieves high receiving sensitivity (-136 to -140 dBm) for weak signals, increasing detection distance and range.

[0063] 4. Low false alarm rate: Combining harmonic energy analysis (second harmonic > third harmonic in PN junction, and vice versa for metal junction), it distinguishes between devices and equipment containing semiconductors, resulting in an extremely low false alarm rate. Built-in non-destructive testing algorithms significantly improve detection capabilities.

[0064] 5. Completely Independent Intellectual Property Rights: Possesses completely independent intellectual property rights, is not restricted by foreign technology imports, allows for rapid customization of features and optimization of algorithms, and offers extremely high security. Complies with electromagnetic radiation standards and features a built-in AES encrypted firmware upgrade mechanism to prevent misuse.

[0065] 6. Intelligent Adaptive Control: Features dynamic power adjustment, automatically increasing or decreasing power based on echo intensity to protect sensitive components and optimize detection range. Utilizes a dual-core architecture: FPGA processes real-time signals, while MCU manages human-machine interaction, enhancing response speed.

[0066] 7. Portability and Battery Life: Compact design, lightweight; ≥5 hours of battery life, supports field operations; simple and practical, providing a good user experience. A 3.5-inch touchscreen visually displays harmonic intensity and alarm prompts, with intuitive parameter adjustments.

[0067] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention.

[0068] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment have been appropriately combined to form other embodiments that are easy for those skilled in the art to understand.

Claims

1. A nonlinear node detector, characterized in that, It includes a radio frequency signal processing module, a baseband signal processing module, and a logic control module; The radio frequency signal processing module adopts a two-stage filtering structure and is connected to the baseband signal processing module. The baseband signal processing module is based on an FPGA, which is connected to the radio frequency signal processing module and the logic control module. The logic control module is based on an STM32 microcontroller and is connected to the baseband signal processing module via the FSMC bus.

2. The nonlinear node detector according to claim 1, characterized in that, The radio frequency signal processing module includes a radio frequency switching circuit, a transmitter, and a receiver. The transmitter includes two transmitting low-pass filter circuits, a transmitting frequency synthesis circuit, a transmitting quadrature modulation circuit, a radio frequency power amplifier circuit, a second low-pass filter circuit, and a transmitting antenna. The two transmitting low-pass filter circuits and the transmitting frequency synthesis circuit are both connected to the transmitting quadrature modulation circuit. The transmitting quadrature modulation circuit, the radio frequency power amplifier circuit, the second low-pass filter circuit, and the transmitting antenna are connected in sequence. The receiver includes a receiving antenna, a band-pass filter circuit, a receiving frequency synthesis circuit, a receiving quadrature modulation circuit, two radio frequency filter amplifier circuits, and two receiving low-pass filter circuits connected in sequence. The receiving antenna is connected to the receiving quadrature modulation circuit through the radio frequency switching circuit and the band-pass filter circuit. The receiving quadrature modulation circuit is connected to the receiving frequency synthesis circuit and the two radio frequency filter amplifier circuits, respectively. The two radio frequency filter amplifier circuits are connected to the two receiving low-pass filter circuits in sequence.

3. The nonlinear node detector according to claim 2, characterized in that, The baseband signal processing module includes an FPGA core circuit, an ADC circuit, and a DAC circuit. The FPGA core circuit is connected to the ADC circuit and the DAC circuit respectively. The DAC circuit is connected to the two transmitting end low-pass filter circuits of the transmitter. The two receiving end low-pass filter circuits of the receiver are connected to the ADC circuit. The FPGA core circuit is also connected to the receiving end frequency synthesis circuit and the transmitting end frequency synthesis circuit respectively.

4. The nonlinear node detector according to claim 3, characterized in that, The logic control module includes a human-machine interaction platform, an STM32 core circuit, an early warning circuit, and a power monitoring module. The STM32 core circuit is connected to the FPGA core circuit, the human-machine interaction platform, the early warning circuit, and the power monitoring module, respectively.

5. The nonlinear node detector according to claim 4, characterized in that, The passband of the bandpass filter circuit is 3.56GHz-3.64GHz, and the stopband rejection is ≥30dB.

6. The nonlinear node detector according to claim 5, characterized in that, The transmitting and receiving antennas are circularly polarized ultrawideband planar spiral antennas, employing an Archimedean spiral structure. The arm length of the Archimedean spiral structure is 1 / 4 of the wavelength corresponding to 3.6 GHz, with a radiation efficiency ≥85% and an axial ratio ≤3 dB.

7. The nonlinear node detector according to claim 6, characterized in that, The FPGA core circuit uses the XILINX A7 series XC7A100T chip. The signal output terminal of the FPGA core circuit is connected to the input terminal of the DAC circuit, and the signal input terminal of the FPGA core circuit is connected to the output terminal of the ADC circuit. The control terminal of the FPGA core circuit is connected to the STM32 core circuit of the logic control module through the FSMC bus, with a data transmission rate of ≥100Mbps.

8. The nonlinear node detector according to claim 7, characterized in that, The STM32 core circuit uses the STM32F767 chip with an ARM Cortex-M7 core.

9. The nonlinear node detector according to claim 8, characterized in that, The logic control module also includes a FLASH circuit, the input of which is connected to the STM32 core circuit and is used to store system firmware and historical detection data.

10. The nonlinear node detector according to claim 4, characterized in that, The human-computer interaction platform includes a 3.5-inch capacitive touch screen. The signal interface of the touch screen is connected to the STM32 core circuit of the logic control module for setting system operating parameters and displaying detection results. The resolution of the touch screen is ≥480×320 pixels.

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