Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the technical field of display, and aim to improve display quality. The display panel comprises a display area and a fan-out area. The fan-out area comprises at least a first wiring area and a second wiring area, and the first wiring area and the second wiring area are arranged along a first direction. The display panel further comprises a plurality of obstacles arranged on a first substrate and located in the second wiring area. In the second wiring area, a first data fan-out line and a second data fan-out line respectively bypass the plurality of obstacles, and the first data fan-out line is located on a side of the second data fan-out line away from the first substrate, and one first data fan-out line and one second data fan-out line are overlapped and insulated. In the second wiring area, a projection of the first data fan-out line on the first substrate and a projection of the second data fan-out line on the first substrate at least partially overlap, and along a second direction, a width of the first data fan-out line is greater than a width of the second data fan-out line.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous advancement of flat panel display technology, thin-film transistor liquid crystal displays (TFT-LCDs) have been successfully applied to various display devices. Under-mount integrated circuits (ICs) are advantageous for achieving narrow bezels in display panels and are relatively inexpensive, thus they are widely used in small-sized display panels.

[0003] Because there are obstacles inside the recessed IC, the data fan-out lines need to avoid these obstacles to prevent short circuits. In areas where obstacles are avoided, double-layer overlapping wiring is typically used. However, in double-layer overlapping wiring, because the upper data fan-out lines are raised, the upper data lines are easily etched during the formation of the upper data fan-out lines, resulting in open circuit defects and thus degrading display quality. Utility Model Content

[0004] This application discloses a display panel and display device, which aim to improve display quality.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0006] On one hand, a display panel is provided, comprising a display area and a fan-out area, wherein the fan-out area is located on one side of the display area along a first direction. The fan-out area includes at least a first wiring area and a second wiring area, which are arranged along the first direction. The display panel includes a first substrate, and a plurality of first data fan-out lines and a plurality of second data fan-out lines disposed on the first substrate, the first data fan-out lines and the second data fan-out lines extending from the first wiring area to the second wiring area. Along a second direction, the first data fan-out lines and the second data fan-out lines are alternately wired within the first wiring area. The second direction intersects the first direction and is parallel to the first substrate. The display panel also includes a plurality of obstacles disposed on the first substrate and located in the second wiring area, the plurality of obstacles being spaced apart along the second direction. Within the second wiring area, the first data fan-out lines and the second data fan-out lines respectively bypass the plurality of obstacles, and the first data fan-out lines are located on the side of the second data fan-out lines away from the first substrate, with one first data fan-out line overlapping and insulated from one second data fan-out line. Within the second wiring area, the orthographic projection of the first data fan-out line on the first substrate at least partially overlaps with the orthographic projection of the second data fan-out line on the first substrate, and along the second direction, the width of the first data fan-out line is greater than the width of the second data fan-out line.

[0007] In embodiments of this application, the display panel includes a display area and a fan-out area. The fan-out area includes at least a first wiring area and a second wiring area. The display panel also includes a first substrate, and a plurality of first data fan-out lines and a plurality of second data fan-out lines disposed on the first substrate, the first data fan-out lines and the second data fan-out lines extending from the first wiring area to the second wiring area. The first data fan-out lines and the second data fan-out lines are alternately wired within the first wiring area.

[0008] The display panel also includes multiple obstacles disposed on the first substrate and located in the second wiring area. Within the second wiring area, the first data fan-out line and the second data fan-out line bypass the multiple obstacles. Within the second wiring area, the first data fan-out line is located on the side of the second data fan-out line away from the first substrate, that is, the first data fan-out line is located above the second data fan-out line, and the first data fan-out line is raised. During the etching process to form the first data fan-out line, because the first data fan-out line is raised, the photoresist layer above the first data fan-out line is prone to peeling off, resulting in the first data fan-out line being mistakenly etched.

[0009] A first data fan-out line and a second data fan-out line overlap and are insulated from each other. That is, the first data fan-out line and the second data fan-out line use overlapping wiring in areas where multiple obstacles are avoided, reducing the wiring space and thus increasing the number of wires per unit area in the second area, which is beneficial to the narrow bezel of the display panel.

[0010] Furthermore, the orthographic projection of the first data fan-out line on the first substrate at least partially overlaps with the orthographic projection of the second data fan-out line on the first substrate, and the width of the first data fan-out line is greater than the width of the second data fan-out line. By compensating for the width of the raised first data fan-out line, the contact area between the photoresist layer and the first data fan-out line is increased, making it less likely for the photoresist layer above the first data fan-out line to detach. In addition, the increased width of the first data fan-out line makes it less likely to be accidentally etched and broken, thereby improving the open circuit defects of the first data fan-out line and thus improving the display quality of the display panel.

[0011] In some embodiments, within the second wiring area, the orthographic projection of the first data fan-out line on the first substrate overlaps the orthographic projection of the second data fan-out line on the first substrate, and along the second direction, at least one side boundary of the first data fan-out line extends beyond the corresponding boundary of the second data fan-out line.

[0012] In some embodiments, within the second wiring area, along the second direction, the opposite side boundaries of the first data fan-out line both extend beyond the corresponding boundaries of the second data fan-out line.

[0013] In some embodiments, within the second wiring area, the ratio of the width of the first data fan-out line to the width of the second data fan-out line ranges from 1.07 to 1.5.

[0014] In some embodiments, within the second wiring area, the difference between the width of the first data fan-out line and the width of the second data fan-out line ranges from 0.2 μm to 0.5 μm. The width of the second data fan-out line is greater than or equal to 3 μm.

[0015] In some embodiments, within the first wiring area, along the second direction, the spacing between the first data fan-out line and the second data fan-out line is 'a'. Within the second wiring area, along the second direction, the process alignment deviation between the first data fan-out line and the second data fan-out line is 'H', and the spacing between two adjacent first data fan-out lines is 'b', then b ≥ a + H.

[0016] In some embodiments, within the second wiring area, along the second direction, the spacing between two adjacent second data fan-out lines is c, then c≥a+H and c≥b.

[0017] In some embodiments, the display panel further includes a second substrate and a sealing adhesive layer, wherein the second substrate is disposed opposite to the first substrate, and the sealing adhesive layer is disposed between the first substrate and the second substrate. Furthermore, the sealing adhesive layer is located on the side of the first data fan-out line away from the first substrate, and a portion of the sealing adhesive layer is located in the second wiring area.

[0018] In some embodiments, the display panel further includes a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer sequentially stacked on a first substrate. A first data fan-out line is located on the second conductive layer. A second data fan-out line and obstacles are both located on the first conductive layer.

[0019] In some embodiments, the display panel further includes a third wiring area. The first wiring area, the second wiring area, and the third wiring area are arranged sequentially along a first direction and in a direction away from the display area. A first data fan-out line and a second data fan-out line extend from the first wiring area, through the second wiring area, to the third wiring area. Along a second direction, the first data fan-out line and the second data fan-out line are alternately routed within the third wiring area.

[0020] In some embodiments, the display panel further includes a plurality of pins disposed on the side of the third wiring area away from the first wiring area. The plurality of pins are arranged along a second direction, and a data fan-out line is electrically connected to one of the pins. Along the second direction, from one side of the display panel to the opposite side, the distance between the plurality of pins and the display area first decreases and then increases.

[0021] In some embodiments, along the first direction, the wiring space distance of the second wiring area is k, the size of the obstacle is L, and the ratio of k to L ranges from 4 to 16.7.

[0022] On the other hand, a display device is provided, which includes the display panel in any of the above embodiments and a controller electrically connected to the display panel.

[0023] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0025] Figure 1 A structural diagram of the display device provided in the embodiments of this application;

[0026] Figure 2 for Figure 1 A magnified view of a portion of the film layer of the display device at point M;

[0027] Figure 3 for Figure 2 A magnified view of a portion of the film layer on the display panel at point N;

[0028] Figure 4 for Figure 2 A magnified view of a portion of the film layer on the display panel at point P;

[0029] Figure 5 for Figure 3 A partial cross-sectional view of a portion of the film layer of the display panel along section line AA';

[0030] Figure 6 A partial cross-sectional view along section line AA' of a portion of the film layer of another display panel provided in this application;

[0031] Figure 7 A partial cross-sectional view along section line AA' of a portion of the film layer of another display panel provided in this application;

[0032] Figure 8 for Figure 4 A partial cross-sectional view of a portion of the film layer of the display panel along section line BB';

[0033] Figure 9 for Figure 3 A partial cross-sectional view of a portion of the film layer of the display panel along section line AA';

[0034] Figure 10 for Figure 3 A partial cross-sectional view of a portion of the film layer of the display panel along section line AA';

[0035] Figure 11 for Figure 4 A partial cross-sectional view of a portion of the film layer of the display panel along section line BB'. Detailed Implementation

[0036] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0037] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0039] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0040] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0041] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0042] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0043] With the continuous advancement of flat panel display technology, liquid crystal displays (LCDs) have been successfully applied to various display devices. Thin-film transistor liquid crystal displays (TFT-LCDs) are an important type of LCD. Under-display integrated circuits (ICs) refer to a design where, in the fanout area of ​​the display panel, the pins on both sides gradually sink down from the center line of the fanout area. This design is widely used in small-sized LCDs.

[0044] The data fan-out lines inside the sunken IC use double-layer alternating wiring. Because there are obstacles inside the sunken IC, the data fan-out lines need to avoid the obstacles to prevent short circuits. In the area where obstacles need to be avoided, double-layer alternating wiring will result in insufficient wiring space. Therefore, double-layer overlapping wiring is usually used in this area.

[0045] However, in double-layer overlapping wiring, the data fan-out lines on the upper layer are raised, which makes the photoresist above the upper data fan-out lines thinner during the formation process. This makes them easier to be blown away and lifted by high-pressure water and gas, allowing the etching solution to enter the metal layer. This can cause the upper data fan-out lines to be accidentally etched, resulting in open circuit defects and thus reducing display quality.

[0046] To address the aforementioned problems, embodiments of this application provide a display device, which can be a thin-film transistor liquid crystal display (TFT-LCD). Figure 1 This is a structural diagram of a display device provided in an embodiment of this application.

[0047] See Figure 1 The display device 100 includes a display panel 10 and a controller 20 electrically connected to the display panel 10. The controller 20 can be located on the non-display side of the display panel 10 and is used to control the display panel 10 to display images.

[0048] The aforementioned display device 100 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, aesthetic structures (e.g., displays of images of a piece of jewelry), laptops, and touch panel computers (TPCs), etc.

[0049] On the other hand, see Figure 1 This application also provides a display panel 10, which includes an active area (AA) 1 and a fan-out area 2, with the fan-out area 2 located on one side of the active area 1 along a first direction Y.

[0050] Figure 2 for Figure 1 A magnified view of a portion of the film layer of the display device at point M.

[0051] See Figure 2 The fan-out area 2 includes at least a first wiring area 21 and a second wiring area 22, which are arranged along a first direction Y. It is understood that the first wiring area 21 may be located on the side of the second wiring area 22 away from the display area 1, or the first wiring area 21 may be located on the side of the second wiring area 22 closer to the display area 1. The embodiments of this application are illustrated using the example where the first wiring area 21 may also be located on the side of the second wiring area 22 closer to the display area 1.

[0052] Figure 3 for Figure 2 A magnified view of a portion of the film layer on the display panel at point N.

[0053] See Figure 3 The display panel 10 also includes a first substrate 31, and a plurality of first data fan-out lines 4 and a plurality of second data fan-out lines 5 disposed on the first substrate 31. The first data fan-out lines 4 and the second data fan-out lines 5 extend from the first wiring area 21 to the second wiring area 22. For example, the first substrate 31 is a color filter substrate made of glass, the first data fan-out lines 4 can be gate lines, and the second data fan-out lines 5 can be data lines or touch signal lines.

[0054] Figure 4 for Figure 2 A magnified view of a portion of the film layer on the display panel at point P.

[0055] See Figure 4 Along the second direction X, the first data fan-out line 4 and the second data fan-out line 5 are alternately routed within the first wiring area 21. The second direction X intersects the first direction Y and is parallel to the first substrate 31. The embodiments of this application are described with the second direction X being perpendicular to the first direction Y as an example.

[0056] It is understandable that within the first wiring area 21, "alternating wiring" means that the orthographic projections of the first data fan-out line 4 and the second data fan-out line 5 on the first substrate 31 do not overlap. Along the Z direction, the heights of the first data fan-out line 4 and the second data fan-out line 5 in the alternating wiring are flush. During the etching process to form multiple data fan-out lines, the photoresist layer is not easily detached, and the first data fan-out line 4 is not easily etched incorrectly.

[0057] See also Figure 3 The display panel 10 also includes a plurality of obstacles 6 disposed on the first substrate 31 and located in the second wiring area 22, with the obstacles 6 spaced apart along the second direction X. Within the second wiring area 22, the first data fan-out line 4 and the second data fan-out line 5 respectively bypass the plurality of obstacles 6. It is understood that, in order to avoid the obstacles 6, at least some of the first data fan-out lines 4 and the second data fan-out lines 5 need to be bent, and the bending area requires a larger wiring space.

[0058] Figure 5 for Figure 3 A partial cross-sectional view of a portion of the film layer of the display panel along section line AA'.

[0059] See Figure 5 Within the second wiring area 22, the first data fan-out line 4 is located on the side of the second data fan-out line 5 away from the first substrate 31. One first data fan-out line 4 and one second data fan-out line 5 overlap and are insulated from each other. It can be understood that within the second wiring area 22, the first data fan-out line 4 and the second data fan-out line 5 are overlapped to reduce the wiring space.

[0060] The orthographic projection of the first data fan-out line 4 on the first substrate 31 at least partially overlaps with the orthographic projection of the second data fan-out line 5 on the first substrate 31. It is understood that the first data fan-out line 4 may cover a portion of the second data fan-out line 5, or the first data fan-out line 4 may cover the entire second data fan-out line 5. Figure 5 The diagram illustrates the situation by taking the portion of the first data fan-out line 4 that covers the second data fan-out line 5 as an example. Along the second direction X, the width d1 of the first data fan-out line 4 is greater than the width d2 of the second data fan-out line 5.

[0061] In embodiments of this application, the display panel includes a display area 1 and a fan-out area 2. The fan-out area 2 includes at least a first wiring area 21 and a second wiring area 22. The display panel 10 also includes a first substrate 31, and a plurality of first data fan-out lines 4 and a plurality of second data fan-out lines 5 disposed on the first substrate 31, the first data fan-out lines 4 and the second data fan-out lines 5 extending from the first wiring area 21 to the second wiring area 22. The first data fan-out lines 4 and the second data fan-out lines 5 are alternately wired within the first wiring area 21.

[0062] The display panel 10 also includes a plurality of obstacles 6 disposed on the first substrate 31 and located in the second wiring region 22. Within the second wiring region 22, the first data fan-out line 4 and the second data fan-out line 5 bypass the plurality of obstacles 6. Within the second wiring region 22, the first data fan-out line 4 is located on the side of the second data fan-out line 5 away from the first substrate 31, that is, the first data fan-out line 4 is located above the second data fan-out line 5, and the first data fan-out line 4 is raised. During the etching process to form the first data fan-out line 4, because the first data fan-out line 4 is raised, the photoresist layer above the first data fan-out line 4 is prone to peeling off, thereby causing the first data fan-out line 4 to be mistakenly etched.

[0063] A first data fan-out line 4 and a second data fan-out line 5 overlap and are insulated from each other. That is, the first data fan-out line 4 and the second data fan-out line 5 use overlapping wiring in the area where multiple obstacles 6 are avoided, which reduces the wiring space and increases the number of wirings per unit area in the second area 22, which is beneficial to the narrow bezel of the display panel 10.

[0064] Furthermore, the orthographic projection of the first data fan-out line 4 on the first substrate 31 at least partially overlaps with the orthographic projection of the second data fan-out line 5 on the first substrate 31, and the width d1 of the first data fan-out line 4 is greater than the width d2 of the second data fan-out line 5. By compensating for the width of the raised first data fan-out line 4, the contact area between the photoresist layer and the first data fan-out line 4 is increased, making it less likely for the photoresist layer above the first data fan-out line 4 to fall off. In addition, the increased width of the first data fan-out line 4 makes it less likely to be accidentally etched and broken, thereby improving the open circuit defect of the first data fan-out line 4 and thus improving the display quality of the display panel 10.

[0065] In some embodiments, see Figure 3Along the first direction Y, the wiring space distance of the second wiring area 22 is k, and the size of the obstacle 6 is L. The ratio of k to L ranges from 4 to 16.7. For example, the ratio of k to L can be 4, 7, 10, 13, or 16.7. For instance, the range of k can be 200μm to 500μm, and the second wiring area 22 occupies only 2% to 5% of the entire wiring space, which is relatively small. It is understood that the wiring space distance k of the second wiring area 22 is related to the size L of the obstacle 6. Within this range, if overlapping wiring is used, the wiring space is insufficient. In the embodiments of this application, double-layer overlapping wiring is used, which can meet the wiring requirements of multiple data fan-out lines in the second area 22.

[0066] In some embodiments, see Figure 3 The display panel also includes a third wiring area 23. Along the first direction Y and in a direction away from the display area 1, the first wiring area 21, the second wiring area 22, and the third wiring area 23 are arranged sequentially. The first data fan-out line 4 and the second data fan-out line 5 extend from the first wiring area 21 through the second wiring area 22 to the third wiring area 23. Along the second direction X, the first data fan-out line 4 and the second data fan-out line 5 are alternately wired within the third wiring area 23.

[0067] It is understandable that within the third wiring region 23, the orthographic projections of the first data fan-out line 4 and the second data fan-out line 5 on the first substrate 31 do not overlap. Along the Z direction, the heights of the alternating first data fan-out line 4 and the second data fan-out line 5 are flush, so during the etching process to form multiple data fan-out lines, the photoresist layer is not easily detached, and the first data fan-out line 4 is not easily etched incorrectly.

[0068] In some embodiments, see Figure 3 The display panel 10 also includes a plurality of pins 9, which are located on the side of the third wiring area 23 away from the first wiring area 21. The plurality of pins 9 are arranged along the second direction X, and a data fan-out line is electrically connected to one of the pins 9.

[0069] See Figures 1-3 Along the second direction X, from one side of the display panel 10 to the opposite side, the distance between the multiple pins 9 and the display area 1 first decreases and then increases. It can be understood that, with the center line S of the display panel 10 as a reference, the multiple pins 9 are symmetrically arranged, and along the second direction X, the distance between the pins 9 and the display area 1 gradually increases. The multiple pins 9 are recessed, which allows the starting segment of the wiring in the fan-out area 2 to be moved downwards, thereby saving wiring space and achieving a narrow bezel design for the display panel 10. For example, approximately 250 pins 9 are arranged on both sides of L.

[0070] Figure 6 A partial cross-sectional view along section line AA' of a portion of the film layer of another display panel provided in this application.

[0071] In some embodiments, see Figure 6 Within the second wiring area 22, the orthographic projection of the first data fan-out line 4 onto the first substrate 31 overlaps the orthographic projection of the second data fan-out line 5 onto the first substrate 31. Furthermore, along the second direction X, at least one boundary of the first data fan-out line 4 extends beyond the corresponding boundary of the second data fan-out line 5. This means that the left boundary of the first data fan-out line 4 extends beyond the left boundary of the second data fan-out line 5, or the right boundary of the first data fan-out line 4 extends beyond the right boundary of the second data fan-out line 5, or both opposite boundaries of the first data fan-out line 4 extend beyond the opposite boundaries of the second data fan-out line 5. Figure 6 The diagram shows a situation where the left boundary of the first data fan-out line 4 extends beyond the left boundary of the second data fan-out line 5, and the right boundary of the first data fan-out line 4 is flush with the right boundary of the second data fan-out line 5.

[0072] By setting the first data fan-out line 4 to cover the second data fan-out line 5, and at least one side boundary of the first data fan-out line 4 to extend beyond the corresponding boundary of the second data fan-out line 5, the total orthographic projection area of ​​the first data fan-out line 4 and the second data fan-out line 5 on the first substrate 31 is reduced, that is, the space required for wiring in the second region 22 is reduced, which is beneficial to achieving a narrow bezel of the display panel 10.

[0073] Figure 7 This application provides a partial cross-sectional view of a portion of the film layer of another display panel along section line AA'.

[0074] For example, see Figure 7 Within the second wiring area 22, along the second direction X, the relative side boundaries of the first data fan-out line 4 extend beyond the relative side boundaries of the second data fan-out line 5, further reducing the area of ​​the total orthographic projection of the first data fan-out line 4 and the second data fan-out line 5 on the first substrate 31, reducing the space required for wiring within the second area 22, and making it more conducive to achieving a narrow bezel for the display panel 10.

[0075] In some embodiments, see Figures 5-7 Within the second wiring area 22, the ratio of the width d1 of the first data fan-out line 4 to the width d2 of the second data fan-out line 5 ranges from 1.07 to 1.5. For example, the value of d1:d2 can be 1.07, 1.2, 1.3, 1.4, or 1.5.

[0076] In some embodiments, within the second wiring area 22, the difference between the width d1 of the first data fan-out line 4 and the width d2 of the second data fan-out line 5 ranges from 0.2 μm to 0.5 μm. For example, the difference between d1 and d2 can be 0.2 μm, 0.3 μm, 0.35 μm, 0.4 μm, or 0.5 μm. The width d2 of the second data fan-out line 5 is greater than or equal to 3 μm, i.e., d1 is greater than or equal to 3.2 μm. By compensating the width of the first data fan-out line 4 by 0.2 μm to 0.5 μm, the incidence of accidental etch-out of the first data fan-out line 4 can be minimized.

[0077] Figure 8 for Figure 4 A partial cross-sectional view of a portion of the film layer of the display panel along section line BB'.

[0078] In some embodiments, see Figure 8 Within the first wiring area 21, along the second direction X, the distance between the first data fan-out line 4 and the second data fan-out line 5 is 'a'. For example, along the second direction X, the distances between the opposite sides of the second data fan-out line 5 and the first data fan-out line 4 are a1 and a2, respectively. a1 and a2 can be equal or unequal; that is, the distance between the first data fan-out line 4 and the second data fan-out line 5 can be equal or unequal.

[0079] See Figures 5-7 Within the second wiring area 22, along the second direction X, the process alignment deviation between the first data fan-out line 4 and the second data fan-out line 5 is H. The spacing between two adjacent first data fan-out lines 4 is b, then b ≥ a + H. For example, if a ≥ 1.5 μm and H ≥ 1.9 μm, then b ≥ 3.4 μm.

[0080] It is understandable that, considering the process alignment deviation of the first data fan-out line 4 and the second data fan-out line 5, the spacing b of adjacent data fan-out lines in the second wiring area 22 with overlapping wiring is set with an additional process alignment deviation value H compared to the spacing a of adjacent data fan-out lines in the first area 21 with alternating wiring, thereby ensuring the product accuracy of the display panel 10.

[0081] In some embodiments, see Figures 5-7 Within the second wiring area 22, along the second direction X, if the spacing between two adjacent second data fan-out lines 5 is c, then c ≥ a + H and c ≥ b. For example, c ≥ 3.4 μm. It can be understood that the setting of the spacing c between two adjacent second data fan-out lines 5 within the second wiring area 22 not only considers process alignment deviations, but also, due to width compensation for the first data fan-out line 4, the width d1 of the first data fan-out line 4 is at least 0.1 μm larger than the width d2 of the second data fan-out line 5, therefore c ≥ b is also required.

[0082] Figure 9 for Figure 3 A partial cross-sectional view of a portion of the film layer of the display panel along section line AA'.

[0083] In some embodiments, see Figure 9 The display panel 10 also includes a second substrate 32 and a sealing adhesive layer 7. The second substrate 32 is disposed opposite to the first substrate 31. For example, the second substrate 32 is an array substrate. The sealing adhesive layer 7 is disposed between the first substrate 31 and the second substrate 32. Furthermore, the sealing adhesive layer 7 is located on the side of the first data fan-out line 4 away from the first substrate 31, and a portion of the sealing adhesive layer 7 is located in the second wiring area 22.

[0084] Within the second wiring area 22, the sealant needs to be photocured. As mentioned above, the wiring spacing (b and c) of the second wiring area 22 is set with a reserved process alignment deviation value H, so that light can pass through the transparent first substrate 31 and the reserved spacing to irradiate the sealant layer 7, thereby enabling the sealant layer 7 located in the second wiring area 22 to be photocured, increasing the firmness between the first substrate 31 and the second substrate 32, thereby improving the structural reliability of the display panel 10.

[0085] Figure 10 for Figure 3 A partial cross-sectional view of a portion of the film layer of the display panel along section line AA'; Figure 11 for Figure 4 A partial cross-sectional view of a portion of the film layer of the display panel along section line BB'.

[0086] In some embodiments, see Figure 10 and Figure 11 The display panel 10 further includes a first conductive layer M1, a first insulating layer 81, a second conductive layer M2, and a second insulating layer 82 sequentially stacked on a first substrate 31. A first data fan-out line 4 is located on the second conductive layer M2. A second data fan-out line 5 and an obstacle 6 are both located on the first conductive layer M1. For example, the first conductive layer M1 is a gate conductive layer, the first insulating layer 81 is a gate insulating layer, the second conductive layer M2 is a source / drain conductive layer, and the second insulating layer 82 is a passivation layer.

[0087] It is understandable that within the fan-out area 2, along the Z direction, the first data fan-out line 4 and the second data fan-out line 5 are on different layers. Regardless of whether alternating wiring or overlapping wiring is used, there will be no short circuit between the first data fan-out line 4 and the second data fan-out line 5. This allows the spacing between adjacent data fan-out lines to be set smaller, making the wiring in the fan-out area 2 compact, thereby saving wiring space and achieving a narrow bezel for the display panel 10.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, It includes a display area and a fan-out area, with the fan-out area located on one side of the display area along a first direction; the fan-out area includes at least a first wiring area and a second wiring area, which are arranged along the first direction; The display panel includes a first substrate, and a plurality of first data fan-out lines and a plurality of second data fan-out lines disposed on the first substrate, wherein the first data fan-out lines and the second data fan-out lines extend from the first wiring area to the second wiring area; Along the second direction, the first data fan-out line and the second data fan-out line are alternately routed within the first wiring area; the second direction intersects the first direction and is parallel to the first substrate; The display panel further includes a plurality of obstacles disposed on the first substrate and located in the second wiring area, the plurality of obstacles being spaced apart along the second direction; within the second wiring area, the first data fan-out line and the second data fan-out line respectively bypass the plurality of obstacles, and the first data fan-out line is located on the side of the second data fan-out line away from the first substrate, and a first data fan-out line and a second data fan-out line overlap and are insulated from each other; Within the second wiring area, the orthographic projection of the first data fan-out line onto the first substrate at least partially overlaps with the orthographic projection of the second data fan-out line onto the first substrate, and along the second direction, the width of the first data fan-out line is greater than the width of the second data fan-out line.

2. The display panel according to claim 1, characterized in that, Within the second wiring area, the orthographic projection of the first data fan-out line onto the first substrate covers the orthographic projection of the second data fan-out line onto the first substrate, and along the second direction, at least one side boundary of the first data fan-out line extends beyond the corresponding boundary of the second data fan-out line.

3. The display panel according to claim 2, characterized in that, Within the second wiring area, along the second direction, the relative boundaries of the first data fan-out line extend beyond the corresponding boundaries of the second data fan-out line on both sides.

4. The display panel according to any one of claims 1 to 3, characterized in that, Within the second wiring area, the ratio of the width of the first data fan-out line to the width of the second data fan-out line ranges from 1.07 to 1.

5.

5. The display panel according to claim 4, characterized in that, Within the second wiring area, the difference between the width of the first data fan-out line and the width of the second data fan-out line ranges from 0.2 μm to 0.5 μm. The width of the second data fan-out line is greater than or equal to 3μm.

6. The display panel according to claim 1, characterized in that, Within the first wiring area, along the second direction, the distance between the first data fan-out line and the second data fan-out line is a; Within the second wiring area, along the second direction, the process alignment deviation between the first data fan-out line and the second data fan-out line is H; the spacing between two adjacent first data fan-out lines is b, then b≥a+H.

7. The display panel according to claim 6, characterized in that, Within the second wiring area, along the second direction, the distance between two adjacent second data fan-out lines is c, then c≥a+H and c≥b.

8. The display panel according to claim 6 or 7, characterized in that, The display panel further includes a second substrate and a sealing adhesive layer, wherein the second substrate is disposed opposite to the first substrate, and the sealing adhesive layer is disposed between the first substrate and the second substrate; Furthermore, the sealing adhesive layer is located on the side of the first data fan-out line away from the first substrate, and a portion of the sealing adhesive layer is located in the second wiring area.

9. The display panel according to claim 1, characterized in that, The display panel further includes a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer that are sequentially stacked on the first substrate; The first data fan-out line is located in the second conductive layer; Both the second data fan-out line and the obstacle are located in the first conductive layer.

10. The display panel according to claim 1, characterized in that, The display panel further includes a third wiring area, and the first wiring area, the second wiring area and the third wiring area are arranged sequentially along the first direction and along the direction away from the display area; The first data fan-out line and the second data fan-out line extend from the first wiring area through the second wiring area to the third wiring area; Along the second direction, the first data fan-out line and the second data fan-out line are alternately routed within the third wiring area.

11. The display panel according to claim 10, characterized in that, The display panel also includes a plurality of pins, which are disposed on the side of the third wiring area away from the first wiring area. The plurality of pins are arranged along the second direction, and a data fan-out line is electrically connected to one pin. Along the second direction, from one side of the display panel to the opposite side, the distance between the plurality of pins and the display area first decreases and then increases.

12. The display panel according to claim 1, characterized in that, Along the first direction, the wiring space distance of the second wiring area is k, the size of the obstacle is L, and the ratio of k to L ranges from 4 to 16.

7.

13. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 12; The controller is electrically connected to the display panel.

Images