Semiconductor device and quantum operating semiconductor device
By forming a high-density qubit array using fin-based semiconductor manufacturing technology, the problems of low qubit density and long distance were solved, achieving high-efficiency quantum computing performance and CMOS integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2025-05-07
- Publication Date
- 2026-07-07
AI Technical Summary
Existing quantum computing systems suffer from low qubit density and large distances between qubits when manipulating qubit states, resulting in insufficient computing performance and difficulty in integrating with complementary metal-oxide-semiconductor integrated circuits.
By employing fin-based semiconductor manufacturing technology, a fin grid structure is formed, with qubits located at the intersection of the fin structure. The electron flow is controlled through the gate structure and source/drain regions, and the spin state of the qubits is modified by the plunger contacts to achieve a two-dimensional arrangement of high-density qubit arrays and efficient quantum computing.
It realizes a two-dimensional arrangement of high-density qubit arrays, shortens the distance between qubits, improves quantum computing performance, and supports integration with CMOS integrated circuits.
Smart Images
Figure CN224473655U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a quantum computing semiconductor device and a method for forming the same. Background Technology
[0002] Quantum computing involves computational systems that manipulate data using quantum mechanical phenomena. A quantum operation can involve initializing the states of N qubits, creating controlled entanglement among the N qubits to allow these states to evolve, and then reading out the states of the N qubits after the evolution. A qubit is a system with two degenerate (e.g., with equal energy) quantum states, where the probability of finding either state is non-zero. Therefore, N qubits can be defined with an initial state that is 2... N A combination of classic states. Utility Model Content
[0003] According to an embodiment of the present invention, a semiconductor device includes: a substrate; a fin grid extending over the substrate, the fin grid including: a first plurality of semiconductor fin structures extending in a first direction and arranged in a second direction; and a second plurality of semiconductor fin structures extending in the second direction and arranged in the first direction, wherein the first plurality of semiconductor fin structures intersect with the second plurality of semiconductor fin structures at a plurality of intersection points; a first plurality of gate structures located on the first plurality of semiconductor fin structures; and a second plurality of gate structures located on the second plurality of semiconductor fin structures.
[0004] According to an embodiment of the present invention, a method includes: forming a first plurality of semiconductor fin structures over a semiconductor substrate of a semiconductor device, wherein the first plurality of semiconductor fin structures extend in a first direction and are arranged in the semiconductor device in a second direction approximately perpendicular to the first direction; forming a second plurality of semiconductor fin structures over the semiconductor substrate, wherein the second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction; forming a first plurality of gate structures on the first plurality of semiconductor fin structures such that the first plurality of gate structures wrap around at least three sides of the first plurality of semiconductor fin structures; forming a second plurality of gate structures on the second plurality of semiconductor fin structures such that the second plurality of gate structures wrap around at least three sides of the second plurality of semiconductor fin structures; forming a first source / drain region at opposite ends of the first plurality of semiconductor fin structures; and forming a second source / drain region at opposite ends of the second plurality of semiconductor fin structures.
[0005] According to an embodiment of the present invention, a quantum computing semiconductor device includes: a substrate; a first plurality of semiconductor fin structures located above the substrate, wherein the first plurality of semiconductor fin structures extend in a first direction and are arranged in a second direction; a second plurality of semiconductor fin structures located above the substrate, wherein the second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction; a plurality of qubit regions located at the intersections between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures; a first plurality of barrier gate structures located on the first plurality of semiconductor fin structures; a second plurality of barrier gate structures located on the second plurality of semiconductor fin structures; and a plurality of plunger contacts located on the plurality of qubit regions. Attached Figure Description
[0006] When read in conjunction with the accompanying drawings, the aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of expression, the dimensions of the various components may be arbitrarily increased or decreased.
[0007] Figure 1A and Figure 1B This is a diagram of the example quantum computing semiconductor device described in this article.
[0008] Figures 2A to 2L This is a diagram of an example of a quantum computing semiconductor device described in this article.
[0009] Figure 3 This is a flowchart of an example process associated with forming the quantum computing semiconductor device described herein. Detailed Implementation
[0010] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first component above or on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which an additional component may be formed between the first and second components so that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0011] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” and the like are used herein to describe the relationship between one element or component and another element or component as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those depicted in the figures. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.
[0012] Quantum computing semiconductor devices can contain multiple qubits implemented in a semiconductor-based structure. For example, multiple qubits can be arranged in a linear array along an active semiconductor region. Adjacent qubits are electrically separated by barrier gates, and a plunger contact coupled to each qubit can be used to control the quantum state of the qubit. Electrons can be provided from the source side of the active semiconductor region and trapped in qubits between adjacent barrier gates, and the spin of the electrons can be modified by spin polarization. The direction of the electron spin can correspond to the quantum operation associated with the qubit. The spin states of the qubits along the linear array become entangled and accumulate at the accumulation side of the active semiconductor region.
[0013] In some embodiments described herein, qubits in a quantum computing semiconductor device are arranged in a two-dimensional array. The two-dimensional array can be implemented using fin-based semiconductor fabrication techniques. For example, a first active semiconductor region (e.g., a first fin structure) may extend in a first direction, and a second active semiconductor region (e.g., a second fin structure) may extend in a second direction. Qubits may be positioned at the intersection between the first and second active semiconductor regions. This allows qubits to be formed in a lattice within the two-dimensional array, providing a greater qubit density and shorter distances between qubits (and therefore greater quantum computing performance) compared to a one-dimensional (e.g., linear) qubit array. Furthermore, implementing qubits using fin-based semiconductor fabrication techniques enables the quantum computing array to be integrated with other complementary metal-oxide-semiconductor (CMOS) integrated circuits on the same semiconductor device.
[0014] Figure 1A and Figure 1B This is a diagram of the example quantum computing semiconductor device 100 described in this article. Figure 1A and Figure 1B A perspective view illustrating the quantum computing semiconductor device 100.
[0015] like Figure 1A As shown, the quantum computing semiconductor device 100 includes a substrate 102 and a fin grid 104 extending above the substrate 102. The substrate 102 may include a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or another type of semiconductor substrate from which the fin grid 104 may be formed.
[0016] The fin grid 104 includes a first plurality of fin structures 104a and a second plurality of fin structures 104b. Figure 1B The diagram illustrates an unobstructed view of a fin grid 104 including fin structures 104a and 104b. The fin structures 104a and 104b of the fin grid 104 may correspond to the active region of the quantum computing array of the quantum computing semiconductor device 100.
[0017] The fin structures 104a and 104b of the fin grid 104 may be formed from the substrate 102, such that the fin structures 104a and 104b of the fin grid 104 comprise the same semiconductor material (or semiconductor material composition) as the substrate 102. Alternatively and additionally, the fin structures 104a and 104b of the fin grid 104 may comprise one or more doped semiconductor materials. For example, the fin structures 104a and 104b of the fin grid 104 may comprise silicon (Si) and / or another semiconductor material doped with one or more n-type dopants and / or one or more p-type dopants. Examples of these p-type dopants include boron (B) or germanium (Ge) and other examples. Examples of these n-type dopants include phosphorus (P) or arsenic (As) and other examples.
[0018] The fin structure 104a extends in a first direction (e.g., the x-direction) and is arranged in a second direction (e.g., the y-direction) in the quantum computing semiconductor device 100. The fin structure 104a extends over the substrate 102 in a third direction (e.g., the z-direction) in the quantum computing semiconductor device 100.
[0019] The fin structure 104b extends in a second direction (e.g., the y-direction) in the quantum computing semiconductor device 100 and is arranged in a first direction (e.g., the x-direction) in the quantum computing semiconductor device 100. The fin structure 104b extends over the substrate 102 in a third direction (e.g., the z-direction) in the quantum computing semiconductor device 100.
[0020] Each fin structure 104a may intersect with each of the fin structures 104b, and each fin structure 104b may intersect with the fin structure 104a to form a fin grid 104. The intersection points between the fin structures 104a and fin structures 104b in the fin grid 104 correspond to the qubit regions of the quantum computing array of the quantum computing semiconductor device 100. Forming qubit regions at the intersection points in the fin grid 104 enables the qubit regions to be arranged in a two-dimensional array in the quantum computing array, wherein the qubit regions are arranged in a first column in a first direction (e.g., the x-direction) and in a second column in a second direction (e.g., the y-direction).
[0021] The qubit region at the intersection between fin structures 104a and fin structures 104b in the fin grid 104 can be configured to trap one or more electrons, such that one or more properties of the electrons (e.g., the electron's spin) can be manipulated or modified to perform quantum operations in a quantum computing array. A first plurality of source / drain regions 106a can be located at the ends of fin structures 104a, and a second plurality of source / drain regions 106b can be located at the ends of fin structures 104b. The source / drain regions 106a can be configured to provide an electron flow through fin structures 104a to the qubit region at the intersection between fin structures 104a and fin structures 104b. The source / drain regions 106b can be configured to provide an electron flow through fin structures 104b to the qubit region at the intersection between fin structures 104a and fin structures 104b.
[0022] Depending on the context, "source / drain region" refers to a source region, a drain region, or both. In some embodiments, a source / drain region 106a located at a first end of fin structure 104a provides electrons to the source region of fin structure 104a, and a source / drain region 106a located at a second end of fin structure 104a opposite to the first end is a drain region or accumulation region for measuring electrons trapped in the qubit region. Similarly, a source / drain region 106b located at a first end of fin structure 104b provides electrons to the source region of fin structure 104b, and a source / drain region 106b located at a second end of fin structure 104b opposite to the first end is a drain region or accumulation region for measuring electrons trapped in the qubit region.
[0023] Source / drain regions 106a and 106b may each comprise a semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), and / or another type of semiconductor material. In some embodiments, source / drain regions 106a and / or 106b each comprise one or more doped semiconductor materials. For example, source / drain regions 106a and / or 106b may each comprise silicon (Si) and / or another semiconductor material doped with one or more n-type dopants and / or one or more p-type dopants. Examples of these p-type dopants include boron (B) or germanium (Ge) and other examples. Examples of these n-type dopants include phosphorus (P) or arsenic (As) and other examples. In some embodiments, source / drain regions 106a and / or 106b comprise a conductive material, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti) and other examples.
[0024] like Figure 1AThe diagram further illustrates that a first plurality of gate structures 108a are included on a fin structure 104a, and a second plurality of gate structures 108b are included on a fin structure 104b. Each gate structure 108a is wound around at least three sides of the fin structure 104a, and each gate structure 108b is wound around at least three sides of the fin structure 104b.
[0025] Each group of two or more gate structures 108a is included on each of the fin structures 104a. For example, a first group of gate structures 108a is included on a first fin structure 104a-1, a second group of gate structures 108a is included on a second fin structure 104a-n, and so on. One or more of the gate structures 108a formed on the fin structure 104a-1 may be located between a first intersection 116 between the fin structure 104a and the first fin structure 104b-1 and a second intersection 116 between the fin structure 104a-1 and the second fin structure 104b-2. In other words, one or more of the gate structures 108a formed on the fin structure 104a may be located between adjacent intersections 116 between the fin structure 104a and the two fin structures 104b. In some embodiments, one or more of the gate structures 108a formed on the fin structure 104a are positioned between the intersection 116 and the end of the fin structure 104a.
[0026] The gate structure 108b can be formed such that each of the plurality of gate structures 108b is formed on its respective fin structure 104b. For example, a first set of gate structures 108b can be formed on a first fin structure 104b, a second set of gate structures 108b can be formed on a second fin structure 104b, and so on. One or more of the gate structures 108b formed on the fin structure 104b can be positioned between a first intersection 116 between the fin structure 104b and the first fin structure 104a and a second intersection 116 between the fin structure 104b and the second fin structure 104a. In other words, one or more of the gate structures 108b formed on the fin structure 104b can be positioned between adjacent intersections 116 between the fin structure 104b and two fin structures 104a. In some embodiments, one or more of the gate structures 108b formed on the fin structure 104b are positioned between the intersection 116 and the end of the fin structure 104b.
[0027] Gate structures 108a and 108b located between two or more intersections in the fin grid 104 may be referred to as barrier gate structures 108c. For example, gate structure 108a located between two or more intersections in the fin grid 104 may be referred to as barrier gate structures 108a / 108c. As another example, gate structure 108b located between two or more intersections in the fin grid 104 may be referred to as barrier gate structures 108b / 108c. Barrier gate structure 108c may be included to control the electron flow between intersections, thereby enabling electrons to be trapped in the qubit regions at the intersections. Gate structure 108a located between an intersection and a source / drain region 106a and gate structure 108b located between an intersection and a source / drain region 106b may be referred to as accumulation gate 108d. For example, the gate structure 108a located between the intersection and the source / drain region 106a can be referred to as the accumulator gate structure 108a / 108d. As another example, the gate structure 108b located between the intersection and the source / drain region 106b can be referred to as the barrier gate structure 108b / 108d. The accumulator gate 108d enables the qubit region to be selectively measured or sampled at the source / drain regions 106a and / or 106b.
[0028] In some embodiments, gate structures 108a and 108b each comprise polysilicon material doped with one or more types of dopants. For example, gate structures 108a and / or 108b may each comprise polysilicon doped with one or more p-type dopants. Examples of these p-type dopants include boron (B) or germanium (Ge) and others. As another example, gate structures 108a and / or 108b may each comprise polysilicon doped with one or more n-type dopants. Examples of these n-type dopants include phosphorus (P) or arsenic (As) and others. In some embodiments, gate structure 108a each comprises polysilicon doped with one or more p-type dopants, and gate structure 108b each comprises polysilicon doped with one or more n-type dopants. In some embodiments, gate structure 108a each comprises polysilicon doped with one or more n-type dopants, and gate structure 108b each comprises polysilicon doped with one or more p-type dopants. In some implementations, gate structure 108a and gate structure 108b each comprise polysilicon doped with the same type of dopant.
[0029] Additionally and / or alternatively, gate structures 108a and / or 108b may each comprise a metal gate structure comprising one or more metal-containing materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), and / or aluminum (Al), and other examples. In these embodiments, gate structures 108a and / or 108b may each comprise one or more work function metals for tuning the work function of gate structures 108a and / or 108b.
[0030] like Figure 1A Further demonstrating, the source / drain contact 110a may be included on and electrically coupled to the source / drain region 106a. Similarly, the source / drain contact 110b may be included on and electrically coupled to the source / drain region 106b. The source / drain contacts 110a and 110b may each comprise one or more metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), copper (Cu), titanium nitride (TiN), and / or aluminum (Al), and other examples. In some embodiments, for example, titanium silicide (TiSi) x A metal silicide layer may be included between the source / drain region 106a and the source / drain contact 110a to achieve low contact resistance between the source / drain region 106a and the source / drain contact 110a. In some embodiments, for example, titanium silicide (TiSi) x The metal silicide layer may be included between the source / drain region 106b and the source / drain contact 110b so that low contact resistance can be achieved between the source / drain region 106b and the source / drain contact 110b.
[0031] Gate contact 112a may be included on and electrically coupled to gate structure 108a. Gate structure 108a can be electrically operated via gate contact 112a. Similarly, gate contact 112b may be included on and electrically coupled to gate structure 108b. Gate structure 108b can be electrically operated via gate contact 112b. Gate contacts 112a and 112b may each comprise one or more metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), copper (Cu), titanium nitride (TiN), and / or aluminum (Al), and other examples.
[0032] A plunger contact 114 may be included on and electrically coupled to the intersection 116 of the fin grid 104. The plunger contact 114 can be used to modify one or more properties of electrons trapped in the qubit region at the intersection 116. For example, the plunger contact 114 can be used to modify the quantum state of electrons trapped in the qubit region at the intersection 116 above the plunger contact 114. A voltage bias can be applied to the plunger contact 114 to modify or select the difference in energy levels associated with different spin orientations of the electrons trapped in the qubit region. In this way, quantum computation operations can be performed in the quantum computing array of the quantum computing semiconductor device 100 by modifying (e.g., alternating) the magnetic field at the intersection 116 to rotate the spin of the electrons trapped in the qubit region. Each plunger contact 114 may comprise one or more metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), platinum (Pt), copper (Cu), titanium nitride (TiN), and / or aluminum (Al), as well as other examples.
[0033] Figure 1B The diagram illustrates a finned grid 104 with source / drain contacts 110a and 110b, and gate contacts 112a and 112b. For clarity, plunger contact 114 is omitted. Figure 1B As shown, each fin structure 104a intersects with one or more fin structures 104b at intersection 116, and each fin structure 104b intersects with one or more fin structures 104a at intersection 116. The intersection 116 of the fin grid 104 may correspond to the position of the qubit region of the quantum computing array of the quantum computing semiconductor device 100. A plunger contact 114 is positioned above the intersection 116 to control one or more properties of the qubit region, such as the difference in quantum states associated with the spin of electrons trapped in the qubit region.
[0034] like Figure 1B The diagram further illustrates that each pair of source / drain regions 106a can be located at opposite ends of fin structures 104a, including fin structures 104a-1 to fin structures 104a-n. For example, the first pair of source / drain regions 106a can be located at opposite ends of fin structure 104a-1, the second pair of source / drain regions 106a can be located at opposite ends of fin structure 104a-2, the third pair of source / drain regions 106a can be located at opposite ends of fin structure 104a-3, and so on.
[0035] Similarly, each pair of source / drain regions 106b can be located at opposite ends of fin structures 104b, including fin structures 104b-1 to fin structures 104a-m. For example, the first pair of source / drain regions 106b can be located at opposite ends of fin structures 104b-1, the second pair of source / drain regions 106b can be located at opposite ends of fin structures 104b-2, the third pair of source / drain regions 106b can be located at opposite ends of fin structures 104b-3, and so on.
[0036] The electron flow to and / or from the qubit region at the intersection 116 of the fin grid 104 can be controlled using gate structures 108a and / or 108b. Each gate structure 108a of at least a subset of the gate structures 108a is positioned in the x-direction between adjacent pairs (e.g., adjacent pairs of qubit regions) at the intersection 116. Each gate structure 108b of at least a subset of the gate structures 108b is positioned in the y-direction between adjacent pairs (e.g., adjacent pairs of qubit regions) at the intersection 116.
[0037] For example, gate structure 108a can be positioned between a first intersection 116 between fin structures 104a-1 and fin structure 104b-1 and a second intersection 116 between fin structures 104a-1 and fin structure 104b-2; another gate structure 108a can be positioned between a first intersection 116 between fin structures 104a-1 and fin structure 104b-2 and a second intersection 116 between fin structures 104a-1 and fin structure 104b-3; and so on. Similarly, the same applies to other fin structures 104a-2 to 104a-n. Gate structure 108a on fin structure 104a-1 can control the electron flow to and / or from the qubit region at the intersection 116 between fin structures 104a-1 and fin structures 104b-1 to 104b-m. Similarly, the same applies to other fin structures 104a-2 to 104a-n. Furthermore, the gate structure 108a, located between the source / drain region 106a at the end of fin structure 104a-1 and the intersection 116 of fin structure 104a-1 and fin structure 104b-m, can be configured to control the electron flow to the source / drain region 106a at the end of fin structure 104-a. Similarly, the same applies to the other fin structures 104a-2 to 104a-n.
[0038] like Figure 1BFurther demonstrating, a gate structure 108b can be positioned between a first intersection 116 between fin structures 104b-1 and fin structure 104a-1 and a second intersection 116 between fin structures 104b-1 and fin structures 104a-n; another gate structure 108b can be positioned between a first intersection 116 between fin structures 104b-2 and fin structure 104a-1 and a second intersection 116 between fin structures 104b-2 and fin structures 104a-n; and so on. The gate structure 108b on fin structure 104b-1 can control the electron flow to and / or from the qubit region at the intersection 116 between fin structures 104b-1 and fin structures 104a-1 to 104a-n. Similarly, the other fin structures 104b-2 to 104b-m are also such that. Furthermore, the gate structure 108a, located between the source / drain region 106b at the end of fin structure 104b-1 and the intersection 116 of fin structure 104b-1 and fin structures 104a-n, can be configured to control the electron flow to the source / drain region 106b at the end of fin structure 104b-1. Similarly, the same applies to the other fin structures 104b-2 to 104b-m.
[0039] As indicated above, Figure 1A and Figure 1B Provided as an example. Other examples may differ from those provided. Figure 1A and Figure 1B Examples described.
[0040] Figures 2A to 2L This is a diagram of an example 200 forming the quantum computing semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing tools may be used to perform the combination. Figures 2A to 2L One or more of the semiconductor processing operations described, such as deposition tools, exposure tools, developer tools, etching tools, ion implantation tools and / or wafer / die transport tools, and other examples.
[0041] Go to Figure 2A A substrate 102 may be provided. The substrate 102 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, a semiconductor die, and / or another type of substrate on which a semiconductor device may be formed.
[0042] like Figure 2A The diagram further demonstrates that a patterned stack can be formed on substrate 102. The patterned stack may include multiple mask layers, including mask layer 202 on substrate 102 and mask layer 204 on mask layer 202. In some embodiments, mask layer 202 and mask layer 204 are formed of different materials so that mask layer 202 and mask layer 204 can be patterned independently of each other. For example, mask layer 202 may include a silicon oxide material (e.g., SiO2). xThe mask layer 204 may contain silicon nitride material (e.g., SiO2), and the mask layer 204 may contain silicon nitride material (e.g., SiO2). x N y (e.g., Si3N4). This enables the etching of mask layer 204, while mask layer 202 serves as an etch stop layer for mask layer 204.
[0043] Deposition tools can be used to deposit each of mask layer 202 and mask layer 204 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or another suitable deposition technique. In some embodiments, a chemical mechanical planarization (CMP) operation or another type of planarization is performed using planarization tools to planarize mask layer 202 and / or mask layer 204 after deposition.
[0044] like Figure 2B As shown, a first pattern 206 can be formed in a mask layer 204. The first pattern 206 may include a plurality of mandrels 208. The mandrels 208 include elongated dielectric fins extending in the y-direction within the quantum computing semiconductor device 100. In some embodiments, the mask layer 204 is etched using a pattern in a photoresist layer to form the first pattern 206 in the mask layer 204. In these embodiments, a deposition tool can be used to form a photoresist layer on the mask layer 204 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the mask layer 204 based on the pattern to form the first pattern 206 in the mask layer 204. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).
[0045] like Figure 2C As shown, a second pattern 210 can be formed in mask layer 202. The second pattern 210 can be formed using the first pattern 206 in mask layer 204 to etch mask layer 202. The second pattern 210 includes a first plurality of mandrels 210a extending in the x-direction and a second plurality of mandrels 210b extending in the y-direction of quantum computing semiconductor device 100. In other words, the first plurality of mandrels 210a extend in the first direction in quantum computing semiconductor device 100, and the second plurality of mandrels 210b extend in the second direction in quantum computing semiconductor device 100, wherein the second direction is approximately perpendicular to the first direction.
[0046] A dual patterning technique can be used to form the second pattern 210. For example, a first plurality of mandrels 210a can be formed using a photolithographic patterning technique similar to that used for the mandrels 208 in the first pattern 206, and a second plurality of mandrels 210b can be formed based on the mandrels 208 in the first pattern 206. To form the first plurality of mandrels, a mask layer 202 is etched using a pattern in a photoresist layer. In these embodiments, a deposition tool can be used to form a photoresist layer on the mask layer 202 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern.
[0047] Next, the mask layer 202 can be etched (e.g., using an etching tool) based on the pattern in the photoresist layer and on the mandrel 208 of the first pattern 206 to form the second pattern 210. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, the mandrel 208 of the first pattern 206 is removed by etching, by CMP, and / or by another suitable technique.
[0048] like Figure 2D As shown, a fin grid 104 can be formed in a substrate 102 using a second pattern 210 in mask layer 202. For example, the substrate 102 can be etched based on the second pattern 210 in mask layer 202 (e.g., using an etching tool). In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. Etching the substrate 102 based on the second pattern 210 includes etching the substrate 102 based on a first plurality of mandrels 210a to form a fin structure 104a in the substrate 102, and etching the substrate 102 based on a second plurality of mandrels 210b to form a fin structure 104b in the substrate 102. Fin structures 104a and 104b are formed in the substrate 102 such that fin structure 104a extends in a first direction (e.g., the x direction) in the quantum computing semiconductor device 100, and fin structure 104b extends in a cross-sectional direction (e.g., the y direction) in the quantum computing semiconductor device 100, wherein the first direction and the second direction are approximately perpendicular.
[0049] like Figure 2EAs shown, a gate electrode layer 212 is formed over a substrate 102 and over a fin gate 104. In some embodiments, a shallow trench isolation (STI) region may be formed around the fin gate 104 prior to the formation of the gate electrode layer 212. The STI region is formed by depositing an STI layer, planarizing the STI layer, and then etching the STI layer to form the STI region. In some embodiments, the remaining portions of the first pattern 206 and / or the remaining portions of the second pattern 210 may be removed during the planarization of the STI layer.
[0050] Figure 2F Explanation along Figure 2E A cross-sectional view of the gate electrode layer 212 of line AA. (See diagram below.) Figure 2F As shown, a gate dielectric layer 214 can be formed on a fin grid 104 (including fin structures 104a and 104b), and a gate electrode layer 212 can be formed on the gate dielectric layer 214 above the fin grid 104. The gate dielectric layer 214 can be conformally deposited using CVD, ALD, and / or another suitable deposition technique. The gate electrode layer 212 can be deposited using a blanket deposition technique using CVD, PVD, and / or another suitable deposition technique.
[0051] The gate electrode layer 212 may comprise a polysilicon material, a polysilicon material doped with one or more types of dopants (e.g., p-type dopants, n-type dopants), a metal-containing material (e.g., tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum (Al)), and / or another suitable gate electrode material. The gate dielectric layer 214 may comprise one or more dielectric materials. For example, the gate dielectric layer 214 may comprise a silicon oxide material (e.g., SiO₂). x For example, SiO2). As another example, the gate dielectric layer 214 may comprise a high dielectric constant (high k) dielectric material, such as silicon nitride (e.g., SiO2). x N y (e.g., Si3N4), hafnium oxide materials (e.g., HfO) x For example, HfO2) and / or alumina materials (Al) x O y (e.g., Al2O3) and other examples.
[0052] like Figure 2GAs shown, a gate electrode layer 212 and a gate dielectric layer 214 can be etched to form a gate structure 108a on a fin structure 104a and a gate structure 108b on a fin structure 104b. Each gate structure 108a can be wound around at least three sides of the fin structure 104a, and each gate structure 108b can be wound around at least three sides of the fin structure 104b. The gate dielectric layer 214 (not shown for clarity) may be included between the gate structure 108a and the fin structure 104a and between the gate structure 108b and the fin structure 104b.
[0053] In some embodiments, a pattern in the photoresist layer is used to etch the gate electrode layer 212 to form gate structures 108a and 108b. In these embodiments, a deposition tool can be used to form the photoresist layer on the gate electrode layer 212 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the gate electrode layer 212 based on the pattern to form gate structures 108a and 108b. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming gate structures 108a and 108b from the gate electrode layer 212.
[0054] Gate structures 108a can be formed such that each of a plurality of gate structures 108a is formed on its respective fin structure 104a. For example, a first set of gate structures 108a can be formed on a first fin structure 104a, a second set of gate structures 108a can be formed on a second fin structure 104a, and so on. One or more of the gate structures 108a formed on the fin structure 104a can be positioned between a first intersection 116 between the fin structure 104a and the first fin structure 104b and a second intersection 116 between the fin structure 104a and the second fin structure 104b. In other words, one or more of the gate structures 108a formed on the fin structure 104a can be positioned between adjacent intersections 116 between the fin structure 104a and two fin structures 104b. In some embodiments, one or more of the gate structures 108a formed on the fin structure 104a are positioned between the intersection 116 and the end of the fin structure 104a.
[0055] The gate structure 108b can be formed such that each of the plurality of gate structures 108b is formed on its respective fin structure 104b. For example, the first set of gate structures 108b can be formed on the first fin structure 104b, the second set of gate structures 108b can be formed on the second fin structure 104b, and so on. One or more of the gate structures 108b formed on the fin structure 104b can be positioned between a first intersection 116 between the fin structure 104b and the first fin structure 104a and a second intersection 116 between the fin structure 104b and the second fin structure 104a. In other words, one or more of the gate structures 108b formed on the fin structure 104b can be positioned between adjacent intersections 116 between the fin structure 104b and two fin structures 104a. In some embodiments, one or more of the gate structures 108b formed on the fin structure 104b are positioned between the intersection 116 and the end of the fin structure 104b.
[0056] like Figure 2H As shown, source / drain regions 106a are formed at the ends of fin structure 104a, and source / drain regions 106b are formed at the ends of fin structure 104b. Deposition tools can be used to form source / drain regions 106a and 106b during epitaxial growth operations, wherein an epitaxial material layer is deposited such that the layer is formed with a specific crystal orientation. Alternatively and / or CVD techniques and / or another suitable deposition technique can be used to form source / drain regions 106a and 106b. In some embodiments, source / drain regions 106a and / or 106b are doped with p-type dopant (e.g., a type of dopant containing electron acceptor atoms that generate holes in the material), n-type dopant (e.g., a type of dopant containing electron donor atoms that generate mobile electrons in the material), and / or another type of dopant. The material can be doped by adding impurities (e.g., p-type dopant, n-type dopant) to the source gas used during epitaxial growth operations. Examples of p-type dopants that can be used in epitaxial operations include boron (B) or germanium (Ge), and others. Examples of n-type dopants that can be used in epitaxial operations include phosphorus (P) or arsenic (As), and others.
[0057] In some embodiments, a source / drain region 106a is formed adjacent to the end of the fin structure 104a, such that the source / drain region 106a is formed on the substrate 102 and / or on the STI region surrounding the fin structure 104a. In some embodiments, the source / drain region 106a is formed on the end of the fin structure 104a. For example, the end of the fin structure 104a may be etched (e.g., using an etching tool) to form a source / drain groove in the end of the fin structure 104a, and the source / drain region 106a may be formed in the source / drain groove on the end of the fin structure 104a.
[0058] In some embodiments, a source / drain region 106b is formed adjacent to the end of the fin structure 104b, such that the source / drain region 106b is formed on the substrate 102 and / or on the STI region surrounding the fin structure 104b. In some embodiments, the source / drain region 106b is formed on the end of the fin structure 104b. For example, the end of the fin structure 104b may be etched to form a source / drain groove in the end of the fin structure 104b, and the source / drain region 106b may be formed in the source / drain groove on the end of the fin structure 104b.
[0059] Source / drain regions 106a are formed such that a pair of source / drain regions 106a are positioned at opposite ends of the fin structure 104a. The source / drain region 106a positioned at the first end of the fin structure 104a corresponds to the input region of the quantum computing array of the quantum computing semiconductor device 100, and the source / drain region 106a positioned at the second end of the fin structure 104a opposite to the first end corresponds to the accumulation region of the quantum computing array of the quantum computing semiconductor device 100. A source / drain region 106a (e.g., an input region) located at a first end of the fin structure 104a may be configured to provide electrons to a qubit region located at an intersection 116 along the fin structure 104a, and a source / drain region 106a (e.g., an accumulation region) located at a second end of the fin structure 104a may be configured to measure or sample the charge (and associated spin) of the qubit region located at the intersection 116 along the fin structure 104a.
[0060] Source / drain regions 106b are formed such that a pair of source / drain regions 106b are positioned at opposite ends of the fin structure 104b. The source / drain regions 106b positioned at the first end of the fin structure 104b correspond to the input region of the quantum computing array of the quantum computing semiconductor device 100, and the source / drain regions 106b positioned at the second end of the fin structure 104b opposite to the first end correspond to the accumulation region of the quantum computing array of the quantum computing semiconductor device 100. A source / drain region 106b (e.g., an input region) located at a first end of the fin structure 104b may be configured to provide electrons to a qubit region located at an intersection 116 along the fin structure 104b, and a source / drain region 106b (e.g., an accumulation region) located at a second end of the fin structure 104b may be configured to measure or sample the charge (and associated spin) of the qubit region located at the intersection 116 along the fin structure 104b.
[0061] like Figure 2IAs shown, an interlayer dielectric (ILD) layer 216 can be formed above the fin grid 104, above the source / drain regions 106a and 106b, and / or above the gate structures 108a and 108b. The ILD layer 216 may comprise one or more dielectric material layers, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y The materials used may be silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), silicon carbide (SiCN), and / or another suitable dielectric material. In some embodiments, an etch stop layer (ESL) is formed prior to the formation of the ILD layer 216. Deposition tools may be used to deposit the ILD layer 216 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The ILD layer 216 may be deposited in one or more deposition operations. In some embodiments, planarization tools may be used to planarize the ILD layer 216 after deposition.
[0062] like Figure 2J As shown, a source / drain contact 110a can be formed on the source / drain region 106a, and a source / drain contact 110b can be formed on the source / drain region 106b. The source / drain contacts 110a and 110b can be formed in a groove in the ILD layer 216 (for clarity). Figure 2J (Not shown in the text).
[0063] In some embodiments, the ILD layer 216 is etched using a pattern in the photoresist layer to form grooves for the source / drain contacts 110a and 110b. In these embodiments, a deposition tool can be used to form the photoresist layer on the ILD layer 216 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ILD layer 216 based on the pattern to form grooves in the ILD layer 216 above the source / drain regions 106a and 106b. In some embodiments, an etching tool is used to etch through the ILD layer 216 and into portions of the source / drain regions 106a and 106b, such that the grooves extend into portions of the source / drain regions 106a and 106b. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming grooves in the ILD layer 216.
[0064] Deposition tools can be used to deposit source / drain contacts 110a and 110b using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, one or more additional layers are formed in the grooves prior to the formation of source / drain contacts 110a and 110b. As an example, a metal silicide layer (e.g., titanium silicide (TiSi)) can be formed on the top surface of the source / drain region 106a and / or the top surface of the source / drain region 106b prior to the formation of source / drain contacts 110a and / or 110b. x (or another metal silicide layer). As another example, one or more barrier layers may be formed on the bottom surface and / or sidewalls of the trench before forming the source / drain contacts 110a and / or 110b. As another example, one or more adhesion layers may be formed on the bottom surface and / or sidewalls of the trench before forming the source / drain contacts 110a and / or 110b. In some embodiments, a planarization tool is used to planarize the source / drain contacts 110a and / or 110b after deposition.
[0065] like Figure 2K As shown, a gate contact 112a can be formed on gate structure 108a, and a gate contact 112b can be formed on gate structure 108b. Gate contacts 112a and 112b can be formed in recesses in ILD layer 216 (for clarity, ...). Figure 2K (Not shown in the text).
[0066] In some embodiments, the ILD layer 216 is etched using a pattern in the photoresist layer to form recesses for gate contacts 112a and 112b. In these embodiments, a deposition tool can be used to form the photoresist layer on the ILD layer 216 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ILD layer 216 based on the pattern to form recesses in the ILD layer 216 above the gate structures 108a and 108b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming grooves in the ILD layer 216.
[0067] Gate contacts 112a and 112b can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, one or more additional layers are formed in the trench prior to the formation of gate contacts 112a and 112b. As an example, one or more barrier layers may be formed on the bottom surface and / or sidewalls of the trench prior to the formation of gate contacts 112a and / or 112b. As another example, one or more adhesion layers may be formed on the bottom surface and / or sidewalls of the trench prior to the formation of gate contacts 112a and / or 112b. In some embodiments, planarization tools are used to planarize gate contacts 112a and / or 112b after deposition.
[0068] like Figure 2L As shown, a plunger contact 114 can be formed at the intersection 116 of the fin grid 104. The plunger contact 114 can be formed in a groove in the ILD layer 216 (for clarity, Figure 2L (Not shown in the text).
[0069] In some embodiments, the ILD layer 216 is etched using a pattern in the photoresist layer to form grooves for the plunger contacts 114. In these embodiments, a deposition tool can be used to form the photoresist layer on the ILD layer 216 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ILD layer 216 based on the pattern to form grooves in the ILD layer 216 above the intersections 116 of the fin grid 104. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming grooves in the ILD layer 216.
[0070] Deposition tools can be used to deposit the plunger contact 114 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. In some embodiments, one or more additional layers are formed in the groove prior to forming the plunger contact 114. As an example, one or more barrier layers may be formed on the bottom surface and / or sidewalls of the groove prior to forming the plunger contact 114. As another example, one or more adhesive layers may be formed on the bottom surface and / or sidewalls of the groove prior to forming the plunger contact 114. In some embodiments, planarization tools are used to planarize the plunger contact 114 after deposition.
[0071] In some embodiments, source / drain contacts 110a and 110b are formed before gate contacts 112a and 112b and before plunger contacts 114. In some embodiments, source / drain contacts 110a and 110b are formed after gate contacts 112a and 112b and before plunger contacts 114. In some embodiments, source / drain contacts 110a and 110b are formed after gate contacts 112a and 112b and after plunger contacts 114. In some embodiments, gate contacts 112a and 112b are formed before plunger contacts 114. In some embodiments, gate contacts 112a and 112b are formed after plunger contacts 114. In some embodiments, source / drain contacts 110a and 110b are formed during the same one or more deposition operations to interact with gate contacts 112a and 112b. In some embodiments, source / drain contacts 110a and 110b and plunger contact 114 are formed during one or more deposition operations. In some embodiments, gate contacts 112a and 112b and plunger contact 114 are formed during one or more deposition operations.
[0072] As indicated above, Figures 2A to 2L Provided as an example. Other examples may differ from those provided. Figures 2A to 2L Examples described.
[0073] Figure 3 This is a flowchart of an example process 300 associated with forming the quantum computing semiconductor device described herein. In some embodiments, one or more semiconductor processing tools are used to perform the process. Figure 3 One or more process frames, such as deposition tools, exposure tools, developer tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or another type of semiconductor processing tools.
[0074] like Figure 3 As shown, process 300 may include forming a first plurality of semiconductor fin structures (block 310) over a semiconductor substrate of a semiconductor device. For example, one or more semiconductor processing tools may be used to form the first plurality of semiconductor fin structures (e.g., fin structure 104a) over a semiconductor substrate (e.g., substrate 102) of a semiconductor device (e.g., quantum computing semiconductor device 100), as described herein. In some embodiments, the first plurality of semiconductor fin structures extend in a first direction (e.g., the x-direction) within the semiconductor device and are arranged in a second direction (e.g., the y-direction) approximately perpendicular to the first direction within the semiconductor device.
[0075] like Figure 3 As further shown, process 300 may include forming a second plurality of semiconductor fin structures over a semiconductor substrate (box 320). For example, one or more semiconductor processing tools may be used to form the second plurality of semiconductor fin structures (e.g., fin structure 104b) over a semiconductor substrate, as described herein. In some embodiments, the second plurality of semiconductor fin structures extend in a second direction and are arranged in a first direction.
[0076] like Figure 3 As further illustrated, process 300 may include forming a first plurality of gate structures on the first plurality of semiconductor fin structures such that the first plurality of gate structures wrap around at least three sides of the first plurality of semiconductor fin structures (block 330). For example, one or more semiconductor processing tools may be used to form the first plurality of gate structures (e.g., gate structure 108a) on the first plurality of semiconductor fin structures such that the first plurality of gate structures wrap around at least three sides of the first plurality of semiconductor fin structures, as described herein.
[0077] like Figure 3 As further illustrated, process 300 may include forming a second plurality of gate structures on the second plurality of semiconductor fin structures such that the second plurality of gate structures wrap around at least three sides of the second plurality of semiconductor fin structures (block 340). For example, one or more semiconductor processing tools may be used to form the second plurality of gate structures (e.g., gate structure 108b) on the second plurality of semiconductor fin structures such that the second plurality of gate structures wrap around at least three sides of the second plurality of semiconductor fin structures, as described herein.
[0078] like Figure 3 As further shown, process 300 may include forming a first source / drain region at opposite ends of the first plurality of semiconductor fin structures (block 350). For example, one or more semiconductor processing tools may be used to form the first source / drain region (e.g., source / drain region 106a) at opposite ends of the first plurality of semiconductor fin structures, as described herein.
[0079] like Figure 3 As further shown, process 300 may include forming a second source / drain region at opposite ends of the second plurality of semiconductor fin structures (block 360). For example, one or more semiconductor processing tools may be used to form the second source / drain region (e.g., source / drain region 106b) at opposite ends of the second plurality of semiconductor fin structures, as described herein.
[0080] Process 300 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with those described elsewhere in this document.
[0081] In a first embodiment, forming the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures includes: forming a first pattern (e.g., first pattern 206) in a first mask layer (e.g., mask layer 204); forming a second pattern (e.g., second pattern 210) in a second mask layer (e.g., mask layer 202) using the first pattern in the first mask layer; and forming the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures using the second pattern in the second mask layer.
[0082] In the second embodiment, either alone or in combination with the first embodiment, the first pattern includes a first plurality of mandrels (e.g., mandrel 208) extending in the second direction and arranged in the first direction, and the second pattern includes a second plurality of mandrels (e.g., mandrel 210a) extending in the first direction and arranged in the second direction.
[0083] In the third embodiment, alone or in combination with one or more of the first and second embodiments, the second pattern further includes a third plurality of mandrels (e.g., mandrel 210b) extending in the second direction and arranged in the first direction, and the second plurality of mandrels intersect with the third plurality of mandrels.
[0084] In the fourth embodiment, forming the first plurality of gate structures and the second plurality of gate structures, alone or in combination with one or more of the first to third embodiments, includes: forming a gate dielectric layer (e.g., gate dielectric layer 214) on the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures; forming a gate electrode layer (e.g., gate electrode layer 212) on the gate dielectric layer; and etching the gate dielectric layer and the gate electrode layer to form the first plurality of gate structures and the second plurality of gate structures.
[0085] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 300 includes: forming an ILD layer (e.g., ILD layer 216) over the first plurality of semiconductor fin structures, the second plurality of semiconductor fin structures, the first plurality of gate structures, and the second plurality of gate structures; forming a groove in the ILD layer over the first plurality of gate structures and the second plurality of gate structures; and forming a first plurality of gate contacts (e.g., gate contact 112a) on the first plurality of gate structures and a second plurality of gate contacts (e.g., gate contact 112b) on the second plurality of gate structures in the groove.
[0086] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 300 includes: forming additional grooves in an ILD layer above an intersection (e.g., intersection 116) between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures; and forming plunger contacts at the intersection in the additional grooves.
[0087] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, process 300 includes: forming other grooves in the ILD layer above the first source / drain region and above the second source / drain region; and forming a first plurality of source / drain contacts (e.g., source / drain contact 110a) on the first source / drain region and a second plurality of source / drain contacts (e.g., source / drain contact 110b) on the second source / drain region in the other grooves.
[0088] although Figure 3 The example frame of process 300 is shown; however, in some implementations, process 300 includes... Figure 3 The boxes depicted in the diagram may be additional boxes, fewer boxes, different boxes, or boxes with different arrangements compared to the original boxes. Alternatively, two or more boxes in process 300 may be executed in parallel.
[0089] In this way, qubits in a quantum computing semiconductor device can be arranged in a two-dimensional array. The two-dimensional array can be implemented using fin-based semiconductor fabrication techniques. For example, a first active semiconductor region (e.g., a first fin structure) can extend in a first direction, and a second active semiconductor region (e.g., a second fin structure) can extend in a second direction. Qubits can be positioned at the intersection between the first and second active semiconductor regions. This allows qubits to be formed in a grid within the two-dimensional array, providing a greater qubit density and shorter distances between qubits (and therefore greater quantum computing performance) compared to a one-dimensional (e.g., linear) qubit array. Furthermore, implementing qubits using fin-based semiconductor fabrication techniques allows quantum computing arrays to be integrated with other complementary metal-oxide-semiconductor (CMOS) integrated circuits on the same semiconductor device.
[0090] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes a fin grid extending over the substrate, the fin grid including a first plurality of semiconductor fin structures extending in a first direction and arranged in a second direction, and a second plurality of semiconductor fin structures extending in the second direction and arranged in the first direction, wherein the first plurality of semiconductor fin structures intersect with the second plurality of semiconductor fin structures at a plurality of intersection points. The semiconductor device includes a first plurality of gate structures on the first plurality of semiconductor fin structures. The semiconductor device includes a second plurality of gate structures on the second plurality of semiconductor fin structures.
[0091] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first plurality of semiconductor fin structures over a semiconductor substrate of a semiconductor device, wherein the first plurality of semiconductor fin structures extend in the semiconductor device in a first direction and are arranged in the semiconductor device in a second direction approximately perpendicular to the first direction. The method includes forming a second plurality of semiconductor fin structures over the semiconductor substrate, wherein the second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction. The method includes forming a first plurality of gate structures on the first plurality of semiconductor fin structures such that the first plurality of gate structures wrap around at least three sides of the first plurality of semiconductor fin structures. The method includes forming a second plurality of gate structures on the second plurality of semiconductor fin structures such that the second plurality of gate structures wrap around at least three sides of the second plurality of semiconductor fin structures. The method includes forming a first source / drain region at opposite ends of the first plurality of semiconductor fin structures. The method includes forming a second source / drain region at opposite ends of the second plurality of semiconductor fin structures.
[0092] As described in more detail above, some embodiments described herein provide a quantum computing semiconductor device. The quantum computing semiconductor device includes a substrate. The quantum computing semiconductor device includes a first plurality of semiconductor fin structures above the substrate, wherein the first plurality of semiconductor fin structures extend in a first direction and are arranged in a second direction. The quantum computing semiconductor device includes a second plurality of semiconductor fin structures above the substrate, wherein the second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction. The quantum computing semiconductor device includes a plurality of qubit regions at the intersections between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures. The quantum computing semiconductor device includes a first plurality of barrier gate structures on the first plurality of semiconductor fin structures. The quantum computing semiconductor device includes a second plurality of barrier gate structures on the second plurality of semiconductor fin structures. The quantum computing semiconductor device includes a plurality of plunger contacts on the plurality of qubit regions.
[0093] The terms “approximately” and “substantially” can indicate the value of a given quantity that varies within 5% of said value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of said value). These values are merely examples and are not intended to be limiting. It should be understood that, in view of this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.
[0094] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.
[0095] Symbol Explanation
[0096] 100: Quantum computing semiconductor devices
[0097] 102: Substrate
[0098] 104: Fin grid
[0099] 104a: Fin structure
[0100] 104a-1 to 104a-n: Fin structure
[0101] 104b: Fin structure
[0102] 104b-1 to 104b-m: Fin structure
[0103] 106a: Source / Drain Region
[0104] 106b: Source / Drain Region
[0105] 108a: Gate structure
[0106] 108b: Gate structure
[0107] 108c: Barrier Gate Structure
[0108] 108d: Accumulation gate structure / Barrier gate structure
[0109] 110a: Source / Drain Contact
[0110] 110b: Source / Drain Contact
[0111] 112a: Gate contact
[0112] 112b: Gate contact
[0113] 114: Plunger Contact
[0114] 116: First intersection
[0115] 200: Examples
[0116] 202: Mask layer
[0117] 204: Mask layer
[0118] 206: First Pattern
[0119] 208: Mandrel
[0120] 210: Second Pattern
[0121] 210a: Mandrel
[0122] 210b: Mandrel
[0123] 212: Gate electrode layer
[0124] 214: Gate dielectric layer
[0125] 216: Interlayer Dielectric (ILD) Layer
[0126] 300: Process
[0127] 310: Box
[0128] 320: Box
[0129] 330: Box
[0130] 340: Box
[0131] 350: Box
[0132] 360: frame.
Claims
1. A semiconductor device, characterized in that... The semiconductor device includes: Substrate; A fin grid extending above the substrate, the fin grid comprising: A first plurality of semiconductor fin structures, extending in a first direction and arranged in a second direction; and A second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction, wherein the first plurality of semiconductor fin structures intersect with the second plurality of semiconductor fin structures at a plurality of intersection points; A plurality of gate structures are located on the plurality of semiconductor fin structures; and The second plurality of gate structures are located on the second plurality of semiconductor fin structures.
2. The semiconductor device according to claim 1, characterized in that... Two or more gate structures of the first plurality of gate structures are located on the same semiconductor fin structure of the first plurality of semiconductor fin structures; and Each of the two or more gate structures is positioned in the first direction between adjacent intersections of the plurality of intersections.
3. The semiconductor device according to claim 2, characterized in that... Two or more of the second plurality of gate structures are located on the same semiconductor fin structure in the second plurality of semiconductor fin structures.
4. The semiconductor device according to claim 1, characterized in that... It further includes: A plunger contact is located above the intersection between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures.
5. The semiconductor device according to claim 1, characterized in that... It further includes: The first plurality of gate contacts are located on the first plurality of gate structures; and The second plurality of gate contacts are located on the second plurality of gate structures.
6. The semiconductor device according to claim 1, characterized in that... It further includes: First source / drain regions are located at opposite ends of each of the first plurality of semiconductor fin structures; and The second source / drain region is located at the opposite ends of each of the second plurality of semiconductor fin structures.
7. A quantum computing semiconductor device, characterized in that... The quantum computing semiconductor device includes: Substrate; A first plurality of semiconductor fin structures are located above the substrate. The first plurality of semiconductor fin structures extend in a first direction and are arranged in a second direction; A second plurality of semiconductor fin structures are located above the substrate. The second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction; Multiple qubit regions are located at the intersections between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures; The first plurality of barrier gate structures are located on the first plurality of semiconductor fin structures; A second plurality of barrier gate structures are located on the second plurality of semiconductor fin structures; and Multiple plunger contacts are located on the multiple qubit regions.
8. The quantum computing semiconductor device according to claim 7, characterized in that... The plurality of qubit regions are arranged in a two-dimensional grid in the quantum computing semiconductor device.
9. The quantum computing semiconductor device according to claim 7, characterized in that... The first plurality of barrier gate structures are positioned in the first direction between adjacent pairs of the plurality of qubit regions; and The second plurality of barrier gate structures are positioned in the second direction between adjacent pairs of the plurality of qubit regions.
10. The quantum computing semiconductor device according to claim 7, characterized in that... It further includes: The first plurality of accumulation regions are located at the ends of the first plurality of semiconductor fin structures; and The second plurality of accumulation regions are located at the ends of the second plurality of semiconductor fin structures.