Display panel, display device, and electronic device

Abstract

A display panel, a display device, and an electronic device having improved integration of pixels are provided. The display panel can include a display area in which a first pixel and a second pixel connected to the first pixel through a connection electrode are disposed. The display panel can further include a non-display area at a periphery of the display area. The first pixel includes a first transistor connected between a first power line and a second node, a second transistor connected between the first node and a third node, a third transistor connected between the second node and the third node, and a first holding capacitor including one electrode connected to the connection electrode through the third node and another electrode connected to a data line. The second pixel includes a fourth transistor connected to the first power line, a fifth transistor connected between a fourth node and a sixth node, and a second holding capacitor including one electrode connected to the connection electrode through the sixth node and another electrode connected to the data line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0080049, filed on June 20, 2024, and Korean Patent Application No. 10-2024-0126887, filed on September 19, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to display panels, display devices including display panels, and electronic devices including display panels. Background Technology

[0004] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Therefore, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0005] Attempts have been made to provide display devices with high resolution. For this, technologies to increase pixel integration are needed. Utility Model Content

[0006] The embodiments provide a display panel that can improve pixel integration, a display device including the display panel, and an electronic device including the display panel.

[0007] According to one aspect of this disclosure, a display panel includes: a display area, a first pixel, and a second pixel connected to the first pixel via a connecting electrode disposed in the display area; and a non-display area at the periphery of the display area, wherein the first pixel includes: a first transistor including a gate electrode connected to a first node, the first transistor being connected between a first power line and a second node; a second transistor connected between the first node and a third node; a third transistor connected between the second node and the third node; and a first holding capacitor including an electrode connected to the connecting electrode via the third node and another electrode connected to a data line, and wherein the second pixel includes: a fourth transistor including a gate electrode connected to a fourth node, the fourth transistor being connected to the first power line; a fifth transistor connected between the fourth node and a sixth node; and a second holding capacitor including an electrode connected to the connecting electrode via the sixth node and another electrode connected to a data line.

[0008] The first pixel may further include a first storage capacitor, which includes one electrode connected to a first node and another electrode connected to a third electric field line. The second pixel may further include a second storage capacitor, which includes one electrode connected to a fourth node and another electrode connected to the third electric field line.

[0009] Each of the first to fifth transistors can be a transistor that includes a P-type semiconductor.

[0010] The second electric field line to which the second electric voltage is applied can be further disposed in the display area. The first pixel may also include a first light-emitting element disposed between the first transistor and the second electric field line. The second pixel may also include a second light-emitting element disposed between the fourth transistor and the second electric field line.

[0011] The first and second light-emitting elements can be configured to emit light simultaneously.

[0012] The second transistor may include a gate electrode connected to the i-th first scan line, where i is an integer of 1 or greater, the third transistor may include a gate electrode connected to the i-th second scan line, and the fifth transistor may include a gate electrode connected to the (i+1)-th first scan line.

[0013] The number of first scan lines set in the display area can be equal to the number of second scan lines set in the display area.

[0014] The number of first scan lines set in the display area can be at least twice the number of second scan lines set in the display area.

[0015] Each of the i-th first scan line, the i-th second scan line, and the (i+1)-th first scan line can extend in a first direction. Data lines can extend in a second direction different from the first direction. Connecting electrodes can extend in the second direction.

[0016] The fourth transistor can be connected between the first power line and the fifth node. The second pixel may also include a sixth transistor connected between the fifth node and the sixth node.

[0017] The second transistor may include a gate electrode connected to the i-th first scan line, where i is an integer of 1 or greater; the third transistor may include a gate electrode connected to the i-th second scan line; the fifth transistor includes a gate electrode connected to the (i+1)-th first scan line; and the sixth transistor may include a gate electrode connected to the (i+1)-th second scan line.

[0018] The display panel can be configured to initialize the corresponding voltages of the second and fifth nodes as a whole.

[0019] The display panel can be configured to compensate for changes in the characteristic values ​​of the first and fourth transistors as a whole.

[0020] According to one aspect of this disclosure, an electronic device includes: a display panel, wherein unit pixels, data lines, and a first power line are disposed in the display panel, wherein the unit pixels include a first pixel, a second pixel, and a connection electrode connected to the first pixel and the second pixel; and a data driving circuit configured to supply a data voltage to the data lines, wherein the first pixel includes: a first transistor including a gate electrode connected to a first node, the first transistor being connected between the first power line and the second node; a second transistor connected between the first node and a third node; a third transistor connected between the second node and the third node; and a first holding capacitor including an electrode connected to the connection electrode via the third node and another electrode connected to the data line, and wherein the second pixel includes: a fourth transistor including a gate electrode connected to a fourth node, the fourth transistor being connected to the first power line; a fifth transistor connected between the fourth node and a sixth node; and a second holding capacitor including an electrode connected to the connection electrode via the sixth node and another electrode connected to the data line.

[0021] The display device may also include a power supply circuit configured to supply a first power voltage to the first power line, which alternately has a first voltage at a high level and a second voltage at a low level.

[0022] The power supply circuit can be configured to: supply a first power voltage having a first voltage in a first time period, wherein the first time period is a conduction bias period; supply a first power voltage having a second voltage in a second time period, wherein the second time period is an initialization period; supply a first power voltage having a first voltage in a third time period, wherein the third time period is a compensation period; supply a first power voltage having a second voltage in a fourth and fifth time period, wherein the fourth time period is a data write period and the fifth time period is a margin period; and supply a first power voltage having a first voltage in a sixth time period, wherein the sixth time period is a transmission period.

[0023] A third power line can be further disposed in the display panel. The first pixel may also include a first storage capacitor, which includes an electrode connected to a first node and another electrode connected to the third power line. The second pixel may also include a second storage capacitor, which includes an electrode connected to a fourth node and another electrode connected to the third power line. The power supply circuit can be configured to supply a third power voltage to the third power line, which alternately has a fifth voltage at a high level and a sixth voltage at a low level.

[0024] The power supply circuit can be configured to: supply a third power voltage having a sixth voltage in the first and second time periods; supply a third power voltage having a fifth voltage in the third and fourth time periods; supply a third power voltage having a sixth voltage in the fifth time period; and supply a third power voltage having a fifth voltage in the sixth time period.

[0025] The second power line to which the second power voltage is applied can be further disposed in the display panel. The first pixel may also include a first light-emitting element disposed between the first transistor and the second power line. The second pixel may also include a second light-emitting element disposed between the fourth transistor and the second power line. The power supply circuit can be configured to supply a second power voltage having a high level of a third voltage during the first to fourth time periods, and a second power voltage having a low level of a fourth voltage during the fifth and sixth time periods.

[0026] The display device may further include a scan driving circuit configured to supply a first scan signal to each of a plurality of first scan lines disposed in the display panel, and to supply a second scan signal to each of a plurality of second scan lines disposed in the display panel. A second transistor may include a gate electrode connected to an i-th first scan line among the plurality of first scan lines, where i is an integer 1 or greater. A third transistor may include a gate electrode connected to an i-th second scan line among the plurality of second scan lines. A fifth transistor may include a gate electrode connected to an (i+1)-th first scan line among the plurality of first scan lines. A sixth transistor included in the second pixel may include a gate electrode connected to an (i+1)-th second scan line among the plurality of second scan lines. The scan drive circuit can be configured to: supply a first scan signal with a cutoff level to the i-th first scan line during the first, fifth, and sixth time periods; supply a first scan signal with a conduction level to the i-th first scan line during the second, third, and fourth time periods; supply a second scan signal with a cutoff level to the i-th second scan line during the first, fourth, fifth, and sixth time periods; and supply a second scan signal with a conduction level to the i-th second scan line during the second and third time periods.

[0027] According to one aspect of this disclosure, an electronic device includes: a processor configured to output first image data; and a display device configured to display an image corresponding to the first image data, wherein the display device includes: a display panel, unit pixels, data lines, and a first power line disposed in the display panel, wherein the unit pixel includes a first pixel, a second pixel, and a connection electrode connected to the first pixel and the second pixel; and a data driving circuit configured to supply a data voltage corresponding to the first image data to the data lines, wherein the first pixel includes: a first transistor including a gate electrode connected to a first node, the first transistor being connected between the first power line and the second node; a second transistor connected between the first node and a third node; a third transistor connected between the second node and the third node; and a first holding capacitor including an electrode connected to the connection electrode via the third node and another electrode connected to the data line, and wherein the second pixel includes: a fourth transistor including a gate electrode connected to a fourth node, the fourth transistor being connected to the first power line; a fifth transistor connected between the fourth node and a sixth node; and a second holding capacitor including an electrode connected to the connection electrode via the sixth node and another electrode connected to the data line. Attached Figure Description

[0028] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, aspects supported by this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always refer to the same elements.

[0030] Figure 1 This is a system block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 2 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0032] Figure 3 This is a diagram that briefly illustrates at least a portion of the display area according to an embodiment of the present disclosure.

[0033] Figure 4 This is an equivalent circuit diagram of a unit pixel according to an embodiment of the present disclosure.

[0034] Figure 5This is a diagram that briefly illustrates at least a portion of the display area according to an embodiment of the present disclosure.

[0035] Figure 6 This is a timing diagram illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0036] Figures 7 to 12 It shows the driver Figure 4 The diagram shows the method for representing a unit pixel.

[0037] Figure 13 This is an equivalent circuit diagram of a unit pixel according to another embodiment of the present disclosure.

[0038] Figure 14 This is a diagram that briefly illustrates at least a portion of the display area according to another embodiment of the present disclosure.

[0039] Figures 15 to 20 It shows the driver Figure 13 The diagram shows the method for representing a unit pixel.

[0040] Figure 21 This is a diagram illustrating an embodiment of a display system according to an embodiment of the present disclosure.

[0041] Figure 22 It is shown Figure 21 The diagram shows an application example of the display system.

[0042] Figure 23 This is a schematic diagram illustrating a head-mounted display device worn by a user. Detailed Implementation

[0043] In the following, embodiments will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement embodiments of this disclosure. This disclosure can be implemented in various different forms and is not limited to the exemplary embodiments described in this specification.

[0044] Parts irrelevant to the description will be omitted in order to clearly describe this disclosure, and throughout the specification and drawings, the same or similar constituent elements will be referred to by the same reference numerals. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0045] In some respects, for better understanding and ease of description, the size and thickness of each component shown in the accompanying drawings are arbitrarily illustrated, but embodiments of this disclosure are not limited thereto. For clarity, the thickness of certain portions and areas has been exaggerated.

[0046] In the description, the expression "equal" can mean "substantially equal." That is, it can mean equal to the extent that a person skilled in the art would understand them as equal. Other expressions may be those in which "substantially" is omitted. As used herein, the term "substantially" can mean approximately or actually.

[0047] It will be understood that although the terms “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the “first” element discussed below may also be referred to as the “second” element without departing from the teachings of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0048] The terms “below,” “under,” “above,” and “over” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0049] It will be understood that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as understood by one of those skilled in the art. Furthermore, terms defined by general dictionaries should not be idealized or overly formalized unless explicitly defined.

[0050] It will be further understood that, when used in this specification, the terms “comprising,” “including,” “having,” and “possessing” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 This is a system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0053] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110, a data driving circuit 120, a scanning driving circuit 130, a power supply circuit 150, and a timing controller 140, etc.

[0054] Display panel 110 may include a substrate SUB. Display panel 110 may include a display area DA containing multiple pixels PXL and a non-display area NDA located on the periphery of the display area DA. Multiple data lines DL1, DL2, ..., DLm (m is an integer of 1 or greater) and multiple scan lines SL1, SL2, ..., SLn (n is an integer of 1 or greater) electrically connected to the multiple pixels PXL may be disposed in display panel 110 (or display area DA). At least one power line is configured to apply a power voltage to the multiple pixels PXL disposed in display panel 110. Non-display area NDA may be located in the peripheral region of display area DA (e.g., the edge region of display area DA). At least one pad may be located in non-display area NDA, and data voltages and power voltages, etc., may be supplied to the multiple data lines DL1 to DLm through the pad.

[0055] The display panel 110 may be formed as a flat surface, but the embodiments disclosed herein are not limited thereto. For example, the display panel 110 may include curved portions formed at the left and right ends of the display panel 110, the curved portions including curved surfaces. The curved surfaces may have a constant curvature or a varying curvature. Furthermore, the display panel 110 may be formed as flexible, such that the display panel 110 is bendable, twistable, foldable, foldable, and / or rollable.

[0056] In some embodiments, the substrate SUB may comprise a rigid glass substrate. However, embodiments of this disclosure are not limited thereto, and the substrate SUB may comprise a flexible plastic substrate. In one example, the plastic substrate may be implemented as a polyimide (PI) substrate. In another embodiment, the substrate SUB may be implemented as a silicon substrate.

[0057] Multiple data lines DL1 to DLm may extend in one direction within the display panel 110. For example, this direction may be a second direction DR2. The multiple data lines DL1 to DLm may be arranged in the display panel 110 while extending along the second direction DR2 (e.g., entirely along the second direction DR2). For example, the second direction DR2 may be a direction that passes from the upper side to the lower side of the display panel 110, but embodiments of this disclosure are not limited thereto.

[0058] Multiple scan lines SL1 to SLn can extend in one direction within the display panel 110. For example, this direction can be a first direction DR1. The multiple scan lines SL1 to SLn can be arranged in the display panel 110 while extending along the first direction (e.g., entirely along the first direction DR1). The first direction DR1 can be a different direction from the second direction DR2, but embodiments of this disclosure are not limited thereto. For example, the first direction DR1 can be a direction that crosses from the left side to the right side of the display panel 110.

[0059] The data driving circuit 120 can be configured to supply data voltages to multiple data lines DL1 to DLm. The data driving circuit 120 can generate data voltages based on the second image data DATA2 and the data driving circuit control signal DCS, and synchronously output the generated data voltages to the multiple data lines DL1 to DLm in a timing sequence. The data driving circuit control signal DCS may include, for example, a source start pulse (SSP) signal, a source shift clock (SSC) signal, and a source output enable (SOE) signal.

[0060] The data driving circuit 120 can be implemented as an integrated circuit (e.g., a source driver integrated circuit (SDIC) formed separately from the display panel 110). The data driving circuit 120 can be formed together with the display panel 110 in at least a portion of the non-display area NDA of the display panel 110.

[0061] The scan drive circuit 130 can be configured to output scan signals to multiple scan lines SL1 to SLn in response to the scan drive circuit control signal SCS. The scan drive circuit control signal SCS may include a start signal indicating the start of a frame and a horizontal synchronization signal for synchronously outputting scan signals in a timing sequence.

[0062] The scan drive circuit 130 can be implemented as an integrated circuit (e.g., a gate driver integrated circuit (GDIC) formed separately from the display panel 110). The scan drive circuit 130 can be formed together with the display panel 110 in at least a portion of the non-display area NDA of the display panel 110.

[0063] The power supply circuit 150 can be configured to output a constant voltage with a constant voltage level. The power supply circuit 150 can output a power voltage (e.g., a first power voltage ELVDD, a second power voltage ELVSS, and / or a third power voltage VINT, etc.) supplied to the display panel 110. In some embodiments, the power supply circuit 150 can output a voltage (e.g., a gate high voltage or a gate low voltage, etc.) supplied to the scan drive circuit 130. In some embodiments, the power supply circuit 150 can output a voltage (e.g., a gamma voltage, etc.) supplied to the data drive circuit 120. The power supply circuit 150 may include, for example, a voltage regulator (e.g., a low dropout (LDO) regulator, etc.). The power supply circuit 150 can be implemented as, for example, a power management integrated circuit (PMIC). The power supply circuit 150 can be configured to output a power voltage to the power line in response to a power supply circuit control signal VCS.

[0064] The timing controller 140 can be configured to control the data drive circuit 120, the scan drive circuit 130, and the power supply circuit 150, etc. The timing controller 140 can generate and output control signals DCS, SCS, and VCS for controlling the data drive circuit 120, the scan drive circuit 130, and the power supply circuit 150 based on control signals CS (e.g., synchronization signals, clock signals, and / or data enable signals, etc.) input via the host HST. In some embodiments, the timing controller 140 can generate synchronization signals and data enable signals, etc., based on the control signals CS (e.g., information about the drive frequency (or frame rate) of the image displayed on the display panel 110) input via the host HST.

[0065] The timing controller 140 can receive first image data DATA1 input from the host HST and align the input first image data DATA1 in pixel line units. The timing controller 140 can synchronously convert the input first image data DATA1 with a predetermined interface (e.g., Low Voltage Differential Signaling (LVDS), DisplayPort (DP), or Embedded DisplayPort (eDP), etc.). The second image data DATA2 output by the timing controller 140 to the data drive circuit 120 can be image data converted internally by the timing controller 140 according to the predetermined interface.

[0066] In some embodiments, the timing controller 140 may be configured in the display device 100 as a logic type. In some embodiments, the timing controller 140 may be configured in the display device 100 as a processor type. The timing controller 140 may include at least one memory (e.g., a register, etc.).

[0067] The host HST may include a set-top box and an application processor (AP), etc. In one embodiment, the host HST may be a component located outside the display device 100 and not included in the display device 100. In another embodiment, the host HST may be installed within the display device 100. First image data DATA1 and control signal CS can be sent / received between the host HST and the display device 100 via an interface. The interface may be, for example, a serial programming interface (SPI), an internal integrated circuit (I2C), or a mobile industrial processor interface (MIPI), etc. However, embodiments of this disclosure are not limited thereto.

[0068] An electronic device DS according to an embodiment of the present disclosure may include a display device 100 and a host HST.

[0069] exist Figure 1In this system, circuits that supply signals and voltages to the display panel 110 are categorized according to their functions. For example, the data drive circuit 120 and the timing controller 140 can be formed in a single integrated circuit. The data drive circuit 120 and the timing controller 140 can be drive circuits / controllers categorized in a single integrated circuit according to their functions in the display device 100.

[0070] The display device 100 according to the embodiments of this disclosure can be used not only as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), but also as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0071] Figure 2 This is an equivalent circuit diagram of pixel PXL according to an embodiment of the present disclosure.

[0072] Reference Figure 2 According to embodiments of the present disclosure, the pixel PXL may include a pixel circuit PXC and a light-emitting element LE.

[0073] A pixel circuit (PXC) may include at least two switching elements and at least one storage element. In one embodiment, the switching elements may include transistors. In another embodiment, the storage device may include a capacitor. (See also...) Figure 2 The present disclosure illustrates an embodiment of a pixel PXL comprising three transistors and two capacitors. However, the embodiments of the present disclosure are not limited thereto, and the pixel circuit PXC can be freely selected according to the choice of those skilled in the art. Below, an embodiment of a pixel circuit PXC comprising three transistors and two capacitors will be described as an example.

[0074] Reference Figure 2 According to embodiments of the present disclosure, the pixel circuit PXC may include a first transistor TR1 to a third transistor TR3, a first capacitor Cst, and a second capacitor Cpr.

[0075] The first transistor TR1 may include a gate electrode connected to a first node N1, a first electrode connected to a first power line PL1, and a second electrode connected to a second node N2. The first electrode may be either a source electrode or a drain electrode (e.g., a source electrode). The second electrode may be either a source electrode or a drain electrode (e.g., a drain electrode). A first power voltage ELVDD may be applied to the first power line PL1. The first transistor TR1 may be configured to provide a current (e.g., a drive current) corresponding to the voltage applied to the first node N1. The first transistor TR1 may be referred to as a drive transistor.

[0076] The second transistor TR2 can be configured to switch the electrical connection between the first node N1 and the third node N3 in response to a first scan signal GW[i] (i is an integer of 1 or greater and n or less). The second transistor TR2 may include a gate electrode connected to the i-th first scan line SL1i. The first scan signal GW[i] can be supplied to the i-th first scan line SL1i. The second transistor TR2 can be electrically connected between the first node N1 and the third node N3 in response to the first scan signal GW[i] having an on level.

[0077] The third transistor TR3 can be configured to switch the electrical connection between the second node N2 and the third node N3 in response to the second scan signal GC[i]. The third transistor TR3 may include a gate electrode connected to the i-th second scan line SL2i. The second scan signal GC[i] can be supplied to the i-th second scan line SL2i. The third transistor TR3 can be electrically connected between the second node N2 and the third node N3 in response to the second scan signal GC[i] having an on level.

[0078] The first capacitor Cst may include one electrode connected to a first node N1 and another electrode connected to a third electric field line PL3. A third electric field voltage VINT may be applied to the third electric field line PL3. The one electrode and the other electrode may be positioned facing each other through a predetermined area (e.g., facing each other through a predetermined area in the vertical direction). The first capacitor Cst may be configured to maintain a potential difference between the third electric field line PL3 and the first node N1. The first capacitor Cst may be referred to as a storage capacitor Cst.

[0079] The second capacitor Cpr may include one electrode connected to the third node N3 and another electrode connected to the j-th data line DLj (j is an integer of 1 or greater and m or less). A data voltage Vdata may be applied to the j-th data line DLj. The one electrode and the other electrode may be positioned facing each other through a predetermined area (e.g., facing each other through a predetermined area in the vertical direction). The second capacitor Cpr may be configured to maintain the potential difference between the j-th data line DLj and the third node N3. The second capacitor Cpr may be referred to as the holding capacitor Cpr.

[0080] A light-emitting element LE can be connected between a second node N2 and a second electric field line PL2. A second electric field voltage ELVSS can be applied to the second electric field line PL2. The light-emitting element LE may include a first electrode (e.g., an anode electrode) connected to the second node N2 and a second electrode (e.g., a cathode electrode) connected to the second electric field line PL2. A light-emitting layer may be located between the first and second electrodes. In some embodiments, the light-emitting layer may be implemented as an organic light-emitting layer comprising organic light-emitting materials. However, embodiments of this disclosure are not limited thereto, and the light-emitting layer may include inorganic light-emitting materials, quantum dots, or nanorods, etc.

[0081] Reference Figure 2 The first transistor TR1 through the third transistor TR3 can all be implemented using transistors comprising P-type semiconductors. Therefore, the first transistor TR1 through the third transistor TR3 can be turned on in response to a low-level voltage and turned off in response to a high-level voltage. However, the embodiments of this disclosure are not limited thereto, and at least one of the first transistor TR1 through the third transistor TR3 can be implemented using transistors comprising N-type semiconductors. Transistors comprising N-type semiconductors can be turned on in response to a high-level voltage and turned off in response to a low-level voltage. In the following description, for ease of description, an embodiment in which the first transistor TR1 through the third transistor TR3 are all implemented using transistors comprising P-type semiconductors will be used as an example. However, the embodiments of this disclosure are not limited thereto.

[0082] In embodiments, each of the first transistor TR1 to the third transistor TR3 may be implemented as a polycrystalline silicon transistor. For example, each of the first transistor TR1 to the third transistor TR3 may comprise a semiconductor formed by a low-temperature polycrystalline silicon (LTPS) process. However, embodiments of this disclosure are not limited thereto. For example, at least one of the first transistor TR1 to the third transistor TR3 may comprise an oxide semiconductor.

[0083] Reference Figure 2The i-th scan line SLi may include the i-th first scan line SL1i and the i-th second scan line SL2i.

[0084] Figure 3 This is a diagram that briefly illustrates at least a portion of the display area DA according to an embodiment of the present disclosure.

[0085] For ease of explanation, some components set in the display area DA are not shown. For example, refer to... Figure 2 The first power line PL1 and the second power line PL2 described can be set in the display area DA, but they are not shown for ease of description.

[0086] Reference Figure 3 According to embodiments of this disclosure, a unit pixel PXU can be disposed in a display area DA. The unit pixel PXU may include a connecting electrode CNE. Pixels disposed in the unit pixel PXU can be connected to each other via the connecting electrode CNE. The connecting electrode CNE may extend in a second direction DR2.

[0087] In an embodiment, a unit pixel PXU may include a first pixel PXL1 and a second pixel PXL2 positioned adjacent to each other in the second direction DR2. However, embodiments of this disclosure are not limited thereto, and a unit pixel PXU may include three or more pixels arranged side by side in the second direction DR2. Hereinafter, an embodiment in which the unit pixel PXU includes two pixels adjacent to each other will be described as an example. However, embodiments of this disclosure are not limited thereto.

[0088] The term "adjacent" in this document can refer to elements that are relatively close to each other (e.g., within a target distance). In some other cases, the term "adjacent" in this document can refer to elements that are in contact with each other. In some cases, the term "adjacent" in this document can refer to elements of the same type, wherein another element of the same type is not disposed between said elements. For example, for a first pixel PXL1 and a second pixel PXL2 described as adjacent to each other, there is no other pixel between the first pixel PXL1 and the second pixel PXL2.

[0089] Reference Figure 3 Four unit pixels (PXU) are arranged in two rows and two columns. These unit pixels (PXU) can be referred to as the unit pixel PXU located at the top left, the unit pixel PXU located at the top right, the unit pixel PXU located at the bottom left, and the unit pixel PXU located at the bottom right.

[0090] The first pixel PXL1 of the unit pixel PXU located at the upper left can be connected to the third power line PL3, the i-th scan line SLi, the j-th data line DLj, and the connecting electrode CNE, etc.

[0091] The second pixel PXL2 of the unit pixel PXU located at the upper left can be connected to the third power line PL3, the (i+1)th scan line SLi+1, the jth data line DLj, and the connecting electrode CNE, etc.

[0092] The first pixel PXL1 of the unit pixel PXU located at the upper right end can be connected to the third power line PL3, the i-th scan line SLi, the (j+1)-th data line DLj+1, and the connecting electrode CNE, etc.

[0093] The second pixel PXL2 of the unit pixel PXU located at the upper right end can be connected to the third power line PL3, the (i+1)th scan line SLi+1, the (j+1)th data line DLj+1, and the connecting electrode CNE, etc.

[0094] The first pixel PXL1 of the unit pixel PXU located at the lower left end can be connected to the third power line PL3, the (i+2)th scan line SLi+2, the jth data line DLj, and the connecting electrode CNE, etc.

[0095] The second pixel PXL2 of the unit pixel PXU located at the lower left end can be connected to the third power line PL3, the (i+3)th scan line SLi+3, the jth data line DLj, and the connecting electrode CNE, etc.

[0096] The first pixel PXL1 of the unit pixel PXU located at the lower right end can be connected to the third power line PL3, the (i+2)th scan line SLi+2, the (j+1)th data line DLj+1, and the connecting electrode CNE, etc.

[0097] The second pixel PXL2 of the unit pixel PXU located at the lower right end can be connected to the third power line PL3, the (i+3)th scan line SLi+3, the (j+1)th data line DLj+1, and the connecting electrode CNE, etc.

[0098] Figure 4 This is an equivalent circuit diagram of a unit pixel PXU according to an embodiment of the present disclosure.

[0099] Reference Figure 4 The unit pixel PXU may include a first pixel PXL1 and a second pixel PXL2.

[0100] The first pixel PXL1 may include a first transistor TR1 to a third transistor TR3, a first storage capacitor Cst1, a first holding capacitor Cpr1, and a first light-emitting element LE1. The first transistor TR1 to the third transistor TR3, the first storage capacitor Cst1, the first holding capacitor Cpr1, and the first light-emitting element LE1 may respectively correspond to a reference. Figure 2The first transistor TR1 to the third transistor TR3, the first capacitor Cst, the second capacitor Cpr, and the light-emitting element LE are described. The first node N1 to the third node N3 of the first pixel PXL1 can respectively correspond to the reference. Figure 2 The first node N1 to the third node N3 are described.

[0101] The second pixel PXL2 may include a fourth transistor TR4 to a sixth transistor TR6, a second storage capacitor Cst2, a second holding capacitor Cpr2, and a second light-emitting element LE2. The fourth transistor TR4 to the sixth transistor TR6, the second storage capacitor Cst2, the second holding capacitor Cpr2, and the second light-emitting element LE2 may respectively correspond to reference... Figure 2 The description includes first transistors TR1 to TR3, first capacitor Cst, second capacitor Cpr, and light-emitting element LE. The fourth node N4 to the sixth node N6 of the second pixel PXL2 can respectively correspond to reference... Figure 2 The first node N1 to the third node N3 are described.

[0102] The gate electrode of the fifth transistor TR5 can be connected to the (i+1)th first scan line SL1i+1. The gate electrode of the sixth transistor TR6 can be connected to the (i+1)th second scan line SL2i+1. The (i+1)th scan line SL1i+1 may include the (i+1)th first scan line SL1i+1 and the (i+1)th second scan line SL2i+1.

[0103] The connecting electrode CNE can be connected between the third node N3 and the sixth node N6. The connecting electrode CNE can be connected to the first holding capacitor Cpr1, the second transistor TR2, the third transistor TR3, the second holding capacitor Cpr2, the fifth transistor TR5, and the sixth transistor TR6.

[0104] According to embodiments of this disclosure, the first pixel PXL1 and the second pixel PXL2 can be compensated as a whole through the connection electrode CNE.

[0105] According to embodiments of this disclosure, the storage capacity of the first holding capacitor Cpr1 and the second holding capacitor Cpr2 can be increased.

[0106] Figure 5 This is a diagram that briefly illustrates at least a portion of the display area DA according to an embodiment of the present disclosure.

[0107] The first pixel PXL1 of the unit pixel PXU located at the upper left can be connected to the third power line PL3, the i-th first scan line SL1i, the i-th second scan line SL2i, the j-th data line DLj, and the connecting electrode CNE, etc.

[0108] The second pixel PXL2 of the unit pixel PXU located at the upper left can be connected to the third power line PL3, the (i+1)th first scan line SL1i+1, the (i+1)th second scan line SL2i+1, the jth data line DLj, and the connecting electrode CNE, etc.

[0109] The first pixel PXL1 of the unit pixel PXU located at the upper right end can be connected to the third power line PL3, the i-th first scan line SL1i, the i-th second scan line SL2i, the (j+1)-th data line DLj+1, and the connecting electrode CNE, etc.

[0110] The second pixel PXL2 of the unit pixel PXU located at the upper right end can be connected to the third power line PL3, the (i+1)th first scan line SL1+1, the (i+1)th second scan line SL2i+1, the (j+1)th data line DLj+1, and the connecting electrode CNE, etc.

[0111] The first pixel PXL1 of the unit pixel PXU located at the lower left end can be connected to the third power line PL3, the (i+2)th first scan line SL1i+2, the (i+2)th second scan line SL2i+2, the jth data line DLj, and the connecting electrode CNE, etc.

[0112] The second pixel PXL2 of the unit pixel PXU located at the lower left end can be connected to the third power line PL3, the (i+3)th first scan line SL1i+3, the (i+3)th second scan line SL2i+3, the jth data line DLj, and the connecting electrode CNE, etc.

[0113] The first pixel PXL1 of the unit pixel PXU located at the lower right end can be connected to the third power line PL3, the (i+2)th first scan line SL1i+2, the (i+2)th second scan line SL2i+2, the (j+1)th data line DLj+1, and the connecting electrode CNE, etc.

[0114] The second pixel PXL2 of the unit pixel PXU located at the lower right end can be connected to the third power line PL3, the (i+3)th first scan line SL1i+3, the (i+3)th second scan line SL2i_3, the (j+1)th data line DLj+1, and the connecting electrode CNE, etc.

[0115] Figure 6 This is a timing diagram illustrating a method 600 for driving a display device according to an embodiment of the present disclosure.

[0116] Reference Figure 6 Method 600 may include the first time period PR1 to the sixth time period PR6.

[0117] In the first time period PR1, the first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a third voltage V3. The third power voltage VINT can have a fifth voltage V5 or a sixth voltage V6. The first scan signal GW[i] can have a cutoff level OFF. The second scan signal GC[i] can have a cutoff level OFF. The data voltage Vdata can be in a state with a predetermined constant voltage applied or in a high impedance state.

[0118] The expression "has" a signal level (e.g., off level OFF, on level ON, high level, or low level, etc.) in this document may refer to a state in which the signal is equal to or set to said level.

[0119] The first voltage V1 can be a high-level voltage. The third voltage V3 can be a high-level voltage. The fifth voltage V5 can be a high-level voltage. The sixth voltage V6 can be a low-level voltage. The cutoff level OFF can be a high-level voltage.

[0120] The first period, PR1, can be referred to as the conduction bias period.

[0121] In the second time period PR2, the first power voltage ELVDD can have a second voltage V2. The second power voltage ELVSS can have a third voltage V3. The third power voltage VINT can have a fifth voltage V5 or a sixth voltage V6. The first scan signal GW[i] can change from a cutoff level OFF to a conduction level ON. The second scan signal GC[i] can have a conduction level ON. The data voltage Vdata can be in a state with a predetermined constant voltage applied or in a high impedance state.

[0122] The second voltage V2 can be a low-level voltage. The third voltage V3 can be a high-level voltage. The fifth voltage V5 can be a high-level voltage. The sixth voltage V6 can be a low-level voltage. The cutoff level (OFF) can be a high-level voltage. The on level (ON) can be a low-level voltage.

[0123] The second time period, PR2, can be referred to as the initialization period.

[0124] The term "off-level" may be referred to as "turn-off level". The term "on-level" may be referred to as "turn-on level". The terms "high level" (or alternatively, "high voltage level") and "low level" (or alternatively, "low voltage level") are relative terms describing voltage levels that, when applied to the transistors described herein, may activate (e.g., "turn on") or disable (e.g., "turn off") the transistors based on the transistor type (e.g., P-type or N-type, etc.) or the circuit configuration including the transistors.

[0125] In the third time period PR3, the first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a third voltage V3. The third power voltage VINT can have a fifth voltage V5. The first scan signal GW[i] can have an ON level. The second scan signal GC[i] can have an ON level. The data voltage Vdata can be in a state with a predetermined constant voltage applied or in a high impedance state.

[0126] The first voltage V1 can be a high-level voltage. The third voltage V can be a high-level voltage. The fifth voltage V5 can be a high-level voltage. The ON level can be a low-level voltage.

[0127] The third period, PR3, can be referred to as the compensation period.

[0128] In the fourth time period PR4, the first power voltage ELVDD can have a second voltage V2. The second power voltage ELVSS can have a third voltage V3. The third power voltage VINT can have a fifth voltage V5. The first scan signal GW[i] can have an ON level. The second scan signal GC[i] can have an OFF level. In the data voltage Vdata, the signal can (e.g., through the data drive circuit 120 (see...)) Figure 1 It is applied to each of the multi-pixel rows.

[0129] The second voltage V2 can be a low-level voltage. The third voltage V3 can be a high-level voltage. The fifth voltage V5 can be a high-level voltage. The cutoff level OFF can be a high-level voltage. The conduction level ON can be a low-level voltage.

[0130] In the data voltage Vdata, the signal written to the i-th pixel row can be called "data voltage Vdata[i]". The signal written to the (i+1)-th pixel row can be called "data voltage Vdata[i+1]".

[0131] The fourth period, PR4, can be referred to as the data writing period.

[0132] In the fifth time period PR5, the first power voltage ELVDD can have a second voltage V2. The second power voltage ELVSS can decrease from the third voltage V3 to the fourth voltage V4. The third power voltage VINT can have a fifth voltage V5 or a sixth voltage V6. The first scan signal GW[i] can have a cutoff level OFF. The second scan signal GC[i] can have a cutoff level OFF. The data voltage Vdata can be in a state of applying a predetermined constant voltage or a high impedance state.

[0133] The second voltage V2 can be a low-level voltage. The third voltage V3 can be a high-level voltage. The fourth voltage V4 can be a low-level voltage. The fifth voltage V5 can be a high-level voltage. The sixth voltage V6 can be a low-level voltage. The cutoff level OFF can be a high-level voltage.

[0134] The fifth period, PR5, can also be referred to as the margin period.

[0135] In the sixth time period PR6, the first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a fourth voltage V4. The third power voltage VINT can have a fifth voltage V5. The first scan signal GW[i] can have a cutoff level OFF. The second scan signal GC[i] can have a cutoff level OFF. The data voltage Vdata can be in a state with a predetermined constant voltage applied or in a high impedance state.

[0136] The first voltage V1 can be a high-level voltage. The fourth voltage V4 can be a low-level voltage. The fifth voltage V5 can be a high-level voltage. The cutoff level OFF can be a high-level voltage.

[0137] The sixth period, PR6, can be referred to as the launch period.

[0138] Figures 7 to 12 It shows the driver Figure 4 The method 600 for the unit pixel PXU shown (see Figure 6 (The image is shown.)

[0139] Reference Figure 7 The image shows the first pixel PXL1 and the second pixel PXL2 in the first time period PR1.

[0140] During the first time period PR1, the second transistor TR2 and the fifth transistor TR5 can be turned off. The first scan signals GW[i] and GW[i+1] can have a cutoff level of OFF.

[0141] During the first time period PR1, the third transistor TR3 and the sixth transistor TR6 can be turned off. The second scan signals GC[i] and GC[i+1] can have a cutoff level of OFF.

[0142] The first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a third voltage V3. The third power voltage VINT can decrease from a fifth voltage V5 to a sixth voltage V6, and then increase back to a fifth voltage V5. Therefore, the voltage of each of the first node N1 and the fourth node N4 can also decrease and then increase again. Therefore, a conduction bias voltage with a conduction level can be applied to the first transistor TR1 and the fourth transistor TR4, and since the second power voltage ELVSS has a third voltage V3 with a high level, no drive current can flow through the first light-emitting element LE1 and the second light-emitting element LE2.

[0143] Reference Figure 8 The image shows the first pixel PXL1 and the second pixel PXL2 in the second time period PR2.

[0144] During the second time period PR2, the second transistor TR2 and the fifth transistor TR5 can be turned on. The first scan signals GW[i] and GW[i+1] can have an ON level.

[0145] During the second time period PR2, the third transistor TR3 and the sixth transistor TR6 can be turned on. The second scan signals GC[i] and GC[i+1] can have an ON level.

[0146] The first node N1, the second node N2, and the third node N3 can be electrically connected to each other. In the example, in response to the voltage of the third power line PL3 (i.e., the third power voltage VINT) changing from the fifth voltage V5 to the sixth voltage V6, the voltage of each of the first nodes N1 to the third node N3 can also be changed and initialized.

[0147] Nodes N4, N5, and N6 can be electrically connected. In the example, in response to a change in voltage from the fifth voltage V5 to the sixth voltage V6 on the third power line PL3, the voltage of each of nodes N4 through N6 can also be changed and initialized.

[0148] In some embodiments, since the third node N3 and the sixth node N6 are electrically connected to each other via the connection electrode CNE, the voltages of the second node N2 and the fifth node N5 can be initialized to be equal to each other. For example, embodiments of this disclosure support controlling the respective voltages of the second node N2 and the fifth node N5 such that the voltages are equal to each other. That is, for example, display panel 110 (see...) Figure 1The corresponding voltages of the second node N2 and the fifth node N5 can be initialized as a whole.

[0149] The first power voltage ELVDD can have a second voltage V2. The second power voltage ELVSS can have a third voltage V3. Therefore, no drive current can flow through the first transistor TR1 toward the first light-emitting element LE1. No drive current can flow through the fourth transistor TR4 toward the second light-emitting element LE2.

[0150] Reference Figure 9 The image shows the first pixel PXL1 and the second pixel PXL2 in the third time period PR3.

[0151] During the third time period PR3, the second transistor TR2 and the fifth transistor TR5 can be turned on. The first scan signals GW[i] and GW[i+1] can have an ON level.

[0152] During the third time period PR3, the third transistor TR3 and the sixth transistor TR6 can be turned on. The second scan signals GC[i] and GC[i+1] can have an ON level.

[0153] The first power voltage ELVDD can have a first voltage V1. Therefore, the first transistor TR1 can be diode-connected. Thus, for example, changes in the characteristic value of the first transistor TR1 (e.g., changes in the threshold voltage of the first transistor T1) can be compensated. Similarly, the fourth transistor TR4 can be diode-connected. Thus, for example, changes in the characteristic value of the fourth transistor TR4 (e.g., changes in the threshold voltage of the fourth transistor T4) can be compensated.

[0154] In some embodiments, since the third node N3 and the sixth node N6 are electrically connected to each other, the characteristic value changes of the first transistor TR1 and the fourth transistor TR4 can be compensated as a whole. That is, for example, in display panel 110 (see... Figure 1 It can compensate for the corresponding characteristic value changes of the first transistor TR1 and the fourth transistor TR4 as a whole.

[0155] The second power voltage ELVSS can have a third voltage V3. Therefore, no drive current can flow from the first transistor TR1 towards the first light-emitting element LE1. No drive current can flow from the fourth transistor TR4 towards the second light-emitting element LE2.

[0156] The third electrical voltage VINT can have a fifth voltage V5. A substantially identical potential difference can be formed across the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0157] Reference Figure 10AThe image shows the first pixel PXL1 and the second pixel PXL2 during at least a portion of the fourth time period PR4.

[0158] Reference Figure 10A During at least a portion of the fourth time period PR4, the data voltage Vdata[i] input to the first pixel PXL1 can be applied to the j-th data line DLj.

[0159] The second transistor TR2 can be turned on based on the voltage level of the first scan signal GW[i]. The first scan signal GW[i] with the on level can be applied to the i-th first scan line SL1i. Through the coupling effect of the first holding capacitor Cpr1, the voltage of the third node N3 can be changed to have a magnitude corresponding to the data voltage Vdata[i]. The first node N1 and the third node N3 can be electrically connected to each other, and the voltage corresponding to the data voltage Vdata[i] can be applied to the first node N1.

[0160] The first transistor TR1 and the third transistor TR3 can be turned off. The fourth transistor TR4 through the sixth transistor TR6 can be turned off.

[0161] Reference Figure 10B This shows the first pixel PXL1 and the second pixel PXL2 in another time period of the fourth time period PR4.

[0162] Reference Figure 10B In another time period of the fourth time period PR4, the data voltage Vdata[i+1] input to the second pixel PXL2 can be applied to the j-th data line DLj.

[0163] The fifth transistor TR5 can be turned on based on the voltage level of the first scan signal GW[i+1]. The first scan signal GW[i+1] can be applied to the (i+1)th first scan line SL1i+1. Through the coupling effect of the second holding capacitor Cpr2, the voltage of the sixth node N6 can be changed to have a magnitude corresponding to the data voltage Vdata[i+1]. The fourth node N4 can be electrically connected to the sixth node N6, and a voltage corresponding to the data voltage Vdata[i+1] can be applied to the fourth node N4.

[0164] The fourth transistor TR4 and the sixth transistor TR6 can be turned off. The first transistor TR1 through the third transistor TR3 can be turned off.

[0165] Reference Figure 11 The image shows the first pixel PXL1 and the second pixel PXL2 in the fifth time period PR5.

[0166] The first electrical voltage ELVDD can have a second voltage V2. The second electrical voltage ELVSS can decrease from a third voltage V3 to a fourth voltage V4.

[0167] The third power voltage VINT can decrease from the fifth voltage V5 to the sixth voltage V6 before / after the second power voltage ELVSS decreases from the third voltage V3 to the fourth voltage V4, and then increase back to the fifth voltage V5.

[0168] The first transistor TR1 through the sixth transistor TR6 can be turned off.

[0169] Reference Figure 12 The image shows the first pixel PXL1 and the second pixel PXL2 in the sixth time period PR6.

[0170] The first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a fourth voltage V4. Therefore, the first transistor TR1 can provide a drive current Idr with a magnitude corresponding to the voltage of the first node N1. The fourth transistor TR4 can provide a drive current Idr with a magnitude corresponding to the voltage of the fourth node N4.

[0171] The second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the sixth transistor TR6 can be turned off.

[0172] The first pixel PXL1 and the second pixel PXL2 can emit light simultaneously (or during the same time period).

[0173] According to embodiments of this disclosure, the characteristic value variations of the first transistor TR1 and the fourth transistor TR4 can be compensated as a whole.

[0174] In some respects, it can exhibit the effect of the electrodes of the first holding capacitor Cpr1 and the second holding capacitor Cpr2 being electrically connected to each other.

[0175] Therefore, display quality can be improved. Furthermore, pixel density can be improved, thereby increasing pixels per inch (PPI).

[0176] Figure 13 This is an equivalent circuit diagram of a unit pixel PXU' according to another embodiment of the present disclosure.

[0177] Reference Figure 13 The unit pixel PXU' may include the first pixel PXL1 and the second pixel PXL2'.

[0178] The first pixel circuit PXC1 of the first pixel PXL may include a first transistor TR1 to a third transistor TR3, a first storage capacitor Cst, a first holding capacitor Cpr1, and a first light-emitting element LE1. The first transistor TR1 to the third transistor TR3, the first storage capacitor Cst, the first holding capacitor Cpr1, and the first light-emitting element LE1 may respectively correspond to reference... Figure 2 The first transistor TR1 to the third transistor TR3, the first capacitor Cst, the second capacitor Cpr, and the light-emitting element LE are described. The first node N1 to the third node N3 of the first pixel PXL1 can respectively correspond to the reference. Figure 2 The first node N1 to the third node N3 are described.

[0179] The second pixel PXC2' may include a fourth transistor TR4 to a fifth transistor TR5, a second storage capacitor Cst2, a second holding capacitor Cpr2, and a second light-emitting element LE2.

[0180] and Figure 4 Compared to the second pixel PXL2 shown, in Figure 13 In the second pixel PXL2' shown, the sixth transistor TR6 can be omitted. Therefore, the (i+1)th second scan line SL2i+1 can be omitted.

[0181] The connecting electrode CNE can be connected between the third node N3 and the sixth node N6. The connecting electrode CNE can be connected to the first holding capacitor Cpr1, the second transistor TR2, the third transistor TR3, the second holding capacitor Cpr2, and the fifth transistor TR5.

[0182] According to embodiments of this disclosure, the first pixel PXL1 and the second pixel PXL2' can be compensated as a whole through the connection electrode CNE.

[0183] According to embodiments of this disclosure, the storage capacity of the first holding capacitor Cpr1 and the second holding capacitor Cpr2 can be increased.

[0184] Figure 14 This is a diagram that briefly illustrates at least a portion of the display area according to another embodiment of the present disclosure.

[0185] and Figure 5Compared to the embodiments shown, the unit pixel PXU' can be connected to three scan lines. However, the embodiments of this disclosure are not limited to this. For example, the unit pixel PXU' can be connected to at least three first scan lines while simultaneously being connected to one second scan line. In one or more embodiments, the number of first scan lines disposed in the display area DA can be at least twice the number of second scan lines disposed in the display area DA. Hereinafter, an embodiment describing the unit pixel PXU' connecting two first scan lines and one second scan line will be used as an example. However, the embodiments of this disclosure are not limited to this.

[0186] The unit pixel PXU' located at the upper left end can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, and the (i+1)-th first scan line SL1i+1.

[0187] and Figure 5 Compared to the embodiment shown, the (i+1)th second scan line SL2i+1 can be omitted in the display area DA. Therefore, since the (i+1)th second scan line SL2i+1 is omitted, the pixel integration can be improved. Thus, for example, the PPI can be further increased.

[0188] In some respects, the scan drive circuit 130 can be omitted (see Figure 1 The configuration for supplying scan signals to the (i+1)th second scan line SL2i+1 is thus simplified. Therefore, the configuration of the scan drive circuit 130 can be further simplified, and the area in which the scan drive circuit 130 is disposed can be reduced (e.g., the non-display area NDA (see...)). Figure 1 Therefore, for example, the area of ​​the display area DA can become relatively wide.

[0189] Figures 15 to 20 It shows the driver Figure 13 Method 600 for the unit pixel PXU' shown (see Figure 6 (The image is shown.)

[0190] Reference Figure 15 The image shows the first pixel PXL1 and the second pixel PXL2' in the first time period PR1.

[0191] During the first time period PR1, the second transistor TR2 and the fifth transistor TR5 can be turned off. The first scan signals GW[i] and GW[i+1] can have a cutoff level of OFF.

[0192] During the first time period PR1, the third transistor TR3 can be turned off. The second scan signal GC[i] can have a cutoff level of OFF.

[0193] The first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a third voltage V3. The third power voltage VINT can decrease from a fifth voltage V5 to a sixth voltage V6, and then increase back to a fifth voltage V5. Therefore, the voltage of each of the first node N1 and the fourth node N4 can also decrease and then increase again. Therefore, a conduction bias voltage with a conduction level can be applied to the first transistor TR1 and the fourth transistor TR4, and since the second power voltage ELVSS has a third voltage V3 with a high level, no drive current can flow through the first light-emitting element LE1 and the second light-emitting element LE2.

[0194] Reference Figure 16 The image shows the first pixel PXL1 and the second pixel PXL2' in the second time period PR2.

[0195] During the second time period PR2, the second transistor TR2 and the fifth transistor TR5 can be turned on. The first scan signals GW[i] and GW[i+1] can have an ON level.

[0196] During the second time period PR2, the third transistor TR3 can be turned on. The second scan signal GC[i] can have an ON level.

[0197] The first node N1, the second node N2, and the third node N3 can be electrically connected to each other. In the example, in response to the voltage of the third power line PL3 (i.e., the third power voltage VINT) changing from the fifth voltage V5 to the sixth voltage V6, the voltage of each of the first nodes N1 to the third node N3 can also be changed and initialized.

[0198] The fourth node N4 and the sixth node N6 can be electrically connected to each other. In the example, in response to the voltage of the third power line PL3 (i.e., the third power voltage VINT) changing from the fifth voltage V5 to the sixth voltage V6, the voltage of each of the fourth node N4 and the sixth node N6 can also be changed and initialized.

[0199] The second node N2, the third node N3, and the sixth node N6 can be electrically connected to each other via the connecting electrode CNE.

[0200] The first power voltage ELVDD can have a second voltage V2. The second power voltage ELVSS can have a third voltage V3. Therefore, no drive current can flow through the first transistor TR1 toward the first light-emitting element LE1. No drive current can flow through the fourth transistor TR4 toward the second light-emitting element LE2.

[0201] Reference Figure 17 The image shows the first pixel PXL1 and the second pixel PXL2' in the third time period PR3.

[0202] During the third time period PR3, the second transistor TR2 and the fifth transistor TR5 can be turned on. The first scan signals GW[i] and GW[i+1] can have an ON level.

[0203] During the third time period PR3, the third transistor TR3 can be turned on. The second scan signal GC[i] can have an ON level.

[0204] The first power voltage ELVDD can have a first voltage V1. Therefore, the first transistor TR1 can be diode-connected. Thus, for example, changes in the characteristic value of the first transistor TR1 (e.g., changes in the threshold voltage of the first transistor T1) can be compensated. The first power voltage ELVDD having the first voltage V1 can be applied to the fourth transistor TR4, and a voltage obtained by reflecting changes in the characteristic value of the first transistor TR1 (e.g., changes in the threshold voltage of the first transistor T1) can be applied to the gate electrode of the fourth transistor TR4. In some embodiments, the first transistor TR1 and the fourth transistor TR4 can be positioned adjacent to each other, and the degree of degradation of the first transistor TR1 while displaying an image and the degree of degradation of the fourth transistor TR4 while displaying an image can be substantially similar to each other. Therefore, the voltage obtained by compensating for changes in the characteristic value of the first transistor TR1 can be used to compensate for changes in the characteristic value of the fourth transistor TR4. Therefore, the voltage obtained by compensating for changes in the characteristic value of the first transistor TR1 can be applied to the fourth node N4, and the corresponding voltage can be used to compensate for changes in the characteristic value of the fourth transistor TR4.

[0205] Therefore, the characteristic value changes of the first transistor TR1 and the fourth transistor TR4 can be compensated as a whole.

[0206] The second power voltage ELVSS can have a third voltage V3. Therefore, no drive current can flow from the first transistor TR1 towards the first light-emitting element LE1. No drive current can flow from the fourth transistor TR4 towards the second light-emitting element LE2.

[0207] The third electrical voltage VINT can have a fifth voltage V5. A substantially identical potential difference can be formed across the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0208] Reference Figure 18A The image shows the first pixel PXL1 and the second pixel PXL2' during at least a portion of the fourth time period PR4.

[0209] Reference Figure 18ADuring at least a portion of the fourth time period PR4, the data voltage Vdata[i] input to the first pixel PXL1 can be applied to the j-th data line DLj.

[0210] The second transistor TR2 can be turned on based on the voltage level of the first scan signal GW[i]. The first scan signal GW[i] with the on level can be applied to the i-th first scan line SL1i. Through the coupling effect of the first holding capacitor Cpr1, the voltage of the third node N3 can be changed to have a magnitude corresponding to the data voltage Vdata[i]. The first node N1 and the third node N3 can be electrically connected to each other, and the voltage corresponding to the data voltage Vdata[i] can be applied to the first node N1.

[0211] The first transistor TR1 and the third transistor TR3 can be turned off. The fourth transistor TR4 and the fifth transistor TR5 can be turned off.

[0212] Reference Figure 18B This shows the first pixel PXL1 and the second pixel PXL2' in another time period of the fourth time period PR4.

[0213] Reference Figure 18B In another time period of the fourth time period PR4, the data voltage Vdata[i+1] input to the second pixel PXL2' can be applied to the j-th data line DLj.

[0214] The fifth transistor TR5 can be turned on based on the voltage level of the first scan signal GW[i+1]. The first scan signal GW[i+1] can be applied to the (i+1)th first scan line SL1i+1. Through the coupling effect of the second holding capacitor Cpr2, the voltage of the sixth node N6 can be changed to have a magnitude corresponding to the data voltage Vdata[i+1]. The fourth node N4 can be electrically connected to the sixth node N6, and a voltage corresponding to the data voltage Vdata[i+1] can be applied to the fourth node N4.

[0215] The fourth transistor TR4 can be turned off. The first transistor TR1 through the third transistor TR3 can be turned off.

[0216] Reference Figure 19 The image shows the first pixel PXL1 and the second pixel PXL2' in the fifth time period PR5.

[0217] The first electrical voltage ELVDD can have a second voltage V2. The second electrical voltage ELVSS can decrease from a third voltage V3 to a fourth voltage V4.

[0218] The third power voltage VINT can decrease from the fifth voltage V5 to the sixth voltage V6 before / after the second power voltage ELVSS decreases from the third voltage V3 to the fourth voltage V4, and then increase back to the fifth voltage V5.

[0219] The first transistor TR1 through the fifth transistor TR5 can be turned off.

[0220] Reference Figure 20 The image shows the first pixel PXL1 and the second pixel PXL2' in the sixth time period PR6.

[0221] The first power voltage ELVDD can have a first voltage V1. The second power voltage ELVSS can have a fourth voltage V4. Therefore, the first transistor TR1 can provide a drive current Idr with a magnitude corresponding to the voltage of the first node N1. The fourth transistor TR4 can provide a drive current Idr with a magnitude corresponding to the voltage of the fourth node N4.

[0222] The second transistor TR2, the third transistor TR3, and the fifth transistor TR5 can be turned off.

[0223] The first pixel PXL1 and the second pixel PXL2' can emit light simultaneously (or during the same time period).

[0224] According to embodiments of this disclosure, the characteristic value variations of the first transistor TR1 and the fourth transistor TR4 can be compensated as a whole.

[0225] In some respects, it can exhibit the effect of the electrodes of the first holding capacitor Cpr1 and the electrodes of the second holding capacitor Cpr2 being electrically connected to each other.

[0226] Therefore, display quality can be improved. Furthermore, pixel density can be improved, thereby increasing PPI.

[0227] Figure 21 This is a diagram illustrating an embodiment of a display system 2100 according to an embodiment of the present disclosure.

[0228] Reference Figure 21 The display system 2100 may include a processor 2110 and one or more display devices 2122 and 2124. The display system 2100 may be provided as... Figure 1 The electronic device DS shown is shown.

[0229] Processor 2110 can perform various tasks and calculations. In embodiments, processor 2110 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, and a central processing unit (CPU), etc. Processor 2110 can be connected to other components of display system 2100 via a bus system to control the components of display system 2100.

[0230] exist Figure 21 The diagram shows a display system 2100 including a first display device 2122 and a second display device 2124. A processor 2110 can be connected to the first display device 2122 via a first channel CH1 and to the second display device 2124 via a second channel CH2.

[0231] Through the first channel CH1, the processor 2110 can send the first image data IMG1 and the first control signal CTRL1 to the first display device 2122. The first display device 2122 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 2122 can be connected to a reference... Figure 1 The described display device 100 is configured identically. The first image data IMG1 and the first control signal CTRL1 can be provided respectively as... Figure 1 The first image data DATA1 and the control signal CTRL are shown in the figure.

[0232] Through the second channel CH2, the processor 2110 can send the second image data IMG2 and the second control signal CTRL2 to the second display device 2124. The second display device 2124 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 2124 can be connected to a reference... Figure 1 The described display device 100 is configured identically. The second image data IMG2 and the second control signal CTRL2 can be provided respectively as... Figure 1 The first image data DATA1 and the control signal CTRL are shown in the figure.

[0233] Processor 2110 can be compared with reference Figure 1 The host HST is configured as described.

[0234] Display system 2100 may include a computing system for providing image display functionality, such as a portable computer, mobile phone, smartphone, tablet PC, smartwatch, watch phone, portable multimedia player (PMP), navigation device, or ultra-mobile personal computer (UMPC). In some aspects, display system 2100 may include at least one of a head-mounted display device (or head-mounted display (HMD)), virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0235] Figure 22 It is shown Figure 21 The diagram shows an application example of the display system 2100.

[0236] Reference Figure 22 , Figure 21 The display system 2100 shown can be applied to a head-mounted display device 2200. The head-mounted display device 2200 can be a wearable electronic device that can be worn on a user's head.

[0237] The head-mounted display device 2200 may include a head-mounting strap 2210 and a display device housing 2220. The head-mounting strap 2210 may be connected to the display device housing 2220. The head-mounting strap 2210 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2200 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, the embodiments are not limited thereto. For example, the head-mounting strap 2210 may be implemented in the form of an eyeglass frame or a helmet, etc.

[0238] The display device housing 2220 can accommodate Figure 21 The first display device 2122 and the second display device 2124 are shown. The display device housing 2220 can further accommodate... Figure 21 The processor 2110 shown is shown.

[0239] Figure 23 This is a schematic diagram showing a head-mounted display device 2200 worn by a user USR.

[0240] Reference Figure 23 First display device 2122 (see Figure 21 The first display panel DP1 and the second display device 2124 (see) Figure 21 The second display panel DP2 can be disposed in the head-mounted display device 2200. The head-mounted display device 2200 may also include one or more lenses. For example, the head-mounted display device 2200 may also include a left eye lens LLNS and a right eye lens RLNS.

[0241] In the display device housing 2220, the right eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user USR. In the display device housing 2220, the left eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user USR.

[0242] The image output from the first display panel DP1 can be viewed by the right eye of the user USR through the right eye lens RLNS. The right eye lens RLNS refracts light emitted from the first display panel DP1 towards the right eye of the user USR. The right eye lens RLNS performs an optical function to adjust the viewing distance between the first display panel DP1 and the right eye of the user USR.

[0243] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS refracts the light emitted from the second display panel DP2 towards the user's left eye. The left eye lens LLNS performs an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0244] In one embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a pancake-shaped cross-section. In another embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. In one or more embodiments, each of the first display panel DP1 and the second display panel DP2 may output images corresponding to the sub-regions of the multi-channel lens, and the output images may be observed by the user USR while passing through the respective sub-regions.

[0245] In the display panel, display device including the display panel, and electronic device including the display panel according to the present disclosure, the pixel integration can be improved.

[0246] Example embodiments have been disclosed herein, and although specific terminology has been used, such terminology is used and will be interpreted in a general and descriptive sense, and is not intended to be limiting. In some instances, unless specifically indicated otherwise, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, as of the date of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: A display area, a first pixel, and a second pixel connected to the first pixel via a connecting electrode are disposed in the display area; and The non-display area is located at the periphery of the display area. in: The first pixel includes: A first transistor includes a gate electrode connected to a first node, the first transistor being connected between a first power line and a second node; The second transistor is connected between the first node and the third node; A third transistor is connected between the second node and the third node; and The first holding capacitor includes one electrode connected to the connection electrode via the third node and another electrode connected to the data line, and The second pixel includes: A fourth transistor includes a gate electrode connected to a fourth node, the fourth transistor being connected to the first power line; A fifth transistor is connected between the fourth and sixth nodes; and The second holding capacitor includes one electrode connected to the connection electrode via the sixth node and another electrode connected to the data line.

2. The display panel according to claim 1, characterized in that: The first pixel further includes a first storage capacitor, which includes one electrode connected to the first node and another electrode connected to the third electric field line. The second pixel also includes a second storage capacitor, which includes one electrode connected to the fourth node and another electrode connected to the third power line.

3. The display panel according to claim 1, characterized in that, Each of the first to fifth transistors is a transistor comprising a P-type semiconductor, and in: The second electric field line to which the second electric voltage is applied is further disposed in the display area. The first pixel further includes a first light-emitting element disposed between the first transistor and the second power line, and The second pixel also includes a second light-emitting element disposed between the fourth transistor and the second power line.

4. The display panel according to claim 1, characterized in that: The second transistor includes a gate electrode connected to the i-th first scan line, where i is an integer of 1 or greater. The third transistor includes a gate electrode connected to the i-th second scan line, and The fifth transistor includes a gate electrode connected to the (i+1)th first scan line.

5. The display panel according to claim 4, characterized in that: Each of the i-th first scan line, the i-th second scan line, and the (i+1)-th first scan line extends in a first direction. The data line extends in a second direction different from the first direction, and The connecting electrode extends in the second direction.

6. The display panel according to claim 1, characterized in that: The fourth transistor is connected between the first power line and the fifth node, and The second pixel also includes a sixth transistor connected between the fifth node and the sixth node. in: The second transistor includes a gate electrode connected to the i-th first scan line, where i is an integer of 1 or greater. The third transistor includes a gate electrode connected to the i-th second scan line. The fifth transistor includes a gate electrode connected to the (i+1)th first scan line, and The sixth transistor includes a gate electrode connected to the (i+1)th second scan line.

7. A display device, characterized in that, The display device includes: A display panel, unit pixels, data lines, and a first power line are disposed in the display panel, wherein the unit pixel includes a first pixel, a second pixel, and a connection electrode connected to the first pixel and the second pixel; and A data driving circuit is configured to supply data voltage to the data lines. Wherein, the first pixel includes: A first transistor includes a gate electrode connected to a first node, the first transistor being connected between the first power line and the second node; The second transistor is connected between the first node and the third node; A third transistor is connected between the second node and the third node; and The first holding capacitor includes one electrode connected to the connection electrode via the third node and another electrode connected to the data line, and The second pixel includes: A fourth transistor includes a gate electrode connected to a fourth node, the fourth transistor being connected to the first power line; A fifth transistor is connected between the fourth and sixth nodes; and The second holding capacitor includes one electrode connected to the connection electrode via the sixth node and another electrode connected to the data line.

8. The display device according to claim 7, characterized in that, The display device further includes a power supply circuit configured to supply a first power voltage to the first power line, the first voltage having an alternating high level and a second voltage having a low level. The power supply circuit is configured as follows: The first power voltage having the first voltage is supplied during the first time period, wherein the first time period is the conduction bias period; The first power voltage with the second voltage is supplied during the second time period, wherein the second time period is the initialization period; The first power voltage with the first voltage is supplied during the third time period, wherein the third time period is a compensation period; The first power voltage with the second voltage is supplied during the fourth and fifth time periods, wherein the fourth time period is a data writing period and the fifth time period is a margin period; and The first power voltage with the first voltage is supplied during the sixth time period, wherein the sixth time period is the transmission period.

9. The display device according to claim 8, characterized in that: A third power line is further provided in the display panel. The first pixel also includes a first storage capacitor, which includes one electrode connected to the first node and another electrode connected to the third electric field line. The second pixel also includes a second storage capacitor, which includes one electrode connected to the fourth node and another electrode connected to the third power line. The power supply circuit is configured to supply the third power line with a third power voltage that alternately has a fifth voltage at a high level and a sixth voltage at a low level. The power supply circuit is configured as follows: The third electrical voltage having the sixth voltage is supplied during the first and second time periods; During the third and fourth time periods, the third electrical voltage having the fifth voltage is supplied; During the fifth time period, the third electrical voltage having the sixth voltage is supplied; and During the sixth time period, the third electrical voltage having the fifth voltage is supplied.

10. An electronic device, characterized in that, The electronic device includes: The processor is configured to output first image data; and The display device is configured to display an image corresponding to the first image data. The display device includes: A display panel, unit pixels, data lines, and a first power line are disposed in the display panel, wherein the unit pixel includes a first pixel, a second pixel, and a connection electrode connected to the first pixel and the second pixel; and A data driving circuit is configured to supply a data voltage corresponding to the first image data to the data line. in: The first pixel includes: A first transistor includes a gate electrode connected to a first node, the first transistor being connected between the first power line and the second node; The second transistor is connected between the first node and the third node; A third transistor is connected between the second node and the third node; and The first holding capacitor includes one electrode connected to the connecting electrode via the third node and another electrode connected to the data line, and the second pixel includes: A fourth transistor includes a gate electrode connected to a fourth node, the fourth transistor being connected to the first power line; A fifth transistor is connected between the fourth and sixth nodes; and The second holding capacitor includes one electrode connected to the connection electrode via the sixth node and another electrode connected to the data line.

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