A kind of based on video memory expansion bus multi-GPU video memory sharing communication control device

Abstract

The utility model relates to a kind of multi-GPU display memory sharing communication control device based on display memory expansion bus, including controller, multiple expansion switch modules and multiple control switch modules, multiple expansion switch modules and multiple computing power graphics card one-to-one correspondence, multiple control switch modules and multiple expansion switch modules one-to-one correspondence, the control end of multiple expansion switch modules is connected respectively by the signal output end of controller, the one end of each expansion switch module is connected display memory expansion bus, the other end of each expansion switch module is connected corresponding computing power graphics card;The one end of multiple control switch modules is connected respectively by the signal input end of controller, the control end of multiple control switch modules is connected respectively by the CPU of computing platform, the other end of multiple control switch modules is accessed first power voltage;The utility model can control the quantity of the display memory sharing of multiple computing power graphics card, the quantity of the computing power graphics card of shared display memory is realized according to need control, and energy consumption is reduced.

Description

Technical Field

[0001] This utility model relates to the field of video memory sharing technology, specifically to a multi-GPU video memory sharing communication control device based on a video memory expansion bus. Background Technology

[0002] Artificial intelligence computing platforms need to support flexible computing power expansion and dynamic resource allocation. Current technologies typically employ multiple high-performance graphics cards configured on a single computing platform to meet computing power demands, while simultaneously utilizing memory-sharing mechanisms among these graphics cards to achieve the desired computing power.

[0003] However, in existing technologies, under conditions with low computing power requirements, the shared state of multiple computing graphics cards is still enabled, which cannot realize memory sharing of multiple computing graphics cards as needed, resulting in high energy consumption. Utility Model Content

[0004] To address the technical problems in existing technologies, such as the inability to achieve memory sharing among multiple GPUs as needed, resulting in high energy consumption, this invention provides a multi-GPU memory sharing communication control device based on a memory expansion bus.

[0005] The technical solution of this utility model to solve the above-mentioned technical problems is as follows: A multi-GPU memory sharing communication control device based on a memory expansion bus includes a controller, multiple expansion switch modules, and multiple control switch modules. The multiple expansion switch modules correspond one-to-one with multiple computing graphics cards, and the multiple control switch modules correspond one-to-one with the multiple expansion modules. The signal output terminal of the controller is connected to the control terminals of the multiple expansion switch modules respectively. One end of each expansion switch module is connected to the memory expansion bus, and the other end of each expansion switch module is connected to the corresponding computing graphics card. The signal input terminal of the controller is connected to one end of each of the multiple control switch modules, the CPU of the computing platform is connected to the control terminal of each of the multiple control switch modules, and the other end of each of the multiple control switch modules is connected to a first power supply voltage.

[0006] The beneficial effects of this invention are as follows: Through multiple corresponding expansion switch modules, multiple computing graphics cards, and multiple control switch modules, the CPU of the computing platform controls each control switch module. Each control switch module sends control commands to the controller. Upon receiving the control command from the corresponding control switch module, the controller activates the corresponding expansion switch module, enabling the corresponding computing graphics card to connect to the memory expansion bus and achieving memory sharing communication among the computing graphics cards. This invention can control the number of shared memory resources among multiple computing graphics cards, allowing for control over the number of computing graphics cards sharing memory as needed, thus reducing energy consumption.

[0007] Based on the above technical solution, the present invention can be further improved as follows.

[0008] Furthermore, it also includes multiple extended indicator light modules, each corresponding to one of the multiple extended switch modules; the control terminal of each extended indicator light module is connected to the control terminal of the corresponding extended switch module, one end of each extended indicator light module is connected to the first power supply voltage, and the other end of each extended indicator light module is grounded.

[0009] The advantage of adopting the above-mentioned further solution is that, by setting up an extended indicator light module, it is possible to display whether the connection with the video memory expansion bus is successful.

[0010] Furthermore, it also includes multiple control indicator modules, each corresponding to one of the multiple control switch modules. One end of each control indicator module is connected to one end of the corresponding control switch module, and the other end of each control indicator module is grounded.

[0011] The advantage of adopting the above-mentioned further solution is that by setting multiple control indicator modules, it is possible to display whether the corresponding control switch module is turned on.

[0012] Furthermore, the expansion switch module includes multiple expansion switch groups, each of which includes two bidirectional MOSFET switches. The control terminal of each bidirectional MOSFET switch is connected to the signal output terminal of the controller, one end of each bidirectional MOSFET switch is connected to the video memory expansion bus, and the other end of each bidirectional MOSFET switch is connected to the corresponding computing graphics card.

[0013] Furthermore, the bidirectional MOS transistor switch includes a first enhancement-mode PMOS transistor, a second enhancement-mode PMOS transistor, a first resistor, a second resistor, a third resistor, a first transistor, and a first capacitor; the source of the first enhancement-mode PMOS transistor is connected to the source of the second enhancement-mode PMOS transistor, the drain of the first enhancement-mode PMOS transistor is connected to the memory expansion bus, and the drain of the second enhancement-mode PMOS transistor is connected to the computing graphics card; One end of the second resistor is connected to the gate of the first enhancement-mode PMOS transistor and the gate of the second enhancement-mode PMOS transistor respectively. The other end of the second resistor is connected to the collector of the first transistor. The base of the first transistor is connected to the signal output terminal of the controller. One end of the third resistor is connected to the base of the first transistor. The emitter of the first transistor and the other end of the third resistor are both grounded. One end of the first resistor and one end of the first capacitor are connected to the source of the first enhancement-mode PMOS transistor or the source of the second enhancement-mode PMOS transistor, and the other end of the first resistor and the other end of the first capacitor are connected to one end of the second resistor.

[0014] Furthermore, the extended indicator module includes a second transistor, a fourth resistor, a fifth resistor, and a first light-emitting diode; one end of the fifth resistor is connected to a second power supply voltage, the other end of the fifth resistor is connected to the positive terminal of the first light-emitting diode, the negative terminal of the first light-emitting diode is connected to the collector of the second transistor, the base of the second transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor and the emitter of the second transistor are both grounded; the base of the second transistor is connected to the signal output terminal of the controller.

[0015] Furthermore, the control switch module includes an optocoupler, a sixth resistor, and a third transistor. The positive input terminal and the collector output terminal of the optocoupler are both connected to the first power supply voltage. The negative input terminal of the optocoupler is connected to the collector of the third transistor. The base of the third transistor is connected to the CPU. One end of the sixth resistor is connected to the base of the third transistor. The other end of the sixth resistor and the emitter of the third transistor are both grounded. The emitter output terminal of the optocoupler is connected to the signal output terminal of the controller.

[0016] Furthermore, the control switch module also includes a second capacitor, one end of which is connected to the base of the third transistor, and the other end of which is grounded.

[0017] Furthermore, the control indicator module includes a seventh resistor and a second light-emitting diode. One end of the seventh resistor is connected to the emitter of the output terminal of the optocoupler, and the other end of the seventh resistor is connected to the positive terminal of the second light-emitting diode. The negative terminal of the second light-emitting diode is grounded.

[0018] Furthermore, the controller is a microcontroller or MCU. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the present invention. Figure 1 ; Figure 2 This is a schematic diagram of the structure of the present invention. Figure 2 ; Figure 3 This is a schematic diagram of the expansion switch module; Figure 4 This is a circuit diagram for a bidirectional MOSFET switch. Figure 5 Circuit diagram for expanding the indicator light module; Figure 6 This is a circuit diagram for the control switch module and the control indicator module.

[0020] The attached diagram lists the components represented by each number as follows: 1. Controller, 2. Computing graphics card, 3. Expansion switch module, 4. Control switch module, 5. CPU, 6. Expansion indicator light module, 7. Control indicator light module. Detailed Implementation

[0021] The principles and features of this utility model are described below with reference to the accompanying drawings. The examples given are only for explaining this utility model and are not intended to limit the scope of this utility model.

[0022] like Figure 1 As shown, this embodiment provides a multi-GPU memory sharing communication control device based on a memory expansion bus, including a controller 1, multiple expansion switch modules 3 and multiple control switch modules 4. The multiple expansion switch modules 3 correspond one-to-one with multiple computing graphics cards 2, and the multiple control switch modules 4 correspond one-to-one with the multiple expansion switch modules 3. The signal output terminal of the controller 1 is connected to the control terminal of the multiple expansion switch modules 3 respectively. One end of each expansion switch module 3 is connected to the memory expansion bus, and the other end of each expansion switch module 3 is connected to the corresponding computing graphics card 2. The signal input terminals of the controller 1 are respectively connected to one end of each of the multiple control switch modules 4, and the CPU 5 of the computing platform is respectively connected to the control terminals of the multiple control switch modules 4. The other ends of the multiple control switch modules 4 are connected to a first power supply voltage. The controller 1 is a microcontroller or MCU, and the expansion switch module 3 is an external electrically controlled bidirectional switch module.

[0023] This embodiment of the invention utilizes multiple corresponding expansion switch modules 3, multiple computing graphics cards 2, and multiple control switch modules 4. The CPU 5 of the computing platform controls each control switch module 4, which sends control commands to the controller 1. Upon receiving the control command from the corresponding control switch module 4, the controller 1 activates the corresponding expansion switch module 3, enabling the corresponding computing graphics card 2 to connect to the memory expansion bus and achieve memory sharing communication between the computing graphics cards 2. This invention can control the number of shared memory resources among multiple computing graphics cards 2, allowing for control over the number of computing graphics cards 2 sharing memory as needed, thus reducing energy consumption.

[0024] like Figure 2As shown, it also includes multiple extended indicator light modules 6 and multiple control indicator light modules 7. Each of the extended indicator light modules 6 corresponds one-to-one with one of the extended switch modules 3. The control terminal of each extended indicator light module 6 is connected to the control terminal of the corresponding extended switch module 3. One end of each extended indicator light module 6 is connected to the first power supply voltage, and the other end of each extended indicator light module 6 is grounded. By setting the extended indicator light modules 6, the connection status with the video memory expansion bus can be displayed.

[0025] Each of the multiple control indicator light modules 7 corresponds one-to-one with a multiple control switch module 4. One end of each control indicator light module 7 is connected to one end of the corresponding control switch module 4, and the other end of each control indicator light module 7 is grounded. By setting multiple control indicator light modules 7, it is possible to indicate whether the corresponding control switch module 4 is turned on or off.

[0026] like Figure 3 As shown, the expansion switch module 3 includes multiple expansion switch groups. Each expansion switch group includes two bidirectional MOSFET switches. The control terminal of each bidirectional MOSFET switch is connected to the signal output terminal of the controller 1. One end of each bidirectional MOSFET switch is connected to the video memory expansion bus, and the other end of each bidirectional MOSFET switch is connected to the corresponding computing graphics card 2. The video memory expansion bus is used to expand the memory of the computing graphics card 2. Multiple channels can be used for expansion. Figure 3 Taking the 2-channel expansion as an example, each expansion switch module 3 includes 2 expansion switch groups, and each expansion switch group includes 2 channels, namely the transmit (TX) channel and the receive (TR) channel. Each channel is equipped with a bidirectional MOSFET switch to realize the switching of each channel. Moreover, the bidirectional MOSFET switches of the same computing power graphics card are controlled by the control signal output by the same controller, so that the bidirectional MOSFET switches of the same computing power graphics card can be turned on or off together, ultimately realizing the switching of the memory shared channel of the entire computing power graphics card.

[0027] like Figure 4 As shown, in some embodiments, the bidirectional MOS transistor switch includes a first enhancement-mode PMOS transistor Q1, a second enhancement-mode PMOS transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q3, and a first capacitor C1; the source of the first enhancement-mode PMOS transistor Q1 is connected to the source of the second enhancement-mode PMOS transistor Q2, the drain of the first enhancement-mode PMOS transistor Q1 is connected to the memory expansion bus, and the drain of the second enhancement-mode PMOS transistor Q2 is connected to the computing graphics card 2.

[0028] One end of the second resistor R2 is connected to the gate of the first enhancement-mode PMOS transistor Q1 and the gate of the second enhancement-mode PMOS transistor Q2, respectively. The other end of the second resistor R2 is connected to the collector of the first transistor Q3. The base of the first transistor Q3 is connected to the signal output terminal of the controller 1. One end of the third resistor R3 is connected to the base of the first transistor Q3. The emitter of the first transistor Q3 and the other end of the third resistor R3 are both grounded.

[0029] One end of the first resistor R1 and one end of the first capacitor C1 are connected to the source of the first enhancement-mode PMOS transistor Q1 or the source of the second enhancement-mode PMOS transistor Q2, and the other end of the first resistor R1 and the other end of the first capacitor C1 are connected to one end of the second resistor R2.

[0030] In this embodiment, since the memory expansion bus and the graphics card are connected by two back-to-back series-connected strong-type PMOS transistors, a bidirectional current switching is realized. When the control signal output by the controller is a high-level control signal, the first transistor Q3 is turned on, and the first enhanced-type PMOS transistor Q1 and the second enhanced-type PMOS transistor Q2 are both turned on, realizing the memory expansion sharing of the graphics card 2. When the control signal output by the controller is a low-level control signal, the first transistor Q3 is turned off, and the first enhanced-type PMOS transistor Q1 and the second enhanced-type PMOS transistor Q2 are both turned off, physically stopping the memory expansion sharing of the graphics card 2.

[0031] like Figure 5 As shown, the extended indicator module 6 includes a second transistor Q4, a fourth resistor R4, a fifth resistor R5, and a first light-emitting diode D1; one end of the fifth resistor R5 is connected to a second power supply voltage, the other end of the fifth resistor R5 is connected to the positive terminal of the first light-emitting diode D1, the negative terminal of the first light-emitting diode D1 is connected to the collector of the second transistor Q4, the base of the second transistor Q4 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 and the emitter of the second transistor Q4 are both grounded; the base of the second transistor Q4 is connected to the signal output terminal of the controller 1.

[0032] When the controller outputs a high-level control signal, the second transistor Q4 conducts, and the first LED D1 lights up; when the controller outputs a low-level control signal, the second transistor Q4 is cut off, and the first LED D1 is off. This ensures that when the graphics card is connected to the memory expansion bus, the first LED D1 lights up; when the graphics card is disconnected from the memory expansion bus, the first LED D1 turns off.

[0033] like Figure 6As shown, the control switch module 4 includes an optocoupler U1, a second capacitor C2, a sixth resistor R6, and a third transistor Q5. The positive input terminal and the collector output terminal of the optocoupler U1 are both connected to the first power supply voltage. The negative input terminal of the optocoupler U1 is connected to the collector of the third transistor Q5. The base of the third transistor Q5 is connected to the CPU 5. One end of the sixth resistor R6 is connected to the base of the third transistor Q5. The other end of the sixth resistor R6 and the emitter of the third transistor Q5 are both grounded. The emitter output terminal of the optocoupler U1 is connected to the signal output terminal of the controller 1.

[0034] When CPU5 outputs a high-level control signal, the third transistor Q5 is turned on, the optocoupler U1 is turned on, and the signal input terminal of controller 1 is connected to the first power supply voltage of 3.3V. After receiving the 3.3V high-level signal, controller 1 outputs a high-level control signal to control the corresponding extended switch module 3 to turn on.

[0035] One end of the second capacitor C2 is connected to the base of the third transistor Q5, and the other end of the second capacitor C2 is grounded. By setting the second capacitor C2, the alternating voltage signal output by the CPU5 can be filtered to prevent the alternating voltage signal from affecting the control of the third transistor Q5.

[0036] The control indicator module 7 includes a seventh resistor R7 and a second light-emitting diode D2. One end of the seventh resistor R7 is connected to the emitter of the output terminal of the optocoupler U1, and the other end of the seventh resistor R7 is connected to the positive terminal of the second light-emitting diode D2. The negative terminal of the second light-emitting diode D2 is grounded. When the optocoupler U1 is turned on, a voltage of 3.3V is applied to one end of the seventh resistor R7, and the second light-emitting diode D2 is powered on and lit. For easy differentiation, the first light-emitting diode D1 and the second light-emitting diode D2 can be set to different colors.

[0037] It should be noted that in this invention, the connection is mainly made by electrical connection through wires or conductors; it is common knowledge that microcontrollers or MCUs output high and low levels according to the input high and low levels, therefore, this invention does not improve the computer program.

[0038] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the concept and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A multi-GPU memory sharing communication control device based on a memory expansion bus, characterized in that: It includes a controller (1), multiple expansion switch modules (3) and multiple control switch modules (4). The multiple expansion switch modules (3) correspond one-to-one with multiple computing graphics cards (2), and the multiple control switch modules (4) correspond one-to-one with multiple expansion switch modules (3). The signal output terminal of the controller (1) is connected to the control terminal of the multiple expansion switch modules (3). One end of each expansion switch module (3) is connected to the video memory expansion bus, and the other end of each expansion switch module (3) is connected to the corresponding computing graphics card (2). The signal input terminal of the controller (1) is connected to one end of one of the multiple control switch modules (4), the CPU (5) of the computing platform is connected to the control terminal of one of the multiple control switch modules (4), and the other end of the multiple control switch modules (4) is connected to the first power supply voltage.

2. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 1, characterized in that: It also includes multiple extended indicator light modules (6), each of which corresponds to one of the multiple extended switch modules (3); the control terminal of each extended indicator light module (6) is connected to the control terminal of the corresponding extended switch module (3), one end of each extended indicator light module (6) is connected to the first power supply voltage, and the other end of each extended indicator light module (6) is grounded.

3. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 2, characterized in that: It also includes multiple control indicator modules (7), each of which corresponds to a multiple control switch module (4). One end of each control indicator module (7) is connected to one end of the corresponding control switch module (4), and the other end of each control indicator module (7) is grounded.

4. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 3, characterized in that: The expansion switch module (3) includes multiple expansion switch groups. Each expansion switch group includes two bidirectional MOS transistor switches. The control terminal of each bidirectional MOS transistor switch is connected to the signal output terminal of the controller (1). One end of each bidirectional MOS transistor switch is connected to the video memory expansion bus, and the other end of each bidirectional MOS transistor switch is connected to the corresponding computing power graphics card (2).

5. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 4, characterized in that: The bidirectional MOS transistor switch includes a first enhancement-mode PMOS transistor (Q1), a second enhancement-mode PMOS transistor (Q2), a first resistor (R1), a second resistor (R2), a third resistor (R3), a first transistor (Q3), and a first capacitor (C1); the source of the first enhancement-mode PMOS transistor (Q1) is connected to the source of the second enhancement-mode PMOS transistor (Q2), the drain of the first enhancement-mode PMOS transistor (Q1) is connected to the memory expansion bus, and the drain of the second enhancement-mode PMOS transistor (Q2) is connected to the computing graphics card (2); One end of the second resistor (R2) is connected to the gate of the first enhancement-mode PMOS transistor (Q1) and the gate of the second enhancement-mode PMOS transistor (Q2), respectively. The other end of the second resistor (R2) is connected to the collector of the first transistor (Q3). The base of the first transistor (Q3) is connected to the signal output terminal of the controller (1). One end of the third resistor (R3) is connected to the base of the first transistor (Q3). The emitter of the first transistor (Q3) and the other end of the third resistor (R3) are both grounded. One end of the first resistor (R1) and one end of the first capacitor (C1) are connected to the source of the first enhancement-mode PMOS transistor (Q1) or the source of the second enhancement-mode PMOS transistor (Q2), and the other end of the first resistor (R1) and the other end of the first capacitor (C1) are connected to one end of the second resistor (R2).

6. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 3, characterized in that: The extended indicator module (6) includes a second transistor (Q4), a fourth resistor (R4), a fifth resistor (R5), and a first light-emitting diode (D1); one end of the fifth resistor (R5) is connected to a second power supply voltage, the other end of the fifth resistor (R5) is connected to the positive terminal of the first light-emitting diode (D1), the negative terminal of the first light-emitting diode (D1) is connected to the collector of the second transistor (Q4), the base of the second transistor (Q4) is connected to one end of the fourth resistor (R4), and the other end of the fourth resistor (R4) and the emitter of the second transistor (Q4) are both grounded; the base of the second transistor (Q4) is connected to the signal output terminal of the controller (1).

7. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 3, characterized in that: The control switch module (4) includes an optocoupler (U1), a sixth resistor (R6), and a third transistor (Q5). The positive input terminal and the collector output terminal of the optocoupler (U1) are both connected to the first power supply voltage. The negative input terminal of the optocoupler (U1) is connected to the collector of the third transistor (Q5). The base of the third transistor (Q5) is connected to the CPU (5). One end of the sixth resistor (R6) is connected to the base of the third transistor (Q5). The other end of the sixth resistor (R6) and the emitter of the third transistor (Q5) are both grounded. The emitter output terminal of the optocoupler (U1) is connected to the signal output terminal of the controller (1).

8. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 7, characterized in that: The control switch module (4) further includes a second capacitor (C2), one end of which is connected to the base of the third transistor (Q5), and the other end of which is grounded.

9. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 7, characterized in that: The control indicator module (7) includes a seventh resistor (R7) and a second light-emitting diode (D2). One end of the seventh resistor (R7) is connected to the emitter of the output terminal of the optocoupler (U1), and the other end of the seventh resistor (R7) is connected to the positive terminal of the second light-emitting diode (D2). The negative terminal of the second light-emitting diode (D2) is grounded.

10. The multi-GPU memory sharing communication control device based on a memory expansion bus according to claim 1, characterized in that: The controller (1) is a single-chip microcomputer or MCU.

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