A display device

Abstract

The display device provided by the present disclosure relates to the technical field of display and comprises at least one display module and a plurality of receiving cards connected in cascade, wherein the receiving cards are connected with the display module. Each receiving card comprises two interfaces, at least two receiving cards are connected through the interfaces, the physical positions of the two receiving cards connected with each other are adjacent, each interface comprises a plurality of pins, and the pins comprise sending pins and receiving pins. Thus, each interface can realize bidirectional transmission, and is no longer limited by the connection of unidirectional interfaces in the related art. When two receiving cards are connected through the interfaces, one of the receiving cards can be connected with another receiving card adjacent thereto, so that long-distance wiring can be avoided, installation is facilitated, and signal quality is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display device. Background Technology

[0002] In today's increasingly popular LED display technology, LED all-in-one displays are widely used in various scenarios such as conferences, exhibitions, and command centers due to their advantages such as seamless splicing, high brightness, and high contrast. These displays are typically composed of multiple cabinets spliced ​​together to form a large display device. In order to drive and control these numerous cabinets, LED controllers need to effectively cascade them to achieve data transmission and command issuance.

[0003] Currently, the mainstream method for cascading receiver cards in the industry involves data output from a central controller, then transmitted via cabling to the signal input interface of a receiver card in one cabinet, and then transmitted through the signal output interface of that receiver card to the signal input interface of the next receiver card in the next cabinet, and so on, to achieve cascading of receiver cards in various cabinets. Because the design of the signal input interfaces of each receiver card is standardized, and the orientation of the interfaces on the receiver cards in each cabinet is also standardized, once the receiver cards in a row of cabinets are cascaded, the cabling needs to run in a large S-shape and undergo multiple bends, running from the top cabinet in one row to the bottom cabinet in the next row, resulting in a long cabling distance. This long-distance cabling and multiple bends lead to inconvenient installation and poor signal quality. Utility Model Content

[0004] To address the aforementioned technical problems, this disclosure provides a display device that avoids long-distance wiring, simplifies installation, and ensures signal quality.

[0005] This disclosure provides a display device, including at least one display module, and further including: a plurality of cascaded receiving cards, the receiving cards being connected to the display module;

[0006] Each of the receiving cards includes two interfaces, and at least two of the receiving cards are connected through the interfaces; the two connected receiving cards are physically adjacent to each other; each of the interfaces includes multiple pins, including transmit pins and receive pins.

[0007] Optionally, in the same interface, the number of transmitting pins is the same as the number of receiving pins.

[0008] Optionally, in the same interface, the transmitting pin and the receiving pin are centrally symmetrically distributed.

[0009] Optionally, the number of transmit pins may differ from the number of receive pins within the same interface.

[0010] Optionally, the interface includes a first region and a second region arranged along its length, with the transmitting pin located in the first region and the receiving pin located in the second region.

[0011] Optionally, the receive pins in the second region are arranged symmetrically with the transmit pins in the first region.

[0012] Optionally, the first region includes a first sub-region and a second sub-region, and the transmitting pin includes a plurality of transmitting pin groups, the transmitting pin groups including a data signal transmitting pin group located in the first sub-region and a clock signal transmitting pin group located in the second sub-region.

[0013] Optionally, the first region further includes a third sub-region, and the transmitting pin includes a detection signal transmitting pin located in the third sub-region.

[0014] Optionally, the second sub-region is adjacent to the second region, and the first sub-region is located between the second sub-region and the third sub-region.

[0015] Optionally, the second region includes a fourth sub-region and a fifth sub-region, and the receiving pin includes a plurality of receiving pin groups, the receiving pin groups including a data signal receiving pin group located in the fourth sub-region and a clock signal receiving pin group located in the fifth sub-region.

[0016] Optionally, the second region includes a sixth sub-region, and the receiving pin includes a detection signal receiving pin located in the sixth sub-region.

[0017] Optionally, the fifth sub-region is adjacent to the first region, and the fourth sub-region is located between the fifth sub-region and the sixth sub-region.

[0018] Optionally, the interface includes a first region and a second region arranged along its length, with at least a portion of the transmitting pins and at least a portion of the receiving pins located in the first region, and at least a portion of the transmitting pins and at least a portion of the receiving pins located in the second region.

[0019] Optionally, the receive pins in the second region are arranged symmetrically with the transmit pins in the first region, and the transmit pins in the second region are arranged symmetrically with the receive pins in the first region.

[0020] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0021] In the display device provided in this disclosure, both interfaces of the receiving card are bidirectional transmission interfaces, including both transmitting and receiving pins, enabling bidirectional signal transmission. Therefore, it is no longer limited by the unidirectional interface connection restrictions of related technologies, and the two receiving cards can be connected nearby through the bidirectional interface. In this disclosure, when connecting two receiving cards through the interface, one receiving card can connect to the adjacent receiving card. For example, in two adjacent columns of receiving cards, the bottom receiving card in one column can connect to the adjacent receiving card in the same row (i.e., the bottom receiving card in the other column), without needing to route the cable to the top of the other column to connect to the top receiving card. Therefore, by setting the interface as a bidirectional interface, the physically adjacent positions of the connected receiving cards can be ensured, greatly reducing or eliminating the need for long-distance, tortuous cables, large S-bends, and multiple sharp bends. This effectively shortens the length of the cabling between the two connected receiving cards, and the shorter, straighter wiring path simplifies the installation process, eliminating the need for installers to laboriously lay long cables or make multiple bends in confined spaces. Because the ribbon cable is shorter and has fewer bends, there will be less signal attenuation and interference, resulting in better signal quality and more stable display output. Furthermore, the reduced number of bends and shorter length of the ribbon cable lowers the stress on it, which also helps improve the overall reliability and lifespan of the display device. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 The diagram shown is a schematic diagram of a receiving card connection in the housing of a display device in related technologies;

[0025] Figure 2 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure;

[0026] Figure 3 The diagram shown is a connection schematic of a receiving card in a display device provided in an embodiment of this disclosure;

[0027] Figure 4 The diagram shown is a pin layout diagram of an interface in a receiver card provided in an embodiment of this disclosure;

[0028] Figure 5 The diagram shows a pin layout of two interfaces in the same receiver card. Detailed Implementation

[0029] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0030] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0031] Figure 1 The diagram shows a connection schematic of the receiver cards 90 in the housing of a display device in related technology. Each receiver card 90 has a transmitting interface TX0 and a receiving interface RX0, and the arrangement of the receiver cards is consistent. For example, the transmitting interface TX0 of each receiver card 90 is located on the first side of the receiver card, and the receiving interface RX0 is located on the second side of the receiver card. Assuming there are six receiver cards, namely S1 to S6, in the first row of receiver cards 90 connected to the transmitting card 80, the transmitting interface TX0 of the first receiver card S1 is connected to the receiving interface RX0 of the second receiver card S2, and the transmitting interface TX0 of the last receiver card S2 in the first row is connected to the receiving interface RX0 of the first receiver card S3 in the second row. When connecting the last receiver card S2 in the first row to the first receiver card S3 in the second row, and when connecting the last receiver card S4 in the second row to the first receiver card S5 in the third row, the ribbon cable needs to take a large S-bend, and one ribbon cable needs to go through 4 bends, resulting in a long cable distance. Long-distance cabling with multiple bends can lead to problems such as inconvenient installation and poor signal quality.

[0032] Based on this, the present disclosure provides a display device 100, Figure 2 The diagram shown is a structural schematic of a display device 100 provided in an embodiment of this disclosure. Figure 3 The diagram shown is a connection schematic of the receiving card 00 in the display device provided in this embodiment of the present disclosure. Please refer to it. Figure 2 and Figure 3 The display device 100 provided in this embodiment includes at least one display module 10 and a plurality of cascaded receiver cards 00, wherein the receiver cards 00 are connected to the display module 10. It should be noted that... Figure 2 and Figure 3The number and arrangement of the display modules 10 and receiver cards 00 shown in the illustration are for illustrative purposes only. This disclosure does not limit the actual number of display modules 10 and receiver cards 00 included in the display device 100. This embodiment uses one receiver card 00 corresponding to four display modules 10 as an example for explanation, but it is not limited to this. The correspondence between the number of receiver cards 00 and display modules 10 can be flexibly adjusted according to the actual situation.

[0033] Please continue to refer to this. Figure 3 Each receiver card 00 includes two interfaces, namely interface U1 and U2, and at least two receiver cards 00 are connected through the interfaces; the two connected receiver cards 00 are physically adjacent; each interface in the receiver card 00 includes multiple pins, including a transmit pin TX and a receive pin RX.

[0034] In practical applications, interfaces U1 and U2 are, for example, Low-Voltage Differential Signaling (LVDS) interfaces.

[0035] The connection relationship between receiver cards 00 can be represented, for example, by connecting one interface of the (N+1)th level receiver card 00 to one interface of the Nth level receiver card 00, and connecting the other interface of the (N+1)th level receiver card 00 to one interface of the (N+2)th level receiver card 00, where N ≥ 1 and N is an integer. Optionally, the two connected receiver cards 00 are physically adjacent. It should be noted that physical adjacency of two receiver cards 00 means that there are no other receiver cards 00 between the two connected receiver cards along the row or column direction, and the ribbon cable does not need to cross other receiver cards when connecting two receiver cards. Optionally, in the two connected interfaces (for example, in two adjacent and connected receiver cards, interface U1 of one receiver card is connected to interface U2 of another receiver card), the transmit pin TX of one receiver card's interface is connected to the receive pin RX of the other receiver card's interface.

[0036] In practical applications, one interface of the first-level receiver card 00 is connected to the interface of the transmitter card 30, enabling data exchange between them. It should be noted that the interface on the transmitter card 30 matches the interface on the receiver card 00, both including transmit and receive pins.

[0037] In the display device 100 provided in this embodiment, both interfaces of the receiving card 00 are bidirectional transmission interfaces, including both a transmit pin TX and a receive pin RX, enabling bidirectional signal transmission. Therefore, it is no longer limited by the connection restrictions of unidirectional interfaces in related technologies, and two receiving cards 00 can be connected nearby through the bidirectional interface. Optionally, the receiving cards 00 are connected via a ribbon cable 20. In this embodiment, when two receiving cards 00 are connected through the interface, one receiving card 00 can be connected to the other adjacent receiving card 00 nearby. For example, in two adjacent columns of receiving cards 00, the bottom receiving card 00 in one column can be connected to the next adjacent receiving card 00 located in the same row (i.e., the bottom receiving card 00 in the other column), without needing to wind the cable to the top of the other column to connect to the top receiving card 00; the ribbon cable only needs to be bent twice. Therefore, by setting the interface to a bidirectional interface, the physical locations of the interconnected receiver cards 00 can be ensured to be adjacent, greatly reducing or eliminating the need for long-distance, tortuous cables, large S-bends, and multiple sharp bends. This effectively shortens the length of the ribbon cable 20 between the two interconnected receiver cards 00. The shorter, straighter wiring path simplifies the installation process, eliminating the need for installers to laboriously lay long cables or make multiple bends in confined spaces. Because the ribbon cable 20 is shorter and has fewer bends, signal attenuation and interference are also reduced, resulting in better signal quality and more stable display output. Furthermore, the reduced number of bends and shorter length of the ribbon cable 20 lowers the stress on it, which also helps improve the overall reliability and lifespan of the display device.

[0038] Figure 4 The diagram shown is a pin layout of an interface in a receiver card 00 provided in this embodiment of the present disclosure. Pins marked with TX are transmit pins (TX), and pins marked with RX are receive pins (RX). Please refer to... Figure 3 and Figure 4 In one optional embodiment of this disclosure, the number of transmit pins (TX) and the number of receive pins (RX) are the same in the same interface.

[0039] When the number of transmit pins (TX) and receive pins (RX) in the same interface is equal, the interface possesses symmetrical uplink and downlink transmission capabilities. This allows data to be transmitted in both directions with the same bandwidth, i.e., equal uplink and downlink bandwidth. Uplink bandwidth, for example, refers to the bandwidth by which the current receiving card 00 transmits data to the next-level or more cascaded receiving card 00, while downlink bandwidth, for example, refers to the bandwidth by which it receives data from the previous-level receiving card 00. If the uplink and downlink bandwidths of the interface are mismatched, for example, if the number of transmit pins is less than the number of receive pins, then the uplink transmission capability may become a bottleneck, limiting the efficiency of certain functions (such as diagnostic data return, control signal uploading, etc.). This embodiment of the disclosure avoids uplink and downlink bandwidth imbalance by setting the number of transmit pins (TX) and receive pins (RX) to be equal, enabling data flow to move more efficiently in both directions.

[0040] Furthermore, having the same number of transmit and receive pins simplifies the internal signal processing logic of the interface. Designers can adopt a more unified circuit design, ensuring that both data transmission and reception follow similar paths and processing flows. No additional adapter or conversion circuitry is needed to accommodate differences in the number of pins in different directions. On the PCB layout, an equal number of transmit and receive pins facilitates more regular routing, reducing signal crosstalk and thus improving signal integrity.

[0041] Furthermore, the pin configuration with the same number of transmit and receive pins provides an ideal foundation for full-duplex communication. Full-duplex communication allows data to be transmitted simultaneously in both directions without waiting for the other side to complete its transmission. In this case, the display module can provide real-time feedback on its operating status and fault information to the main control device without affecting normal display data transmission. Moreover, users can simultaneously send control commands and receive device feedback, improving the efficiency of remote operation and facilitating remote diagnostics and control.

[0042] Please continue to refer to this. Figure 4 Optionally, within the same interface, the transmit pin TX and receive pin RX are centrally symmetrically distributed. For example, Figure 4Pins 5 (TX_DATA4_N) and 6 (TX_DATA4_P) are centrally symmetrically arranged with pins 47 (RX_DATA4_N) and 46 (RX_DATA4_P), respectively. This central symmetry means that regardless of the cable's orientation (correct or incorrect insertion, rotated 180 degrees) when connected to the interface, the physical position of the transmit pin (TX) and receive pin (RX) relative to the wires on the cable remains consistent. In traditional asymmetrical designs, the cable must be inserted strictly in a specific orientation; otherwise, the transmit and receive pins will be misaligned, leading to signal transmission failure. Central symmetry eliminates this limitation, eliminating the need for installers to spend time identifying the correct orientation of the cable or interface, allowing for plug-and-play functionality and significantly improving installation efficiency. The flexibility of the interface orientation reduces the risk of device malfunction or potential damage due to incorrect cable insertion, improving system reliability. Furthermore, this interface design makes the cable and interface more universal, reducing the complexity of spare parts management and production.

[0043] Figure 5 The diagram shown illustrates a pin layout for interfaces U1 and U2 within the same receiver card 00. Please refer to the diagram. Figure 5 In one optional embodiment of this disclosure, the pins of the two interfaces U1 and U2 in the same receiver card 00 are centrally symmetrically distributed. For example... Figure 5 The pin numbered 1 in interface U1 corresponds to pin number 51 in interface U2, and pin number 2 in interface U1 corresponds to pin number 50 in interface U2. The sum of the pin numbers for these two corresponding pins is equal, both being 52. This centrally symmetrical pin distribution makes the wiring on the PCB (printed circuit board) corresponding to the receiver card 00 more regular and efficient. Designers can replicate the wiring of the other interface by mirroring or rotating it, greatly reducing the time and complexity of manual wiring. Utilizing this symmetry, the circuitry of one interface can be laid out by mirroring or rotating it, and then directly copied to the other symmetrical interface. This not only accelerates the design process but also reduces the possibility of design errors. Since the circuit paths and electrical characteristics of the two interfaces may be very similar, this also helps to achieve more consistent signal transmission performance. Moreover, the centrally symmetrical pin distribution design means that only one type of connector (e.g., an interface on a ribbon cable) needs to be designed and manufactured in practical applications. Regardless of which symmetrical interface on the receiver card 00 the connector is used for, its pins can correspond to that interface, thus greatly reducing the types of connectors and simplifying procurement and material management. When cascading receiver cards 00 using ribbon cable 20, there is no need to distinguish between two different interface orientations or models, thus effectively improving production efficiency and reducing operational errors. For manual installation, it reduces errors caused by interface type confusion and simplifies training.

[0044] Please refer to the following: Figure 4 In one optional embodiment of this disclosure, the interface includes a first region Q1 and a second region Q2 arranged along its length, with the transmit pin TX located in the first region Q1 and the receive pin RX located in the second region Q2.

[0045] This embodiment provides a scheme in which the transmit pins (TX) are concentrated in a first region Q1, and the receive pins (RX) are concentrated in a second region Q2. This regional arrangement of transmit and receive pins effectively isolates them physically. Transmitted signals typically have high power and can easily cause crosstalk to nearby received signals. By partitioning the region, the physical distance between the transmit and receive pins can be maximized, thereby effectively reducing electromagnetic interference. This is particularly important for high-speed signal transmission, helping to maintain signal integrity and stability.

[0046] Furthermore, partitioning the transmit and receive pins allows for more intuitive PCB routing based on their functional areas. Transmit signals can be routed in one direction, while receive signals can be routed in another, preventing signal lines from becoming tangled or crossing on the PCB. Moreover, the orderly pin arrangement helps automated routing tools complete tasks more efficiently, reducing the need for manual adjustments and optimizations. When signal problems occur, maintenance personnel can quickly pinpoint the source of the problem based on the pin's functional area. For example, if a display problem occurs, the pin connections in the receive area can be checked first; if data transmission fails, the transmit area should be investigated. This partitioning makes fault diagnosis more efficient.

[0047] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the first region Q1 and the second region Q2 are isolated by at least one ground pin. Figure 4 This embodiment illustrates a scheme where the first region Q1 and the second region Q2 are isolated using three ground pins, but the number of ground pins is not limited. The ground pins form a physical "barrier" between the transmitting and receiving signal regions. High-speed signals on the transmitting pins may generate varying electromagnetic fields, which can couple to adjacent receiving pins, causing crosstalk. As a low-impedance path, the ground pins absorb and dissipate this coupling energy, significantly reducing interference from the transmitting end to the receiving end. The isolation provided by the ground pins is particularly critical for high-frequency signals, effectively preventing transmitted data from "leaking" into the receiving channel and ensuring signal purity. Furthermore, the ground pins provide a stable reference potential, helping to suppress the propagation of common-mode noise between the transmitting and receiving regions, further improving the signal's anti-interference capability.

[0048] Please continue to refer to this. Figure 4When the transmitting pins are concentrated in the first region Q1 and the receiving pins are concentrated in the second region Q2, in one optional embodiment of this disclosure, the receiving pins in the second region Q2 are symmetrically arranged with the transmitting pins in the first region Q1. This symmetry makes PCB routing extremely efficient. Designers can design a routing pattern for the transmitting pins in the first region Q1 and then directly mirror or rotate it to the receiving pins in the second region Q2, thereby greatly reducing routing time and complexity and lowering the possibility of human error. Symmetrical layout helps create shorter, more direct signal paths, reducing unnecessary bends and crossings, thereby reducing signal loss and crosstalk. Moreover, symmetrical pin layout in the same interface helps design and maintain a uniform characteristic impedance of the interface. Whether it is the transmitting or receiving path, the electrical environment of signal transmission tends to be consistent, which helps reduce signal reflection and ensures efficient signal energy transmission.

[0049] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the first region Q1 includes a first sub-region Q11 and a second sub-region Q12. The transmit pins include a plurality of transmit pin groups Z0, wherein the transmit pin groups Z0 include a data signal transmit pin group Z1 located in the first sub-region Q11 and a clock signal transmit pin group Z2 located in the second sub-region Q12. Optionally, adjacent transmit pin groups Z0 are isolated from each other by at least one ground pin.

[0050] This embodiment further illustrates the layout of the transmit pin groups in the interface. Data signal transmit pin group Z1 is used to transmit data signals, and clock signal transmit pin group Z2 is used to transmit clock signals. Data signals and clock signals are the two most critical and easily interfered-with signals in digital circuits. By centrally configuring them in separate regions (first sub-region Q11 and second sub-region Q12) and using grounding pins for physical and electrical isolation, interference from data signals to clock signals, and vice versa, can be minimized, thus ensuring the accuracy of data signal transmission and the stability of clock signals. Furthermore, partitioning the data signal transmit pin group Z1 and the clock signal transmit pin group Z2 allows maintenance personnel to quickly determine whether the problem lies in the data transmission path or the clock signal path when display abnormalities occur, such as screen flickering or data errors, based on the signal type partition, thereby accelerating the troubleshooting and repair process.

[0051] In this embodiment, adjacent data signal transmission pin groups Z1 are also isolated by ground pins. Data signal transmission pin groups Z1 typically contain multiple pairs of data lines (such as RGB channel data), each pair carrying a rapidly changing signal. The ground pins between adjacent data signal transmission pin groups Z1 effectively create physical and electrical isolation barriers between each data "sub-channel." As a low-impedance path, the ground pins effectively absorb and dissipate the electromagnetic coupling energy generated between adjacent data signal groups. This significantly reduces crosstalk between data lines. Consequently, each data signal can be transmitted in a cleaner, less distorted form, directly improving the accuracy and reliability of data transmission. When differential transmission (such as LVDS) is used, the ground pins help to better isolate different differential pairs, maintain tight coupling within the differential pair, and reduce coupling with other differential pairs, thereby improving the noise immunity and common-mode rejection ratio of the differential signal.

[0052] In this embodiment, adjacent clock signal transmission pin groups Z2 are also isolated by ground pins. The clock signal is the "heart" of digital circuits, synchronizing all data transmission and operations. Any distortion, jitter, or offset in the clock signal can lead to data errors, abnormal display, or even complete system failure. Multiple clock signals may exist in an interface (e.g., clocks for different data channels or different display modes). Introducing ground pins between adjacent clock signal transmission pin groups effectively suppresses electromagnetic coupling and crosstalk between them. This means that the activity of one clock signal transmission pin group will not interfere with another, ensuring that the waveform of each clock signal is as pure and stable as possible. The ground pin provides a stable reference potential and an effective noise absorption path. This helps reduce common-mode noise and random jitter in the clock signal, ensuring the accuracy of the clock edge and thus providing a stable time base for data sampling.

[0053] It should be noted that the embodiments disclosed herein are only illustrated by an interface that includes 5 data signal transmission pin groups Z1 (TX_DATA0_N / P, TX_DATA1_N / P, TX_DATA2_N / P, TX_DATA3_N / P, and TX_DATA4_N / P respectively) and 2 clock signal transmission pin groups Z2 (TX_CLK0_N / P and TX_CLK1_N / P respectively), but are not limited thereto. The number of data signal transmission pin groups and clock signal transmission pin groups can be flexibly set according to the actual situation.

[0054] Please continue to refer to this. Figure 4In one optional embodiment of this disclosure, the first region Q1 further includes a third sub-region Q13, and the transmitting pin includes a detection signal transmitting pin TX_DET, which is located in the third sub-region Q13. Optionally, the detection signal mentioned in this embodiment is, for example, a plug-in / plug-out detection signal. The plug-in / plug-out detection signal allows the display device (or its main control device) to sense the connection status of the display module in real time. When the module is inserted or removed, this signal changes immediately, thereby triggering the corresponding system action. In this way, the system can automatically detect the newly inserted display module and start communication without the user having to manually refresh or restart. When the module is removed, the system can quickly stop data transmission to avoid invalid transmission, and may even trigger power management strategies to reduce power consumption.

[0055] When a detection signal transmission pin TX_DET is introduced into the interface, it can be isolated from other pins (such as data or clock) via a ground pin. Although the insertion / removal detection signal itself is low-speed, its level change can be relatively drastic when insertion / removal occurs, and the instantaneous level jump will generate some transient noise. Isolation via a ground pin can effectively prevent this transient noise from coupling to adjacent high-speed data or clock pins, avoiding interference with critical signals. Conversely, high-speed data and clock signals may also affect the insertion / removal detection signal through crosstalk, leading to false triggering or unstable detection. Ground isolation provides a "noise barrier" for the insertion / removal detection pin, ensuring the accuracy and stability of the detection signal and avoiding system errors caused by misjudging the insertion / removal status.

[0056] Please continue to refer to this. Figure 3 In one optional embodiment of this disclosure, the second sub-region Q12 is adjacent to the second sub-region Q2, and the first sub-region Q11 is located between the second sub-region Q12 and the third sub-region Q13. Thus, in the same interface, it is equivalent to placing the detection signal transmission pin TX_DET at the outermost edge of the interface, the clock signal transmission pin group Z2 in the middle region of the interface, and the data signal transmission pin group Z1 between the detection signal transmission pin TX_DET and the clock signal transmission pin group Z2. The clock signal is the "pulse" of the high-speed digital interface, and its purity and stability are crucial for the synchronization and data sampling of the entire system. Placing the second sub-region Q12, where the clock signal transmission pin group is located, in the middle of the interface allows it to be surrounded and protected by surrounding data signals and ground pins to the greatest extent, reducing electromagnetic interference from the outside. Moreover, the central position of the interface provides the shortest and most balanced signal path to the receiving end (or processor), helping to reduce clock signal attenuation, jitter, and phase shift, ensuring that its waveform remains in optimal condition during transmission.

[0057] Furthermore, by placing the data signal transmission pin group Z1 between the detection signal transmission pin TX_DET and the clock signal transmission pin group Z2, the data signal is surrounded by a high-priority clock signal, which is typically ground-isolated, and a relatively low-speed detection signal. The data signal transmission pin group Z1 also benefits from isolation from both the clock and detection regions, effectively reducing crosstalk between them.

[0058] In this disclosure, the third sub-region Q13 where the detection signal transmission pin is located is located at the outermost edge of the interface. Since the detection signal is usually low-speed, placing it on the outer edge and separating it from the internal high-speed signal can effectively prevent its transient changes (such as the moment of plugging and unplugging) from interfering with the core high-speed signal.

[0059] In this embodiment, the layered layout of the second sub-region Q12, the first sub-region Q11, and the third sub-region Q13, combined with the previously mentioned grounding isolation, physically creates multiple layers of "protection bands." By effectively separating signals of different types, sensitivities, or operating frequencies, crosstalk (including crosstalk between data-clock, data-data, and clock-clock) and common-mode noise within the interface is greatly reduced.

[0060] It should be noted that the relative positional relationship of the first sub-region Q11, the second sub-region Q12, and the third sub-region Q13 provided in this embodiment is only for illustration. In practical applications, the positions of the three regions can be flexibly set according to other requirements.

[0061] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the second region Q2 includes a fourth sub-region Q24 and a fifth sub-region Q25. The receiving pins include multiple receiving pin groups Z3, each containing a data signal receiving pin group Z4 located in the fourth sub-region Q24 and a clock signal receiving pin group Z5 located in the fifth sub-region Q25. Adjacent receiving pin groups Z3 are isolated from each other by at least one ground pin. The data signal receiving pin group Z4 of the fourth sub-region Q24 corresponds to the data signal transmitting pin group Z1 of the first sub-region Q11, and the clock signal receiving pin group Z5 of the fifth sub-region Q25 corresponds to the clock signal transmitting pin group Z2 of the second sub-region Q12. If differential transmission is used for the data and clock signals, this precise correspondence ensures that the differential pairs at the transmitting and receiving ends are perfectly matched, thereby maximizing the common-mode rejection ratio and noise immunity of the differential signal and ensuring that the signal maintains its inherent purity during high-speed transmission.

[0062] Data signals and clock signals are the two most critical and easily interfered-with signals in digital circuits. By centrally configuring the data signal receiving pin group Z4 and the clock signal receiving pin group Z5 into separate regions (fourth sub-region Q24 and fifth sub-region Q25), and using a ground pin for physical and electrical isolation, interference from the data signal to the clock signal, and vice versa, can be minimized. This helps ensure the accuracy of data signal transmission and the stability of the clock signal. Furthermore, partitioning the data signal receiving pin group Z4 and the clock signal receiving pin group Z5 allows maintenance personnel to quickly determine whether the problem lies in the data transmission path or the clock signal path when display abnormalities occur, such as screen flickering or data errors, based on the signal type partitioning, thus accelerating the troubleshooting and repair process.

[0063] In this embodiment, adjacent data signal receiving pin groups Z4 are also isolated by ground pins. Data signal receiving pin groups Z4 typically contain multiple pairs of data lines (such as RGB channel data), each pair carrying a rapidly changing signal. The ground pins between adjacent data signal groups Z4 effectively create physical and electrical isolation barriers between each data "sub-channel." As a low-impedance path, the ground pins effectively absorb and dissipate the electromagnetic coupling energy generated between adjacent data signal groups. This significantly reduces crosstalk between data lines. Consequently, each data signal can be transmitted in a cleaner, less distorted form, directly improving the accuracy and reliability of data transmission. When differential transmission (such as LVDS) is used, the ground pins help to better isolate different differential pairs, maintain tight coupling within the differential pair, and reduce coupling with other differential pairs, thereby improving the noise immunity and common-mode rejection ratio of the differential signal.

[0064] In this embodiment, adjacent clock signal receiving pin groups Z5 are also isolated by ground pins. The clock signal is the "heart" of digital circuits, synchronizing all data transmission and operations. Any distortion, jitter, or offset of the clock signal can lead to data errors, abnormal display, or even complete system failure. Multiple clock signals may exist in an interface (e.g., clocks for different data channels or different display modes). Introducing ground pins between adjacent clock signal receiving pin groups Z5 effectively suppresses electromagnetic coupling and crosstalk between them. This means that the activity of one clock signal receiving pin group will not interfere with another, ensuring that the waveform of each clock signal is as pure and stable as possible. The ground pin provides a stable reference potential and an effective noise absorption path. This helps reduce common-mode noise and random jitter in the clock signal, ensuring the accuracy of the clock edge and thus providing a stable time base for data sampling.

[0065] It should be noted that the embodiments disclosed herein are only illustrated by an interface that includes 5 data signal receiving pin groups Z4 (RX_DATA0_P / N, RX_DATA1_P / N, RX_DATA2_P / N, RX_DATA3_P / N, and RX_DATA4_P / N) and 2 clock signal receiving pin groups Z2 (RX_CLK0_P / N and RX_CLK1_P / N), but are not limited thereto. The number of data signal receiving pin groups and clock signal receiving pin groups can be flexibly set according to the actual situation.

[0066] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the second region Q2 includes a sixth sub-region Q26, and the receiving pin includes a detection signal receiving pin RX_DET, which is located in the sixth sub-region Q26. The detection signal receiving pin corresponds to the detection signal transmitting pin TX_DET in the third sub-region Q13 of RX_DET. Having insertion / removal detection pins at both the transmitting and receiving ends allows for the establishment of a complete, bidirectional insertion / removal detection closed loop. The transmitting end (e.g., a transmitting card) sends an insertion / removal detection signal, and the receiving end (e.g., a receiving card 00) receives the signal and can acknowledge or send back confirmation, thereby more accurately determining the physical connection status. This bidirectional detection mechanism provides more reliable connection status verification. For example, if the transmitting end sends a detection signal and the receiving end does not receive it, or if the receiving end receives it but does not send back an acknowledgment signal, the system can determine that there is a connection problem, rather than simply a one-way signal loss. When a problem is detected, if the transmitting end acknowledges that it has sent an insertion / removal detection signal, but the receiving end does not receive it, this can quickly indicate that the problem may lie in the connection cable or the insertion / removal detection circuitry itself at the receiving end. This segmented detection capability helps to pinpoint the fault more accurately. By comparing the plug-in / plug-out detection signal (physical connection status) with the actual data / clock signal (transmission quality), engineers can clearly distinguish whether the physical connection is not established or the connection is established but there is a problem with signal transmission, thereby significantly reducing troubleshooting time.

[0067] When a detection signal receiving pin RX_DET is introduced into the interface, it can be isolated from other pins (such as data or clock) via a ground pin. Although the insertion / removal detection signal itself is low-speed, its level change can be relatively drastic when insertion / removal occurs, and the instantaneous level jump will generate some transient noise. Isolation via a ground pin can effectively prevent this transient noise from coupling to adjacent high-speed data or clock pins, avoiding interference with critical signals. Conversely, high-speed data and clock signals may also affect the insertion / removal detection signal through crosstalk, leading to false triggering or unstable detection. Ground isolation provides a "noise barrier" for the insertion / removal detection pin, ensuring the accuracy and stability of the detection signal and avoiding system errors caused by misjudging the insertion / removal status.

[0068] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the fifth sub-region Q25 is adjacent to the first region Q1, and the fourth sub-region Q24 is located between the fifth sub-region Q25 and the sixth sub-region Q26. This arrangement ensures that the sixth sub-region Q26 and the third sub-region Q13 are symmetrically arranged, both located on the outermost edge of the interface, while the second sub-region Q12 and the fifth sub-region Q25 are symmetrically arranged, located in the middle of the interface. The third sub-region Q13, where the detection signal receiving pin is located, is on the outermost edge of the interface. Since the detection signal is typically low-speed, placing it on the periphery and separating it from the internal high-speed signals effectively prevents transient changes (such as during insertion / removal) from interfering with the core high-speed signals.

[0069] The clock signal is the "pulse" of a high-speed digital interface, and its purity and stability are crucial for the synchronization and data sampling of the entire system. Positioning the fifth sub-region Q25, where the clock signal receiving pin group Z5 is located, in the center of the interface maximizes its surrounding protection by data signals and ground pins, reducing external electromagnetic interference. Furthermore, the central position of the interface provides the shortest and most balanced signal path to the receiver (or processor), helping to reduce clock signal attenuation, jitter, and phase shift, ensuring its waveform remains optimal during transmission.

[0070] Furthermore, by placing the data signal receiving pin group Z4 between the detection signal receiving pin group and the clock signal receiving pin group Z5, the data signal is surrounded by a high-priority clock signal, which is typically ground-isolated, and a relatively low-speed detection signal. The data signal receiving pin group Z4 also benefits from isolation from both the clock and detection regions, effectively reducing crosstalk between them.

[0071] The above embodiments illustrate a scheme in which the transmitting pins are concentrated in a first region and the receiving pins are concentrated in a second region. However, this disclosure is not limited thereto. In an optional embodiment of this disclosure, both the first region and the second region may also be provided with transmitting pins and receiving pins. For example, an interface includes a first region and a second region arranged along its length, with at least some transmitting pins and at least some receiving pins located in the first region, and at least some transmitting pins and at least some receiving pins located in the second region.

[0072] This embodiment illustrates another implementation of the interface, where both the first and second regions contain a portion of transmit pins and a portion of receive pins. In some high-speed interface standards, to meet stringent timing requirements, specific transmit pins and their corresponding receive pins may need to be as close as possible. Mixing transmit and receive pins in the same region can minimize the physical path of critical signals (such as high-bandwidth data pairs or clock signals). Placing closely related transmit and receive pins in the same region helps ensure a better match between their signal path lengths and electrical characteristics, thereby reducing transmission delay differences (timing deviations). In some cases, a mixed layout of transmit and receive pins may help distribute high-speed signals more evenly throughout the interface region, avoiding excessive signal density in certain areas that could lead to localized hotspots or more severe electromagnetic interference problems.

[0073] Optionally, a ground pin can be introduced for isolation between transmit and receive pins located in the same area. The ground pin acts as an isolation barrier, reducing crosstalk between transmit and receive pins in the same area.

[0074] When both the first and second regions are provided with transmit and receive pins, in one optional embodiment of this disclosure, the receive pins in the second region are symmetrically arranged with the transmit pins in the first region, and vice versa. Because the transmit and receive pins are symmetrically arranged between the two regions, any external or internal electromagnetic interference, such as common-mode noise or crosstalk, can be coupled symmetrically to the corresponding transmit and receive paths, thus more effectively suppressing common-mode noise and crosstalk and ensuring signal purity.

[0075] It should be noted that the accompanying drawings in this disclosure only illustrate an interface with 53 pins as an example, but this is not a limitation. In some other embodiments of this disclosure, the number of pins included in an interface can be set according to actual conditions. For example, it can be... Figure 4 Based on the example shown, remove some unused pins to bring the total number of pins to 51. Alternatively, in... Figure 4 Based on this, add some transmit and receive pins to increase the total number of pins to 96 or higher. Alternatively, in... Figure 4Based on this, some transmit and receive pins are removed, making the total number of pins 41, etc. This disclosure does not specifically limit this.

[0076] It should also be noted that the above embodiments are only illustrated using the example of the same number of transmit and receive pins in the same interface. In some other embodiments of this disclosure, the number of transmit and receive pins in the same interface may differ. For example, the number of transmit pins may be greater than the number of receive pins. This type of interface design is mainly used for data output, such as broadcasting information from a powerful control source to multiple downstream devices, or when a large amount of data needs to be transmitted in parallel to the next receiving card. Of course, another feasible approach is to have a greater number of receive pins than transmit pins. This type of interface design is mainly used for data input, such as receiving data from multiple upstream sensors or feedback units, or when information needs to be received in parallel from multiple channels. This design with a differentiated number of transmit and receive pins allows the interface to more accurately match the actual cascaded data flow requirements. For example, in an LED display system, if the data mainly flows in one direction (from the controller to the last cabinet), then there may be more transmit pins, or more receive pins when data needs to be aggregated at a specific point. The embodiments disclosed herein allow for the design of different types of interfaces to accommodate the functional requirements of different modules in an LED display device (e.g., some receiving cards may be primarily responsible for receiving central data, while others may need to send processed data to the next module), thus providing greater design freedom and allowing interfaces to be customized according to actual data throughput and directional requirements.

[0077] In summary, the technical solution provided by the embodiments of this disclosure has the following advantages compared with the prior art:

[0078] In the display device provided in this disclosure, both interfaces of the receiving card are bidirectional transmission interfaces, including both transmitting and receiving pins, enabling bidirectional signal transmission. Therefore, it is no longer limited by the unidirectional interface connection restrictions of related technologies, and the two receiving cards can be connected nearby through the bidirectional interface. In this disclosure, when connecting two receiving cards through the interface, one receiving card can connect to the adjacent receiving card. For example, in two adjacent columns of receiving cards, the bottom receiving card in one column can connect to the adjacent receiving card in the same row (i.e., the bottom receiving card in the other column), without needing to route the cable to the top of the other column to connect to the top receiving card. Therefore, by setting the interface as a bidirectional interface, the physically adjacent positions of the connected receiving cards can be ensured, greatly reducing or eliminating the need for long-distance, tortuous cables, large S-bends, and multiple sharp bends. This effectively shortens the length of the cabling between the two connected receiving cards, and the shorter, straighter wiring path simplifies the installation process, eliminating the need for installers to laboriously lay long cables or make multiple bends in confined spaces. Because the ribbon cable is shorter and has fewer bends, there will be less signal attenuation and interference, resulting in better signal quality and more stable display output. Furthermore, the reduced number of bends and shorter length of the ribbon cable lowers the stress on it, which also helps improve the overall reliability and lifespan of the display device.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display device comprising at least one display module, characterized in that, Also includes: Multiple cascaded receiving cards, wherein the receiving cards are connected to the display module; Each of the receiving cards includes two interfaces, and at least two of the receiving cards are connected to each other through the interfaces; the two connected receiving cards are physically adjacent to each other. Each of the interfaces includes multiple pins, including transmit pins and receive pins.

2. The display device according to claim 1, characterized in that, In the same interface, the number of transmitting pins is the same as the number of receiving pins.

3. The display device according to claim 2, characterized in that, In the same interface, the transmitting pin and the receiving pin are centrally symmetrically distributed.

4. The display device according to claim 1, characterized in that, In the same interface, the number of transmitting pins is different from the number of receiving pins.

5. The display device according to claim 1, characterized in that, The interface includes a first region and a second region arranged along its length, with the transmitting pin located in the first region and the receiving pin located in the second region.

6. The display device according to claim 5, characterized in that, The receive pins in the second region are arranged symmetrically with the transmit pins in the first region.

7. The display device according to claim 5, characterized in that, The first region includes a first sub-region and a second sub-region, and the transmitting pin includes multiple transmitting pin groups, including a data signal transmitting pin group located in the first sub-region and a clock signal transmitting pin group located in the second sub-region.

8. The display device according to claim 7, characterized in that, The first region further includes a third sub-region, and the transmitting pin includes a detection signal transmitting pin, which is located in the third sub-region.

9. The display device according to claim 8, characterized in that, The second sub-region is adjacent to the second region, and the first sub-region is located between the second sub-region and the third sub-region.

10. The display device according to claim 5, characterized in that, The second region includes a fourth sub-region and a fifth sub-region. The receiving pins include multiple receiving pin groups, including a data signal receiving pin group located in the fourth sub-region and a clock signal receiving pin group located in the fifth sub-region.

11. The display device according to claim 10, characterized in that, The second region includes a sixth sub-region, and the receiving pin includes a detection signal receiving pin located in the sixth sub-region.

12. The display device according to claim 11, characterized in that, The fifth sub-region is adjacent to the first region, and the fourth sub-region is located between the fifth sub-region and the sixth sub-region.

13. The display device according to claim 1, characterized in that, The interface includes a first region and a second region arranged along its length, with at least a portion of the transmitting pins and at least a portion of the receiving pins located in the first region, and at least a portion of the transmitting pins and at least a portion of the receiving pins located in the second region.

14. The display device according to claim 13, characterized in that, The receive pins in the second region are symmetrically arranged with the transmit pins in the first region, and the transmit pins in the second region are symmetrically arranged with the receive pins in the first region.

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